SUBSTRATE FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME

Abstract

The present invention provides a substrate for a semiconductor device and a semiconductor device using the same. The substrate for a semiconductor device comprises a ceramic supporting base plate formed by a polycrystalline aluminum nitride (AlN) sintered body; at least one silicon oxide layer formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layer is only formed from the sol-gel method and are not single crystalline; a first buffer layer comprising aluminum nitride (AlN) on the at least one silicon oxide layer with a thickness of 0.1˜10 μm; and a gallium nitride layer formed on the first buffer layer and having a single-crystal crystalline structure.

Claims

1. A substrate for a semiconductor device comprising: a supporting base plate, made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; at least one silicon oxide layer, formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layer is only formed from the sol-gel method and are not single crystalline; a first buffer layer, comprising aluminum nitride (AlN) formed on the at least one silicon oxide layer with a thickness of 0.1˜10 μm and having a preferred orientation (002) AlN crystalline structure; and a gallium nitride layer, formed on the first buffer layer and having a single-crystalline crystalline structure.

2. The substrate as claimed in claim 1, wherein the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm.

3. The substrate as claimed in claim 1, wherein the at least one silicon oxide layer includes 1˜10 layers.

4. The substrate as claimed in claim 1, further comprising: a titanium/platinum layer (titanium layer and/or platinum layer), formed on the at least one silicon oxide layer wherein the titanium layer has a thickness of 1˜100 nm and the platinum layer has a thickness of 5˜1000 nm.

5. A method for manufacturing a substrate for a semiconductor device comprising: providing a supporting base plate made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; performing a sol-gel process to form a silicon oxide layer at least one time wherein the sol-gel process is performed 1˜10 times, the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm and the at least one silicon oxide layer has a total thickness in a range of 10˜5000 nm; using a metal-organic chemical vapor deposition method to form a first buffer layer which comprises aluminum nitride (AlN) formed on the at least one silicon oxide layer; and using a metal-organic chemical vapor deposition method to form a gallium nitride layer formed on the first buffer layer and having a single-crystal crystalline structure.

6. The method as claimed in claim 5, further comprising: Using a metal-organic chemical vapor deposition or physical vapor deposition method to form a titanium/platinum layer (titanium layer and/or platinum layer) on the at least one silicon oxide layer wherein the titanium layer has a thickness of 1˜100 nm and the platinum layer has a thickness of 5˜1000 nm.

7. The method as claimed in claim 5, wherein the first buffer layer has a thickness of 0.1˜10 μm and has a preferred orientation (002) AlN crystalline structure.

8. A semiconductor device, comprising: a supporting base plate, made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; at least one silicon oxide layer, formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than that of the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layers are only formed from the sol-gel method and are not single crystalline; a first buffer layer, formed on the at least one silicon oxide layer wherein the first buffer layer is of aluminum nitride (AlN) and has a thickness of 10˜50000 nm and a preferred orientation (002) AlN crystalline structure; a gallium nitride layer, formed on the first buffer layer and having a single-crystal crystalline structure; a light emitting layer on the gallium nitride layer, wherein the light emitting layer is a n-type layer and has a single-crystal crystalline structure; and a p-type layer on the light emitting layer.

9. The semiconductor device as claimed in claim 8, wherein the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm and the at least one silicon oxide layer has a total thickness in a range of 10˜5000 nm.

10. The semiconductor device as claimed in claim 8, wherein the average roughness of the supporting base plate is equal to or more than 0.3 μm.

11. An insulated gate bipolar transistor, comprising: a supporting base plate, made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; at least one silicon oxide layer, formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than that of the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layers are only formed from the sol-gel method and are not single crystalline; a first buffer layer, formed on the at least one silicon oxide layer wherein the first buffer layer is of aluminum nitride (AlN) and has a thickness of 10˜50000 nm and a preferred orientation (002) AlN crystalline structure; an n-type layer, formed on the first buffer layer; an insulated gate bipolar transistor structure, formed on the n-type layer; and electrodes, formed on the insulated gate bipolar structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 1 of the invention.

[0012] FIG. 2 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 2 of the invention.

[0013] FIG. 3 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 3 of the invention.

[0014] FIG. 4 shows a schematic diagram illustrating a semiconductor device according to example 4 of the invention.

[0015] FIG. 5 shows a schematic diagram illustrating a semiconductor device according to example 5 of the invention.

[0016] FIG. 6 shows a schematic diagram illustrating a semiconductor device according to example 6 of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. The drawings are only schematic and the sizes of components may be exaggerated for clarity. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The common structures and elements that are known to everyone are not described in details to avoid unnecessary limits of the invention. Some preferred embodiments of the present invention will now be described in greater detail in the following.

[0018] A first embodiment of the invention discloses a substrate for a semiconductor device. The substrate comprises a ceramic supporting base plate, at least one silicon oxide layer, a first buffer layer and a gallium nitride layer. The supporting base plate is made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body. The at least one silicon oxide layer is formed on the base plate by a sol-gel method and the silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm. The silicon oxide layer is only formed from the sol-gel method and is not single crystalline. The first buffer layer comprises aluminum nitride (AlN) formed on the at least one silicon oxide layer with a thickness of 0.1˜10 μm and has a preferred orientation (002) AlN crystalline structure. The gallium nitride layer is formed on the first buffer layer and has a single-crystalline crystalline structure.

[0019] Preferably, the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm. As there are multiple silicon oxide layers, the silicon oxide layer which is the farthest away from the base plate preferable has an average roughness less than 10 nm or close to 0 nm. The at least one silicon oxide layer can have 1˜10 layers, and preferable 1˜5 layers.

[0020] Specifically, the method for forming the silicon oxide layer(s) is, for example, to use a spin-on glass coating(SOG) material such as hydrogen silsesquioxane (HSQ) to form a layer of silicon oxide and then dry the coating layer (for example, set under 120° C. for 2 min and heat to 345° C. by controlling the heating rate). When 2 layers of silicon oxide are to be formed, the above method is repeated twice. The thickness of one silicon oxide layer after dried is about in the range of 10˜100 nm.

[0021] The ceramic supporting base plate is made of aluminum nitride or is a ceramic base plate containing aluminum, for example formed by a polycrystalline aluminum nitride (AlN) sintered bulk body. The “bulk body” in the present specification means the thickness is thick, compared to its cross section, that is, in some case if necessary, the thickness could be greater than or close to the other two dimensions, the width and the length, which forms the surface the silicon oxide layer is formed thereon.

[0022] In one embodiment, the above mentioned substrate further comprises a titanium/platinum layer (Ti/Pt layer; titanium layer and/or platinum layer) formed on the at least one silicon oxide layer. The titanium layer has a thickness of 1˜100 nm and/or the platinum layer has a thickness of 5˜1000 nm. The “titanium/platinum layer” indicates the layer is formed by a titanium layer only, a platinum layer only or a layer including the titanium layer and platinum layer.

[0023] A second embodiment of the invention discloses a method for manufacturing a substrate for a semiconductor device. The method comprises the following steps, providing a supporting base plate made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; performing a sol-gel process to form a silicon oxide layer at least one time wherein the sol-gel process is performed 1˜10 times, the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm and the at least one silicon oxide layer has a total thickness in a range of 10˜5000 nm; using metal-organic chemical vapor deposition to form a first buffer layer which comprises aluminum nitride (AlN) formed on the at least one silicon oxide layer; and using metal-organic chemical vapor deposition to form a gallium nitride layer formed on the first buffer layer and having a single-crystal crystalline structure. The supporting base plate is made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body.

[0024] In the method for manufacturing a substrate for a semiconductor device, the sol-gel process to form a silicon oxide layer can be performed 1˜10 times, preferably 1˜5 times. Thus, the substrate according to the present invention has at least one silicon oxide layer. The silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm. The silicon oxide layer which is the farthest away from the supporting base plate has the smoothest surface, that is has the smallest average roughness among the multiple laminated layers of the silicon oxide layers.

[0025] The method for manufacturing a substrate for a semiconductor device, can further comprises a step of using metal-organic chemical vapor deposition or physical vapor deposition to form a titanium/platinum layer (titanium layer and/or platinum layer) on the at least one silicon oxide layer wherein the titanium layer has a thickness of 1˜100 nm and the platinum layer has a thickness of 5˜1000 nm.

[0026] The substrate manufactured using the method according to the present invention can be applied in a semiconductor device, such as a light emitting diode, insulated gate bipolar transistor, etc.

[0027] For example, a semiconductor device using the above mentioned substrate comprises a supporting base plate, made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; at least one silicon oxide layer formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than that of the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layers are only formed from the sol-gel method and are not single crystalline; a first buffer layer formed on the at least one silicon oxide layer wherein the first buffer layer is of aluminum nitride (AlN) and has a thickness of 10˜50000 nm and a preferred orientation (002) AlN crystalline structure; a gallium nitride layer formed on the first buffer layer and having a single-crystal crystalline structure; a light emitting layer on the gallium nitride layer wherein the light emitting layer is a n-type layer and has a single-crystal crystalline structure; and a p-type layer on the light emitting layer.

[0028] Specifically, FIG. 1 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 1 of the invention. As shown in FIG. 1, the substrate 1 comprises a ceramic supporting base plate 10, a silicon oxide layer(s) 12, a first buffer layer 13 and a gallium nitride layer 14. The silicon oxide layer(s) 12 was formed, for example, by using a spin-on glass coating (SOG) material such as hydrogen silsesquioxane (HSQ) to form a layer of silicon oxide by spin coating or spraying (sol-gel method) and then dry the coating layer (for example, set under 120° C. for 2 min and heat to 345° C. by controlling the heating rate). The thickness of one silicon oxide layer after dried is about in the range of 10˜100 nm, preferably 30˜100 nm. The first buffer layer 13 has a preferred orientation (002) MN crystalline structure. FIG. 2 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 2 of the invention. The substrates 2 and 2-1 in FIG. 2 have the similar structures as the substrate 1 in FIG. 1 except the silicon oxide layers 12-1 and 12-2. The substrate 2 in FIG. 2(a) has two layers of silicon oxide layers and the substrate 2-1 in FIG. 2(b) has three layers of silicon oxide layers. That is, the sol-gel process were repeated once or twice (preforming two or three times) for the substrates 2 and 2-1, respectively, during the method for manufacturing the substrate. In such a method, the surface of the substrate can be further smoothed. The gallium nitride layer 14 has a single crystalline structure.

[0029] FIG. 3 shows a schematic diagram illustrating a substrate for a semiconductor device according to example 3 of the invention. The substrate 3 additionally has a titanium/platinum layer 13-1 (Ti/Pt layer; titanium layer and/or platinum layer). The rest of the structure is the same as that in FIG. 1. The method to form the titanium/platinum layer 13-1 is for example to use metal-organic chemical vapor deposition or physical vapor deposition to deposit a titanium thin film and then form a platinum thin film to form the titanium/platinum layer 13-1. The titanium layer has a thickness of 1˜100 nm and the platinum layer has a thickness of 5˜1000 nm. The titanium/platinum layer 13-1 can assist the formation of single crystalline gallium nitride as the gallium nitride layer 14. However, the titanium/platinum layer 13-1 is optional. That is, in another embodiment, the substrate can have no titanium/platinum layer 13-1.

[0030] FIG. 4 shows a schematic diagram illustrating a semiconductor device according to example 4 of the invention. The semiconductor device 4 comprises a supporting base plate 100, at least one silicon oxide layer 120, a first buffer layer 130, an n-type layer 140, a p-type layer 160, a contact electrode 170 in contact with the p-type layer 160, a contact electrode 180 in contact with the n-type layer 140. The supporting base plate 100 has the same structure and composition as the supporting base plate 10. The at least one silicon oxide layer 120 has the same structure and composition as the at least one silicon oxide layer 12. The first buffer layer 130 has the same structure and composition as the first buffer layer 13. The n-type layer 140 can be formed by n-type doping the gallium nitride layer 14. For example, an n-type layer can be obtained by doping phosphorus to a gallium nitride epitaxial layer. The p-type layer 160 can be formed by p-type doping. For example, a p-type layer 160 can be obtained by a boron doped gallium nitride epitaxial layer.

[0031] FIG. 5 shows a schematic diagram illustrating a semiconductor device according to example 5 of the invention. The semiconductor device 4′ comprises a supporting base plate 100, a silicon oxide layer 120, a first buffer layer 130, an n-type layer 140, a light emitting layer 150, a p-type layer 160, a contact electrode 170 in contact with the p-type layer 160, a contact electrode 180 in contact with the n-type layer 140. The difference between the semiconductor device 4 and semiconductor device 4′ is that the light emitting layer 150 positioned between the n-type layer 140 and the p-type layer 160 is in the semiconductor device 4′. The light emitting layer 150 can be formed by a plurality of well layers and a plurality of barrier layer which are alternately laminated, that is, the laminate of one well layer, one barrier layer, one well layer, one barrier layer . . . is formed. Besides, the light emitting layer can be a quantum confinement layer formed by Al doped GaN with a high energy gap barrier and In (indium) doped GaN with a low energy gap barrier.

[0032] On the other hand, in examples 4 and 5, the silicon oxide layer 120 can be replaced by, for example, a plurality layers of silicon oxide layers 120-1, 120-2, 120-3 . . . . Besides, the modified example of examples 4 and 5 can have a titanium/platinum layer between the first buffer layer 130 and the n-type layer 140. The method to form the titanium/platinum layer is the same as the method to form titanium/platinum layer 13-1 described in the above.

[0033] Manufacturing a substrate for a semiconductor device specifically includes the following steps. A ceramic supporting base plate 10 (polycrystalline aluminum nitride) is coated with silicon oxide to form a silicon oxide layer 12 (planarization layer), then deposited with aluminum nitride to form a first buffer layer 13 (aluminum nitride thin film) by sputtering on the silicon oxide layer 12, and finally depositing a gallium nitride epitaxial layer by RF-MOMBE (radio-frequency metal-organic molecular beam epitaxy) on the first buffer layer 13. The supporting base plate 10 can be pre-treated, such as washed by acetone for 10 min, rinsed by iso-propyl alcohol (IPA) at 40° C. for 5 min to clean the surface of the supporting base plate 10 and heated by a hot plate at 120° C. for 5 min to dry moisture and IPA. The purpose of forming the silicon oxide layer by spin-coating is to fill holes on the surface of the polycrystalline aluminum nitride supporting base plate through filling the holes with the liquid phase of silicon oxide to smooth the surface or reduce the surface roughness. The reduction of the surface roughness can provide a better condition to deposit a gallium nitride thin film. To prevent cracking of aluminum nitride at 1000° C., the aluminum nitride supporting base plate can be annealed in a furnace at 1000° C. for 10 h at a heating rate controlled at 5° C./min and purged with nitrogen gas set to 100 sccm.

[0034] In the above semiconductor device, the silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm. The polycrystalline aluminum nitride supporting base plate has an average roughness more than 0.3 μm. Besides, preferably the average roughness of the silicon oxide layer is less than 10 nm, the total thickness of the silicon oxide layer is 100˜1000 nm and the average roughness of the aluminum nitride supporting base plate is more than 30 nm. More preferably, the average roughness of the silicon oxide layer is less than 5 nm, the total thickness of the silicon oxide layer is 100˜600 nm and the average roughness of the aluminum nitride supporting base plate is more than 30 nm.

[0035] As another example of the semiconductor device using the above mentioned substrate, the insulated gate bipolar transistor comprises: a supporting base plate, made of ceramics and formed by a polycrystalline aluminum nitride (AlN) sintered bulk body; at least one silicon oxide layer formed on the base plate by a sol-gel method wherein the sol-gel process is performed 1˜10 times, the average roughness of the top layer of the at least one silicon oxide layer is less than 25 nm and the at least one silicon oxide layer has a total thickness in a range of 10˜5000 nm, the silicon oxide layers are only formed from the sol-gel method and are not single crystalline; a first buffer layer formed on the at least one silicon oxide layer wherein the first buffer layer is of aluminum nitride (AlN) and has a thickness of 10˜50000 nm and a preferred orientation (002) AlN crystalline structure; an n-type layer formed on the first buffer layer; an insulated gate bipolar transistor structure formed on the n-type layer; and electrodes formed on the insulated gate bipolar transistor structure. The insulated gate bipolar transistor according to the present invention uses the substrate disclosed in the present invention and uses the insulated gate bipolar transistor structure which can be any insulated gate bipolar transistor structure according to the prior art. The insulated gate bipolar transistor structure includes p and n+ regions and the electrodes include emitter, gate and collector electrodes. FIG. 6 shows a schematic diagram illustrating a semiconductor device (insulated gate bipolar transistor; IGBT) according to example 6 of the invention. The semiconductor device 6 (IGBT 6) comprises a supporting base plate 100, a silicon oxide layer 120, a first buffer layer 130, an n-type layer 140, an insulated gate bipolar transistor structure including p and n+ regions, oxide layers 200 and electrodes including emitter, gate and collector electrodes. The substrate according to the present invention can also be used in a solar cell other than the above examples. For example, the semiconductor epitaxial layer of the solar cell can be deposited on the substrate according to the present invention to form the solar cell structure for solar cell application, which is also in the scope of the present invention.

[0036] In conclusion, according to the present invention, a substrate for a semiconductor device and a semiconductor device using the same are provided and the use of a polycrystalline aluminum nitride sintered bulk body provides a low-cost substrate instead of the high-cost single crystalline substrate. Besides, the present invention uses the sintered bulk body to increase the heat dissipation efficiency, forms the smooth silicon oxide layer (as a planarization layer) via solution coating on the rough surface of the sintered bulk body (polycrystalline aluminum nitride ceramic plate) and then grows the aluminum nitride epitaxial layer to provide a substrate ready for the epitaxial growth such as forming a GaN layer and light emitting layer. The process of manufacturing a substrate for a semiconductor device is simplified.

[0037] The foregoing description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to particularly preferred exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims. Each of the terms “first” and “second” is only a nomenclature used to modify its corresponding element. These terms are not used to set up the upper limit or lower limit of the number of elements.