High-Frequency Variable Load Inverter and Related Techniques

Abstract

Inverter systems, circuits and associated control techniques for providing efficient delivery of high-frequency (HF) power and radio-frequency (RF) power into variable load impedances while maintaining resistive/inductive loading of the constituent inverters for zero voltage switching (ZVS) are described. The inverter architecture and associated control techniques for providing efficient delivery of HF into variable load impedances includes a first inverter having an output coupled to an input of an immittance converter. An output of the immittance converter is coupled to a second inverter. The second inverter maybe either serially or parallel coupled between the output of the immittance converter and a load.

Claims

1. An inverter system having an output with the output configured to be coupled a load, the inverter system comprising: a first inverter having an output adapted to be directly connected to the load wherein the first inverter is coupled such that its output is coupled in series or in parallel with the load. an immittance converter having first and second ports; and a second inverter having an output coupled to the load through said immittance converter and wherein said immittance converter is configured such one of said first and second immittance converter ports is coupled in parallel or series with the load; and a controller coupled to provide control signals to said first and second inverters such that a capacitive susceptive portion of a load current is substantially provided by said second inverter via said immittance converter, and an inductive susceptive portion of load current is substantially provided by said first inverter.

2. The inverter system of claim 1 wherein the first inverter is coupled such that its output is in parallel with the load.

3. The inverter system of claim 1 wherein said first inverter is coupled such that its output is in series with the load.

4. The inverter system of claim 1 wherein said controller is coupled to said first and second inverters and configured to controlling at least one of the inverter output voltages by controlling an inverter bias voltage.

5. The inverter system of claim 1 further wherein said controller is coupled to provide control signals to said first and second inverters and is configured to dynamically vary each of the inverter output voltages and relative output phases of the first and second inverters to control the system.

6. The inverter system of claim 5 wherein said controller controls the first and second inverters such that each inverter always has presented thereto a load impedance having a resistive/inductive characteristic with the inductive loading component limited to that necessary for supplying any reactive component of a load current while at the same time realizing zero-voltage switching (ZVS) of both inverters.

7. The inverter system of claim 5 wherein any capacitive susceptive portion of load current is substantially provided by said second inverter via said immittance converter, and any inductive susceptive portion of load current is substantially provided by said first inverter.

8. The inverter system of claim 1 further comprising first and second preload networks coupled to respective ones of said first and second inverters and configured to provide zero voltage switching (ZVS) under resistive or resistive/inductive loading.

9. The inverter system of claim 1 wherein the immittance converter is realized as a T network.

10. In an inverter system having a first [Inverter A] directly coupled to a load with an output in parallel or in series with the load and a second inverter [Inverter B] coupled to the load through an immittance converter with one port of the immittance converter in parallel or series with the load, a method of operating the inverter system comprising: (a) setting an in-phase component of a voltage command (V.sub.AI) to the first inverter [Inverter A] to achieve a desired radio frequency (RF) power level at an RF output of the second inverter [Inverter B]; (b) setting a quadrature-phase component of a voltage command (V.sub.AQ) to the first inverter [Inverter A] to a first reference value; (c) setting a quadrature-phase component of a voltage command (V.sub.BQ) to the second inverter [Inverter B] such that the second inverter [Inverter B] drives a capacitive component of the first inverter [Inverter A] loading to substantially zero, and wherein the quadrature-phase component of a voltage command (V.sub.BQ) to the second inverter becomes zero when the load is inductive; and (d) setting an in-phase component of a voltage command (V.sub.BI) to the second inverter (Inverter B) such that the second inverter [Inverter B] delivers a real component of an output power which is within the voltage rating of second inverter [Inverter B] while maintaining an in-phase current sourced by first inverter [Inverter A] to be zero or positive.

11. The method of claim 10 wherein setting an in-phase component of a voltage command (V.sub.AI) to the first inverter comprises: setting a voltage amplitude of the in-phase component of the voltage command to the first inverter within a range of 0≦V.sub.AI≦V.sub.M to achieve a desired reference output power Po,ref, wherein V.sub.M corresponds to a maximum peak ac voltage rating of the first inverter.

12. The method of claim 10 wherein setting a quadrature-phase component of a voltage command to the second inverter comprises: setting an amplitude of a quadrature-phase component of a voltage command to the second inverter to be within the range of 0≦V.sub.BQ≦V.sub.M wherein V.sub.M corresponds to a maximum peak ac voltage rating of the first inverter.

13. The method of claim 12 wherein: setting a quadrature-phase component of a voltage command to the second inverter comprises setting the amplitude of a quadrature-phase component of a voltage command to the second inverter to drive capacitive components of the first inverter loading to zero, and wherein in response to the load being inductive, the quadrature-phase component of a voltage command to the second inverter becomes zero.

14. The method of claim 10 wherein setting the amplitude of the in-phase component of a voltage command to the second inverter comprises: setting the amplitude of the in-phase component of the voltage command to the second inverter within the range of 0 to (V.sub.M.sup.2−V.sub.BQ.sup.2).sup.1/2.

15. The method of claim 10 wherein the in-phase component of a voltage command to the second inverter is selected to drive an in-phase current I.sub.AI of the first inverter towards zero.

16. The method of claim 15 wherein selecting the in-phase component of a voltage command to the second inverter is limited by: (1) the requirement that the amplitude of the quadrature-phase component of a voltage command to the second inverter be within the range of 0≦V.sub.BQ≦V.sub.M; and (2) the allowed total operating voltage of the second inverter.

17. The method of claim 10 wherein the first reference value is zero.

18. A method for providing efficient delivery of high frequency (HF) power into a load having a variable load impedance, the method comprising: (a) controlling a first inverter to achieve a desired radio frequency (RF) power level at an RF output thereof; and (b) controlling a second inverter such that the second inverter drives substantially any capacitive component of the first inverter loading to substantially zero, and a quadrature-phase component of a voltage command provided to the second inverter becomes zero when the load is inductive such that the second inverter delivers a real component of the output power having an amplitude within its voltage rating while concurrently maintaining an in-phase current sourced by the first inverter to be substantially zero or positive such that the first and second inverters have presented thereto a load impedance having a resistive/inductive characteristic.

19. The method of claim 18 further controlling the first and second inverters to have an inductive loading component limited to that necessary for supplying any reactive component of a load current while at the same time realizing zero-voltage switching (ZVS) of both inverters.

20. The method of claim 19, wherein in response to the load having an inductive impedance characteristic, the second inverter delivers as much of the real component of the HF output power as possible within its voltage rating while concurrently maintaining the in-phase component of current sourced by the first inverter to be zero or positive

21. A method for providing efficient delivery of radio frequency (RF) power from an inverter into a load having a variable load impedance, the method comprising: (a) controlling a first inverter to achieve a desired RF power level at an RF output thereof; and (b) controlling a second inverter to drive capacitive components of first inverter loading to substantially zero.

22. The method of claim 21, wherein in response to the load being inductive a, quadrature-phase component of a voltage command provided to the second inverter becomes zero such that the second inverter delivers as much of a real component of the output power as possible within its voltage rating while concurrently maintaining a real power sourced by the first inverter to be substantially zero or positive.

23. The method of claim 21 further comprising controlling the first and second inverters such that each inverter always has presented thereto a load impedance having a resistive/inductive characteristic with the inductive loading component limited to that necessary for supplying any reactive component of a load current while at the same time realizing zero-voltage switching (ZVS) of both inverters.

24. A power delivery system comprising: a controller; an immittance converter; and a pair of inverters coupled to each other, said immittance converter and said controller and responsive to control signals provided by said controller such that each inverter always has presented thereto a load impedance having a resistive/inductive characteristic with the inductive component of the resistive/inductive characteristic limited to that necessary for supplying any reactive component of a load current while at the same time realizing zero-voltage switching (ZVS) of both inverters.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The foregoing features may be more fully understood from the following description of the drawings in which:

[0021] FIG. 1A is a block diagram of a variable load inverter;

[0022] FIG. 1B is a block diagram of an alternate embodiment of a variable load inverter;

[0023] FIG. 2 is a phasor diagram illustrating voltage and current relationships in the network of FIG. 1A for a load having inductive susceptance;

[0024] FIG. 3 is a phasor diagram illustrating voltage and current relationships in the network of FIG. 1B for a load having capacitive susceptance;

[0025] FIG. 4 is a plot of constraints vs. load conductance which illustrates voltage and current constraints determining allowable inverter operating range as a function of load conductance;

[0026] FIG. 5 is a plot of susceptance vs. conductance which illustrates the region of the load admittance plane that can be driven by the systems of FIGS. 1A, 1B for resistive/inductive loading of each inverter an assuming an output power of level P≦P.sub.r,i;

[0027] FIG. 6 is a plot of imaginary vs. real components of load admittance;

[0028] FIG. 7 is a plot of imaginary vs. real components of load admittance;

[0029] FIG. 8 is a Smith chart which illustrates achievable operating ranges for the system of FIG. 1A for different normalized output power levels (illustrating reflectance and admittance);

[0030] FIGS. 9A-9F are a series of phasor representations of system voltages and currents for different load admittances with V.sub.M=1, I.sub.M=1, Z.sub.0=1 and P=0.5 P.sub.r,i=025 using the control approach specified in Table I;

[0031] FIG. 10 is a schematic diagram of an example circuit implementation of a system having a high frequency variable load inverter architecture based on zero-voltage switching (ZVS) class D inverters with inductive preload networks and a lumped “T” implementation of an immittance converter; and

[0032] FIGS. 11A and 11B are plots of voltage vs. time for an inverter system which may be the same as or similar to the system of FIG. 10.

DETAILED DESCRIPTION

[0033] In general overview, described is a new architecture for HF variable-load inverters which Incorporates two ZVS soft-switched HF inverters and an immittance converter. The amplitudes and phases of inverters can be controlled so as to enable delivery of RF power into a wide range of varying load impedances (both capacitive and inductive loads) while maintaining resistive/inductive loading of the inverters for ZVS soft switching.

[0034] The concepts, systems, circuits and techniques described herein find use in a wide variety of applications requiring power in the HF (3-30 MHz) or VHF (30 MHz-300 MHz) frequency ranges. In general, concepts, systems, circuits and techniques described herein may find use in any application in which RF energy must be delivered to a load having a wide range of load impedances (i.e. the impedance characteristic of the load dynamically varies (i.e. changes while the system is operating). Such applications include, but are not limited to plasma generation, induction heating, wireless power, magnetic resonance imaging (MRI) applications. Some applications may be narrow-band (e.g., ISM band 6.78 MHz, 13.56 MHz, 27.12 MHz).

[0035] Referring now to FIG. 1A, an inverter system 10 for delivering power at high frequency (HF) e.g. frequencies in the range of 3 MHz-30 MHz comprises a pair of inverters 12a, 12b, (e.g. switched mode inverters) with a first one of the inverters 12a directly coupled to a load 14 and a second one of the inverters 12b coupled to the load 14 via an immittance converter 16. Immittance converter 16 is here illustrated as a T network provided from lumped components. Those of ordinary skill in the art will appreciate, of course, that immittance converter 16 may also be provided from a distributed circuit such as a quarter-wave transmission line section or from a combination of lumped and distributed circuit components.

[0036] For reasons which will become apparent from the description hereinbelow, the inverter system also comprises a controller coupled to provide control signals to the first and second inverters, to dynamically vary at least one of bias input voltages and/or ac output voltages and relative switching phases of the first and second inverters 12a, 12b so as to control the delivery of HF power to the load 14.

[0037] Thus, as illustrated in FIG. 1A, the two HF ZVS inverters 12a, 12b, are interconnected with immittance converter 16 and load network 14 and the amplitudes and relative phases of the inverters may be controlled to modulate output power and realize inductive/resistive loading of both inverters for ZVS soft switching under both capacitive and inductive loading.

[0038] Referring briefly to FIG. 1B, in which like elements of FIG. 1A are provided having like reference designations, a variant of the system described in FIG. 1A is shown. It should be appreciated that the alternative embodiment of FIG. 1B can be used to provide the same advantages as the embodiment of FIG. 1A in terms of inverter loading. It should also be appreciated that in the embodiment of FIG. 1B, the location of inverter 12a and the load may be exchanged to make the inverter ground referenced.

[0039] One difference between the embodiments of FIGS. 1A and 1B is that the architecture of the system illustrated in FIG. 1A is more suitable for supplying loads requiring large transient currents at limited voltage, while systems having the architecture illustrated in FIG. 1B are advantageous for supplying loads requiring large transient voltages at limited current. In either case, however, one inverter (i.e. inverter 12a in the illustrative embodiments) is directly connected to the load (with an output in series or parallel with the load), while the other inverter (i.e. inverter 12b) is coupled to the load via an immittance converter (with one port of the immittance converter in parallel or series with the load).

[0040] Referring again to FIG. 1A, for modeling purposes and to explain the operation of the proposed architecture, the inverters are treated as ideal ac voltage sources having controllable amplitude and phase. In practice, one can utilize any type of inverter suitable for HF operation under resistive/inductive loading, and amplitude control of the individual inverters can be realized through any suitable means (e.g., supply voltage modulation, phase-shift or outphasing control, pulse-width modulation, etc.).

[0041] The immittance converter 16 serves to losslessly transform the voltage (current) delivered by inverter 12b at the first port of the immittance converter into an appropriately-scaled and phase-shifted current (voltage) at the second port of the immittance converter and vice versa, according to the following rule:

[00001]$\begin{array}{cc}\left[\begin{array}{c}{V}_A\\ I_Z\end{array}\right]=\left[\begin{array}{cc}0& -j.Math.Z_0\\ \frac{-j}{Z_0}& 0\end{array}\right].Math.\left[\begin{array}{c}{V}_B\\ I_B\end{array}\right]& \left(1\right)\end{array}$

[0042] An immittance converter is thus a two-port lossless, reciprocal network that swaps between voltages and currents at its ports (with a 90° delay). For example, a quarter-wave transmission line is an immittance converter. Also, many lumped circuit implementations of an immittance converter are available. An immittance converter “inverts” impedances—e.g. an Impedance Z.sub.L on one port is presented as (looks like) an impedance value of Z.sub.0.sup.2/Z.sub.L at the other port.

[0043] Thus, immittance converter 16 has a characteristic such that the immittance converter swaps voltages and currents between its ports, consequently transforming between capacitive and inductive impedances. Such a characteristic is important to the operation of a power delivery system having the proposed architectures described herein. In practice, the immittance converter can be realized with a variety of passive lumped networks and at sufficiently high frequencies can be realized with a quarter-wave transmission line. Immittance converter 16 may, for example, be the same as or similar to the type described in (M. Borage, K. V. Nagesh, M. S. Bhatia and S. Tiwari, “Resonant Immittance Converter Topologies,” IEEE Transactions on Industrial Electronics, Vol. 58, No. 3, pp. 971-978, March 2011).

[0044] The amplitudes and relative phase of the two inverters 12a, 12b are used to control both the total output power and the effective loading admittance presented at the ports of each of the two inverters. It should be appreciated that as used herein the phrase “effective loading admittance,” refers to the complex ratio of current to voltage at an inverter output port with both inverters active. In particular, the relative phases and amplitudes of inverters 12a, 12b are controlled in a manner such that each inverter 12a, 12b are presented a resistive/inductive effective load regardless of the nature of the actual system load, facilitating zero-voltage switching (ZVS) of the inverters.

[0045] With reference to prior art systems, it is noted that a classical Doherty rf power amplifier utilizes an immittance converter to combine power from two sources into a single output and has an architecture which provides in-phase combining of power from linear power amplifiers into a specified resistive load (yielding resistive load modulation of the amplifiers),

[0046] The present architecture, on the other hand, utilizes both amplitude and phase shift control among switched-mode inverters to achieve both power control and desirable resistive/inductive loading of the constituent inverters across a wide range of load impedances.

[0047] For simplicity of explanation, inverter controlled is explained in terms of the conductive and susceptive components of the load admittance.

[0048] Which inverter supplies the susceptive component of the load current depends upon whether the susceptive component is inductive or capacitive. In the case where the load is inductive, the susceptive portion of the load current I.sub.LB is provided by inverter 12a, while the conductive portion of the load current I.sub.LG is split between inverters 12a, 12b.

[0049] In contrast, when the load is capacitive, the susceptive portion of the load current I.sub.LB is provided by inverter 12b (after processing through the immittance converter), while the conductive portion of the load current I.sub.LG is split between inverters 12a, 12b. In each case, the relative phases of inverters 12a, 12b can also be set to ensure a degree of inductive loading for each inverter to provide soft switching we treat each of these cases in turn.

[0050] To further explain the broad concepts sought to be protected herein, and with reference to FIGS. 2 and 3, consider an inductive/resistive load as illustrated by the phasor relationship of FIG. 2 and only use of inverter 12a. In this case, inverter 12a is inductively loaded (for ZVS). Next, with reference to FIG. 3, consider a capacitive/resistive load and only use of inverter 12b. Through action of the immittance converter 16, the capacitive/resistive load appears as an inductive/resistive load to Inverter 12b. Thus, inverter 12b is also is inductively loaded (for ZVS).

[0051] Consider next the interaction of the two inverters (neglecting load). With appropriate phasing between components of V.sub.A, V.sub.B, both inverters see an inductive loading component owing to the action of the immittance converter. This provides reactive currents facilitating ZVS switching of both inverters. Thus, operated together, inverter 12a supplies reactive current for inductive loads and inverter 12b supplies reactive current for capacitive loads while one or both inverters may deliver real power. Thus, the two inverters 12a, 12b can cover a wide load admittance range with inductive loading (for ZVS) of both inverters.

[0052] Referring now to FIG. 2, as noted above, a phasor relationship for the example where a load (e.g. load 14 in FIG. 1A) is conductive/inductive is shown. The load voltage may be directly set by the voltage of inverter 12a, with amplitude V.sub.A (as identified by reference numeral 20) set to a level sufficient to drive the desired average load power. It should be noted that a zero-phase reference for voltage V.sub.A is arbitrarily assumed. The phase of inverter 12b voltage V.sub.B is set to an angle (θ.sub.B+90°) ahead of the phase of inverter 12a voltage V.sub.A owing to the action of the immittance converter 16, the current I.sub.B lags V.sub.B by θ.sub.B, providing a degree of inductive loading for inverter 12b. Angle θ.sub.A is selected to be as small as possible commensurate with providing both inverters 12a, 12b, with desirable operating waveforms (e.g. waveforms which provide sufficient inductive currents to each inverter for ZVS switching.)

[0053] In the case where the inverters 12a, 12b are designed such that they can achieve ZVS with a purely resistive load, θ.sub.B can be set to zero. Owing to the action of the immittance converter 16, current I.sub.Z leads V.sub.A by θ.sub.B. The amplitude V.sub.B is selected such that the sum of the real components of I.sub.Z and I.sub.A are sufficient to support the necessary load conductance current I.sub.LG. The imaginary component of I.sub.A is negative, representing the difference between the susceptive component of the load current I.sub.LB and the imaginary component of current I.sub.Z. I.sub.A thus lags V.sub.A, providing inverter 12a with a degree of inductive loading.

[0054] The detailed achievable operating range is described below, however, FIG. 2 illustrates that for any conductive or conductive/inductive load admittance, each of the two inverters 12a, 12b can be provided with desirable loading conditions (e.g., for ZVS soft switching).

[0055] Referring now to FIG. 3, as noted above, a phasor diagram illustrates an example in which a load is conductive/capacitive. As described above in conjunction with FIG. 2, the load voltage and output power are again set by the voltage of inverter 12a and the phase of inverter 12b voltage V.sub.B is likewise set to an angle (θ.sub.B+90°) ahead of V.sub.A. In this case, however, the phase θ.sub.B is selected in conjunction with the amplitude of V.sub.B such that the imaginary component of related current I.sub.Z provides the susceptive portion of the load current I.sub.LB along with any necessary additional current to enable soft switching of the two inverters.

[0056] Owing to this additional (imaginary axis) current, the phase of current I.sub.A lags V.sub.A by a small amount (θ.sub.A), thereby providing an inductive loading component to inverter 12a. For an inverter which is preloaded for ZVS soft switching under resistive load, θ.sub.A can be zero, while without preloading, θ.sub.A can be just sufficiently large in conjunction with the amplitude of I.sub.A that the resulting susceptive component of I.sub.A suffices to realize a voltage transition for zero-voltage switching.

[0057] Likewise, phase θ.sub.B provides a sufficient inductive loading component for inverter 12b. If the inverters 12a, 12b, are designed to achieve desired operation into a resistive load, phase θ.sub.B can be selected such that θ.sub.A is zero, making current I.sub.A in phase with V.sub.A).

[0058] As can be seen from FIGS. 2 and 3, by utilizing the appropriate controls, loads with either capacitive or inductive susceptive components can be supplied with the proposed system while maintaining resistive/inductive loading of each inverter (e.g., for ZVS soft switching). A more detailed control strategy by which the above goals can be realized is described below.

[0059] Of interest in the proposed architecture is the achievable load admittance range that can be driven as a function of inverter VA rating and specified output power. In the example provided herein, focus is placed on the symmetric case in which the two inverters 12a, 12b are substantially identical, each with an ac output current amplitude rating Wand ac output voltage amplitude rating V.sub.M and with characteristic impedance of the immittance converter of Z.sub.0=V.sub.M/I.sub.M=1/Y.sub.0. Each inverter 12a, 12b thus has an ideal rated output power of P.sub.r,i=½.Math.−V.sub.M.Math.I.sub.M, though this output power is only achievable into a single effective load impedance. Consequently, the system 10 is typically operated at a power level which is well below P.sub.r,i.

[0060] Described below is an analytical treatment of the range of load admittances that can be driven within inverter operating limits as a function of the desired output power (normalized to the power rating of a single inverter P.sub.r,i). The analysis starts by establishing the load conductance range over which a single inverter can drive a desired average power P assuming zero susceptance. Equations 2 and 3 show the required load voltage amplitude [V.sub.OUT, equal to V.sub.A in FIG. 1A] and conductive load current amplitude [I.sub.L] necessary to drive power P as a function of conductance G.

[00002]$\begin{array}{cc}.Math.V_{\mathrm{OUT}}.Math.=\frac{\sqrt{2.Math..Math.P}}{\sqrt{G}}& \left(2\right)\\ .Math.I_G.Math.=\sqrt{2.Math..Math.P}.Math.\sqrt{G}& \left(3\right)\end{array}$

[0061] Referring now to FIG. 4, the above relationships are illustrated along with constraints on inverter voltage and current, with curve 34 corresponding to the current constraint and curve 36 corresponding to the voltage constraints. G.sub.MIN denotes the minimum load conductance for which power P can be delivered within the specified inverter voltage rating V.sub.M. For lower conductances, power P cannot be delivered without exceeding the inverter voltage limit. Similarly, G.sub.MAX1 is the maximum load conductance for which a single inverter can deliver sufficient current to drive power P within inverter current rating I.sub.M. Given that two inverters are available to deliver power, there is an extended load conductance range over which a specified power P could be delivered by the system. G.sub.MAX2 shows the maximum conductance for which both inverters operating together (e.g. inverters 12a, 12b) could deliver the current required to provide power P (at zero susceptance). These load conductance values can be found to be

[00003]$\begin{array}{cc}{G}_{\mathrm{MIN}}=\frac{2.Math..Math.P}{V_M^2}.Math..Math.G_{\mathrm{MAX}.Math..Math.1}=\frac{I_M^2}{2.Math..Math.P}.Math..Math.G_{\mathrm{MAX}.Math..Math.2}=4.Math.\frac{I_M^2}{2.Math..Math.P}& \left(4\right)\end{array}$

[0062] The real part of the load admittance range that can be supported is defined by G.sub.MIN, G.sub.MAX1, G.sub.MAX2. To find the complete admittance range that is supportable, first consider the typical case of power levels P≦P.sub.r,i for which G.sub.MIN≦G.sub.MAX1<G.sub.MAX2. For operation between G.sub.MIN and G.sub.MAX1, the system is not constrained by voltage, and the real (conductive portion) of load current can be completely supported by one of the two inverters. This leaves the second inverter to support the susceptive portion of load current up to its maximum rated current I.sub.M. Based on the current delivery constraint of the second inverter, the necessary current can be provided for susceptances having magnitudes up to a value B.sub.MAX:

[00004]$\begin{array}{cc}.Math.B_{\mathrm{MAX}}.Math.=\frac{I_M}{\sqrt{2.Math..Math.P}}.Math.\sqrt{G}& \left(5\right)\end{array}$

[0063] Operating between G.sub.MAX and G.sub.MAX2, current contributions from both inverters are needed to support the conductive component of the load current. This leaves a portion of current from one of the inverters remaining to support susceptive load components, which may be shown to yield a maximum susceptance amplitude for this range of conductances:

[00005]$\begin{array}{cc}.Math.B_{\mathrm{MAX}}.Math.=\sqrt{\frac{G}{2.Math..Math.P}.Math.\left(2.Math..Math.I_M.Math.\sqrt{2.Math..Math.\mathrm{PG}}-2.Math..Math.\mathrm{PG}\right)}& \left(6\right)\end{array}$

[0064] Referring now to FIG. 5, a plot of susceptance vs. conductance which illustrates a region of a load admittance plane that can be driven by the systems having an architecture in accordance with the concepts described herein for resistive/inductive loading of each inverter (assuming an output power level of P≦P.sub.r,i) is shown (i.e. FIG. 5 illustrates a load admittance range at power P within an inverter ac output voltage and having current ratings V.sub.M and I.sub.M).

[0065] As can be seen from FIG. 5 when load conductance G reaches G.sub.MAX2, all available current is being delivered to the load conductance, and the achievable susceptance is zero as indicated by reference numeral 50.

[0066] To further delineate the achievable operating range, the largest susceptance magnitude that can be driven while providing power P to the load conductance is found. This susceptance magnitude is denoted as B.sub.BP, and the load conductance (between G.sub.MAX1 and G.sub.MAX2) at which this peak susceptive drive capability is reached as G.sub.BP. Differentiating Equation (6) with respect to G and setting this derivative to zero yields:

[00006]$\begin{array}{cc}{B}_{\mathrm{BP}}=\frac{3.Math.\sqrt{3.Math..Math.I_M^2}}{8.Math..Math.P}.Math..Math.G_{\mathrm{BP}}=\frac{9.Math..Math.I_M^2}{8.Math..Math.P}& \left(7\right)\end{array}$

This boundary result is likewise indicated in FIG. 5.

[0067] It will be appreciated that the range of load admittances that can be driven is a function of an average power P, with lower power corresponding to a wider region of admittances.

[0068] Referring now to FIG. 6, a plot of imaginary vs. real components of load admittance illustrates a region of the load admittance plane that can be driven by a system provided in accordance with the concepts described herein for different normalized output power levels. The achievable operating range of load admittances that can be driven (normalized to a characteristic admittance Y.sub.0=1), is illustrated for specified output powers of 0.5 (curve 52), 1 (curve 54) and 1.5 (curve 56) times P.sub.r,i (i.e. FIG. 6 illustrates an achievable range of load admittances at different power levels −1.5P.sub.r,i, 1.0P.sub.r,i, 0.5P.sub.r,i).

[0069] From curves 52, 54, 56, it can be seen that the load admittance range that can be driven increases rapidly with reductions in commanded power (or, equivalently, with increases in the volt-ampere ratings of the inverters relative to a desired output power). Thus, from FIG. 6 it can be thus be appreciated that to enable operation over a wide range of load admittances, one may oversize the VA ratings of the inverters.

[0070] The boundaries of the operating region are directly linked to inverter constraints. For example, the vertical boundary of a minimum load conductance directly expresses the voltage output limit of inverter 12a and current output limit of inverter 12b, while the boundaries to the right reflect complementary constraints.

[0071] At power levels below P.sub.r,i G.sub.MIN<G.sub.MAX1, the region is delineated just as illustrated in FIG. 5, with the area encompassed diminishing as P increases at P=P.sub.r,i, G.sub.MIN=G.sub.MAX1, while for higher values of P, G.sub.MIN>G.sub.MAX1, such that the inverter voltage limit increasingly constrains the achievable admittance region. The area of allowable admittances continues to decrease with increasing power collapsing to a single point Y=2Y.sub.0 at P=2P.sub.r,i.

[0072] Referring now to FIG. 7, a plot of imaginary vs. real components of load admittance illustrates regions of a load impedance plane that can be driven by a system provided in accordance with the concepts described herein for different normalized output power levels. It should be noted that the same constraints on allowable load range as a function of power described above can be expressed as regions of the load impedance plane. Results are shown normalized to a characteristic impedance Z.sub.0=1. It should be appreciated that the curves of FIG. 7 reflect the same operating boundaries as FIG. 6.

[0073] Referring now to FIG. 8, Smith chart results are shown normalized to a characteristic admittance of Y.sub.0=1. This plot reflects the same operating boundaries as FIGS. 6 and 7.

[0074] It can be observed that the admittance regions encompassed in FIGS. 5, 6 and 8 are symmetric about zero susceptance, and the impedance regions in FIG. 7 are symmetric about zero reactance. It should, of course, be appreciated that the operating ranges can be made nonsymmetric by inclusion of “offset” reactance(s) in shunt and/or series with the load.

[0075] Also, it should be noted that the operating boundaries indicated in FIGS. 5-8 assume the use of inverters which operate well under all of pure resistive, pure inductive, and combination resistive/inductive loading. Thus, to meet these boundaries, the inverters must be able to efficiently supply a purely resistive load. Inverters requiring external inductive loading can be accommodated by adjusting the relative inverter phases such that each inverter sees a sufficient inductive load through action of the immittance converter (as illustrated in FIGS. 2 and 3), while incurring a degree of reduction in the operating boundaries. In the description below, it is assumed that the inverters are designed to operate with any combination of resistive and inductive loading within their voltage and current ratings.

[0076] There are many high-frequency inverter designs that can operate well within the constraints of resistive/inductive loading described above. One option is a ZVS class D or class DE inverter having either a matching network or inductive pre-load network such that it can operate with soft switching into a variable resistive/inductive load. Another option is an appropriately-designed single-switch inverter (e.g., class E, class φ.sub.2, etc.). While “classical’ Class-E inverter designs impose significant constraints on loading to maintain ZVS, some single-switch inverters are suitable for variable-load operation, In particular, the variable-load class E design and other single-switch inverter designs introduced in (L. Roslaniec, A. S. Jurkov, A. Al Bastami and D. J. Perreault “Design of Single-Switch Inverters for Variable Resistance/Load Modulation Operation,” IEEE Transactions on Power Electronics, Vol. 30, No. 6, pp. 3200-3214, June 2015.) can operate with low loss across a wide range of resistive, resistive/inductive and inductive loads. While some systems only explicitly treat design for variable load resistance, the resulting inverter designs can maintain ZVS and low loss for resistive/inductive and pure inductive loads as well, so long as the active switch has an antiparallel diode or equivalently provides reverse conduction. Modulation of the individual inverter output amplitudes (as necessary for the proposed architecture) may be relatively easily realized by modulating the inverter supply voltages (e.g., using dc-dc converters to vary the inverter dc supplies, also known as “drain modulation”), though other means are also possible.

[0077] It should be noted that the operating points on the boundaries of FIGS. 5-8 reflect the most extreme loads that can be driven at the specified power levels by inverters operating within maximum peak ac voltage and current rating V.sub.M and I.sub.M. As such, there is typically only one set of control commands (inverter amplitudes and phases) that can support these operating points. By contrast, there are many combinations of amplitudes and phases that can support many interior points (as one could divide power between the two inverters in various ways for these interior points). This, in turn, means that there are multiple ways the system can be controlled to achieve the desired output. Many of these control means share the above-described characteristic of which inverter takes on the supply of the susceptive portion of the load current (after compensating any offset components in the susceptive range) depending upon whether this susceptive portion is inductive or capacitive. Described below is one possible control strategy.

[0078] One possible control strategy (explained herein in terms of in-phase and quadrature components of inverter voltages) may be as follows. An in-phase component of V.sub.A (denoted as V.sub.AI) sets an output power level, provides any inductive portion of load current and provides any conductive portion of load current not supplied by V.sub.B. A quadrature component of V.sub.A (denoted as V.sub.AQ) is set to a reference value (e.g. zero). An in-phase component of V.sub.B (denoted as V.sub.BI) is set to provide an amount of a conductive portion of a load current within inverter voltage limit V.sub.BI≦(V.sub.M.sup.2−V.sub.BQ.sup.2).sup.1/2. In preferred embodiments, the in-phase component of V.sub.BI is set to provide as much of the conductive portion of the load current as possible within inverter voltage limit. A quadrature component of V.sub.B (denoted as V.sub.BQ) provides capacitive portions of the load current and sets additional reactive current for ZVS switching. Such control strategy results in an inverter system capable of dynamically adjusting to varying impedances of a load coupled to an output thereof.

[0079] As noted above, the example control strategy described herein is based upon in-phase and quadrature components of the voltage common as provided to inverters 12a, 12b. This I/Q representation carries the same information as the magnitudes and phases of the inverter voltages. The I/Q relationships can be defined such that the quadrature component for each inverter leads its in-phase component by 90°, and the in-phase component of inverter 12b leads that of inverter 12a by 90°. The in-phase component of inverter 12a (V.sub.AI) may be arbitrarily defined to be the desired output voltage phase reference such that the voltage of inverter 12a is defined by its in-phase component and has zero quadrature component (V.sub.AQ=0). The in-phase component of inverter 12b (V.sub.BI) may be defined as leading the in-phase component of inverter A by 90°. Thus, in terms of phasors. V.sub.A=V.sub.AI and V.sub.B=−V.sub.BQ+jV.sub.BI. To achieve the desired control goals, the in-phase and quadrature components of the two inverters may be selected as shown in Table I (i.e. Table I shows a control method based upon setting in-phase and quadrature components of the inverter voltages to achieve the desired output power and inverter loading characteristics).

TABLE-US-00001 TABLE I V.sub.AI Set amplitude (within 0 ≦ V.sub.AI ≦ V.sub.M) to achieve desired reference output power P.sub.o,ref (V.sub.AI is thus used to set output power). V.sub.AQ Set to zero (by definition of the desired phase of V.sub.A). V.sub.BQ Set within 0 ≦ V.sub.BQ ≦ V.sub.M to drive I.sub.AQ to zero (V.sub.BQ is thus used to drive any capacitive component of inverter A loading to zero, and becomes zero when t load is inductive). V.sub.BI Set within 0 ≦ V.sub.BI ≦ (V.sub.M.sup.2 − V.sub.BQ.sup.2).sup.1/2 to drive I.sub.AI towards 0.sup.+ limited by the requirement on V.sub.BQ above and by the allowed total operating voltage of invert (V.sub.BI is thus set such that inverter B will deliver as much of the real component the output power as possible within the voltage rating of inverter B and while maintaining the current sourced by inverter A to be zero or positive).

[0080] This control technique (supported by appropriate measurements and feedback compensators) can provide a desired output and inverter loading characteristics across the operating range.

[0081] FIGS. 9A-9F are a series of phasor representations of system voltages and currents for different load admittances with V.sub.M=1, I.sub.M=1, Z.sub.0=1 and P=0.5 P.sub.r,i=0.25 using the control approach specified in Table I. The load admittances correspond to some of the boundary operating points specified in FIG. 5;

[0082] Thus, FIGS. 9A-9F show the resulting inverter voltages and current phasors using the above-described control technique for six of the boundary operating points indicated in FIG. 5 (six load admittances at P=0.5.Math.P.sub.r,i with normalized inverter ratings V.sub.M=1, I.sub.M=1 and Z.sub.0=1). The relationships between inverter 12a voltage (V.sub.A) and inverter 12b current (I.sub.B), and inverter 12b voltage (V.sub.A) and immittance converter output current (I.sub.Z) are apparent.

[0083] FIGS. 9A-9F illustrate that inverters 12a, 12b both maintain resistive/inductive loading for all operating points. Moreover, it can be seen that any capacitive component of load current is provided by inverter 12b through the immittance converter 16, while any inductive component of load current is provided directly by inverter 12a.

[0084] Referring now to FIG. 10, an example circuit implementation of a system 70 having a high frequency variable load inverter architecture provided from zero-voltage switching (ZVS) class D inverters 72, 74 with inductive preload networks 76, 78 and a lumped “T” implementation of an immittance converter 79. Component values for operating at a switching frequency of 13.56 MHz are shown in Table II.

TABLE-US-00002 TABLE II V.sub.INA 0-160 V.sub.DC V.sub.INB C.sub.SA1, C.sub.SA2, C.sub.SB1, C.sub.SB2 1 μF L.sub.SSA L.sub.SSB 100 nh Q.sub.A1, Q.sub.A2, Q.sub.B1, Q.sub.B2 R.sub.ON = 50 mΩ C.sub.OSS = 40 pf L.sub.TA, L.sub.TB, L.sub.PFA, L.sub.PFB 470 nH C.sub.TA, C.sub.TB, C.sub.PFA, C.sub.PFB 294 pF L.sub.IC1, L.sub.IC2 117 nH C.sub.IC 117 nF

[0085] The example circuit of FIG. 10 thus represents a simulated 13.56 MHz inverter system having component values as shown in Table II (i.e. Table II shows component values for the example inverter system of FIG. 10).

[0086] The ZVS class D inverters (operated with 11 ns switching deadtime) utilize the inductive preload networks to provide ZVS soft switching under resistive or resistive/inductive loading. The immittance converter has a characteristic impedance of 10Ω and is realized as a T network. Notional values for V.sub.M and I.sub.M are 100 V and 10 A, respectively, though these are only approximate in practice. The inverter devices are modeled as having 50 mΩ on-state resistance and 400 pF output capacitance, commensurate with available devices. The inverters are each provided with series and parallel filter networks 77, 78 tuned at the switching frequency for harmonic reduction. The dc input voltages and relative switching phases of the two inverters are dynamically varied to control the system in accordance with the concepts and techniques described herein. Such control may be implemented through control system 75 and bias system 76 (e.g. a drain voltage bias system).

[0087] FIGS. 11A, 11B are LTSPICE simulations showing the behavior of an inverter system which may be the same as or similar to the example system of FIG. 10 having the values show in Table II. This system operations at a frequency 13.56 MHz with a system characteristic admittance of Y.sub.0=0.1.

[0088] Referring now to FIGS. 11A and 11B, shown are example simulation results for a system which may be the same as or similar to the system of FIG. 10. Curves 81, 82 correspond to the unfiltered outputs of the ZVS soft-switched inverters 12a 12b and curves 84 and 86 are their respective currents (providing resistive and/or inductive loading of the inverters). Curve 88 corresponds to the output (load) voltage.

[0089] FIG. 11A illustrates operation with a resistive/capacitive load comprising a 5Ω resistor in parallel with a 2.34 nF capacitor (representing an admittance of approximately 0.2+0.2j). This operating point is achieved with dc input voltages V.sub.IN,A=80 V and V.sub.IN,B=160 V, with the fundamental output voltage component of inverter B leading that of inverter A by approximately 180°.

[0090] FIG. 11B illustrates operation for a resistive/inductive load comprising a 5Ω resistor in parallel with a 58.7 nH inductor (representing an admittance of approximately 0.2-0.2j). This operating point also utilizes dc input voltages V.sub.IN,A=80 V and V.sub.IN,B=160 V, but with the fundamental output voltage component of inverter 12b (FIG. 1A) leading that of inverter 12a by approximately 90°. These two operating points correspond approximately to those of the middle column in FIG. 9 (with values appropriately renormalized for V.sub.M, I.sub.M and Z.sub.0).

[0091] It can be seen that zero-voltage switching of each inverter is maintained for both the resistive/capacitive and resistive/inductive load cases. Moreover, the output waveforms match well with the underlying theory. For the resistive/capacitive case, the ac output voltage has a peak value of 48.6 V and the system delivers 234 W, while in the resistive/inductive case the peak ac output voltage is 48.8 V, and the system delivers 238 W. These simulation results illustrate the ability of the architecture and control/operating techniques described herein to operate with a wide range of load impedances including both capacitive and inductive loads and show how such a system might work with practical inverter designs.