METHOD OF MAKING SUPERCONDUCTING INTERCONNECTIONS

Abstract

The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising:

a) a first substrate, which carries at least one first line of a first superconducting material;
b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via;
c) at least one second line above said first via and in contact with the latter.

Claims

1. Interconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising: a) a first substrate, which carries at least one first line of a first superconducting material; b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via; c) at least one second line above said first via and in contact with the latter.

2. Device according to claim 1, each superconducting material being chosen from V.sub.3Si, CoSi.sub.2, Nb.sub.3Ge, TiN, NbN, Al, and TaN.

3. Device according to claim 1, the first superconducting material being of aluminum, and the second superconducting material being TiN or TaN.

4. Device according to claim 1, further comprising a dielectric material covering of said first line.

5. Device according to claim 4, the dielectric material being: of low dielectric constant k<7; and/or chosen from the following list: SiN, SiCN, SiO.sub.2, SiCOH or porous SiCOH.

6. Device according to claim 1, comprising several first lines, with a pitch less than 500 nm, preferably comprised between 56 nm and 500 nm.

7. Device according to claim 1, comprising at least one first line of thickness H.sub.1 comprised between 40 nm and 300 nm.

8. Device according to claim 1, said at least one first line having a thickness H.sub.1 and at least one via, in contact with said first line, being of thickness comprised between H.sub.1 and H.sub.1/2.

9. Device according to claim 1, said first substrate comprising at least part of a circuit, for example at least one contact stud, with which said first line is in contact.

10. Method for producing lines of superconducting material and vias in contact with those lines, comprising: a) forming, on a first substrate, a first superconducting layer of at least one superconducting material, of a thickness at least equal to the thickness of a first line and of a first via; b) etching said first superconducting layer to form first of all at least one first via; c) then etching said layer to form at least one first line between said first substrate and said first via; the first superconducting layer comprising a first sub-layer of a first superconducting material, in which said first line is produced and a second sub-layer of a second superconducting material, different from the first superconducting material, in which said via is produced. d) forming at least one second line above said first via and in contact with the latter.

11. Method according to claim 10, each superconducting material being chosen from V.sub.3Si, CoSi.sub.2, Nb.sub.3Ge, TiN, NbN, Al, and TaN.

12. Method according to claim 10, the sub-layer of said first superconducting material, in which said first line is produced, being of aluminum, and the second sub-layer of said second superconducting material being of TiN or TaN.

13. Method according to claim 10, the etching of the first superconducting layer to form said via being stopped on the upper surface of said first sub-layer of a first superconducting material.

14. Method according to claim 10, step d) of forming at least one second line comprising forming in advance at least one second via, then the second line.

15. Method according to claim 10, further comprising, between steps c) and d), a step of covering said first line with a dielectric material, forming a second substrate.

16. Method according to claim 15, the dielectric material having a low dielectric constant k<7.

17. Method according to claim 15, the dielectric material being chosen from the following list: SiN, SiCN, SiO.sub.2, SiCOH or porous SiCOH.

18. Method according to claim 15, step d) comprising: depositing on the second substrate a second superconducting layer of at least one superconducting material, of thickness at least equal to the thickness of a second line, and optionally a second via; etching the second superconducting layer to optionally form the second via, and to form at least said second line, in contact with said first via.

19. Method according to claim 10, step b) being carried out by partial etching of said first superconducting layer, leaving part of that layer intact.

20. Method according to claim 10, step c) being carried out by lithography with total etching of the exposed parts of said first superconducting layer reaching the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Example embodiments of the invention will now be described with reference to the accompanying drawings in which:

[0060] FIG. 1A-FIG. 1E and FIG. 2A-FIG. 2F show examples of known methods;

[0061] FIG. 3A-FIG. 3H show an example of a method and a device according to the invention;

[0062] FIG. 4A-FIG. 4B show a variant of a method and a device according to the invention;

[0063] In the Figures similar or identical technical members are designated by the same reference numbers.

DETAILED DESCRIPTION OF EMBODIMENTS

[0064] An example embodiment of a method according to the invention is shown in FIGS. 3A-3G.

[0065] On a substrate S, for example of dielectric material such as SiO.sub.2, and which may comprise at least part one of or components of a circuit, for example contact studs 102, a deposit is made of a layer 104 of superconducting material (FIG. 3A).

[0066] This layer 104 has a thickness preferably equivalent or equal to the sum of the thicknesses: [0067] of the track(s) or line(s), to produce in the part referenced 104.sub.1 of that layer 104, which form the first metallic level (or lower level); [0068] and of the via or vias to produce in the part referenced 104.sub.2 of that same layer 104 and which will be in contact with the line or lines.

[0069] In this example: [0070] the superconducting material may be niobium (Nb), but other examples of superconducting materials that may be employed are given further on; [0071] the layer 104 is constituted by a single superconducting material, but it will be seen further on that it may comprise a first layer, or sublayer, of a first superconducting material for producing the lower metallic level and a second layer, or sublayer, of a second superconducting material, different from the first superconducting material, this second layer being in direct contact with the first layer and being provided for the production of the via or vias; this case is shown by the dashed lines in FIGS. 3A-3G, the first layer or sublayer of a first superconducting material being identified by the reference 104.sub.1, the second layer or sublayer of a second superconducting material, being identified by the reference 104.sub.2.

[0072] Next on this layer 104 is produced a resist (hard or of resin) 106 for the purpose of carrying out etching of the via or vias.

[0073] After partial etching of the layer 104 and removal of the resist, the structure of FIG. 3B is thus obtained which comprises the metallic core of the vias 108 (etched in the part referenced 104.sub.2 of the initial layer 104) on the part referenced 104.sub.1 in which the lower lines will be produced (after a later etching step). As this step is carried out by partial etching of the superconducting layer, it leaves part thereof intact.

[0074] In this case, mentioned above and also described in connection with FIGS. 4A-4B, in which the layer 104 comprises 2 sublayers of different superconducting material, the reference 104.sub.1 of FIGS. 3A and 3B designates the first layer or sublayer of a first superconducting material (for producing the lower metallic level) and the reference 104.sub.2 designates the second layer or sublayer of a second superconducting material, different from the first superconducting material, this second layer being in direct contact with the first sublayer and being provided for production of the via or vias.

[0075] For the purpose of achieving the definition of the lines of the lower level, the part referenced 104.sub.1 of the initial layer 104 as well as the metallic core of the vias 108 will be covered with a resin layer 110 and with a layer 112 of BARC “Bottom Anti Reflectant Coating”) or SOC (“Spin on Carbon”) type. A photolithography step (FIG. 3C) then of etching the resin layer 110 (FIG. 3D) but also of the part referenced 104.sub.1 of the initial layer 104 (FIG. 3E) enable definition of the metallic track or tracks 114 of the lower level. At least one such metallic track 114 may be in contact with, for example, at least part of or a component of a circuit produced in the substrate S, for example a contact stud or studs 102. This step may be carried out by lithography with total etching of the exposed parts of the superconducting layer, reaching the substrate S. The etching of this step may be followed by a cleaning step. The assembly may be covered with a dielectric layer 124 (FIG. 3F), which is then planarized (FIG. 3G) for example down to the level of the upper part of the via(s). A new substrate 120 is then formed of which the upper surface 117 comprises alternating zones of dielectric material and zones of superconducting material. A second track (or line) level (or upper level) of superconducting material may be formed on this upper surface 117, these tracks being in direct contact with the vias 108. Concerning the dielectric material 124, it preferably has a low dielectric constant k; for example k<7. It may be chosen from the following list SiN, SiCN, SiO.sub.2, SiCOH or porous SiCOH. If a porous “Low-k” material is chosen, the technique according to the invention does not give rise to modification of the properties of that material, contrary to the known “damascene” approach (described above in connection with FIGS. 1A-1E).

[0076] The steps described above (FIGS. 3A-3G) may be iterated on that substrate 120: it is also possible to deposit on the upper surface 117 an upper metallic level comprising at least one metallic layer 116 (FIG. 3G) of superconducting material the thickness of which will depend on the presence or absence of another level of vias above that upper metallic level. The sequence of steps described above starting from FIG. 3A can therefore be performed again; for example, a step of photolithography, then etching makes it possible to form the tracks 126, 126′ of the upper level (FIG. 3H). Optionally, one are more of the vias 128, 128′ are formed prior to the tracks 126, 126′. FIG. 3H represents a structure (an interconnect device) obtained with a method according to the invention, in which vias 108 connect lines 114 of a metallic level below and lines 126, 126′ of a metallic level above.

[0077] The superconducting material used in a method or a device according to the invention may be niobium; as a variant that may for example be chosen from the following list (after each material, one or 2 possible techniques for deposit have been indicated, a possible temperature or temperature range for that deposit, and, possibly, a annealing temperature range): V.sub.3Si (PVD at ambient temperature, annealing at 500-900° C.), CoSi.sub.2 (PVD at ambient temperature, anealing at 600-900° C.), Nb.sub.3Ge (PVD at ambient temperature), TiN (PVD or CVD at a temperature between ambient temperature and 400° C.), NbN (PVD or CVD at ambient temperature, annealing at 500-900° C.), Al (PVD at a temperature between ambient temperature and 450° C.), TaN (PVD at ambient temperature between 20 and 90° C. or CVD, with a maximum temperature of 400° C.).

[0078] In this example embodiment and in the variant or variations disclosed below: [0079] in the case of TiN, the etching is for example carried out by chlorine chemistry; reference may also be made to the paper by J. Tonotani et al. entitled “Dry etching characteristics of TiN film using Ar/CHF.sub.3, Ar/Cl.sub.2, and Ar/BCl.sub.3 gas chemistries in an inductively coupled plasma” which appeared in the Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 21, 2163 (2003); doi: 10.1116/1.1612517; [0080] in the case of NbN, the etching is for example carried out by a fluorine-containing gas (for example based on SF.sub.6 or CF.sub.4).

[0081] Reference may also be made to the paper by Qing Zhong, et al. entitled “Study of Dry Etching Process Using SF.sub.6 and CF.sub.4/O.sub.2 for Nb/Nb.sub.xSi.sub.1-x/Nb Josephson-Junction Fabrication” 978-1-4673-0442-9/12/$31.00, July 2012, IEEE, p. 46-47; CPEM Digest (Conference on Precision Electromagnetic Measurements), DOI:10.1109/CPEM. 2012.6250653.

[0082] The person skilled in the art will adapt the etching conditions indicated above and/or in the papers cited above to etch the various levels and/or to etch other materials, including for the variants disclosed below.

[0083] As a variant of the method or a device according to the invention described above, it is possible to use 2 different superconducting materials (FIG. 4A) for one or more of the superconducting layers 104, 116: [0084] a first superconducting material to form a first layer 204.sub.1, for the purpose of producing lines of the lower metallic layer. [0085] and a second superconducting material, different from the first, to form a second layer 204.sub.2, for producing the vias.

[0086] Each of these superconducting materials may be chosen from the list given above. This variant enables better control for stopping etching (by the upper surface of the layer 204.sub.1) when etching the vias 208. The sequence of the steps is then that described above in connection with FIGS. 3B-3G and leads to the structure of FIG. 4B, in which the superconducting material constituting the vias 208 is in direct contact with the superconducting material constituting the lines 214. It is then possible to form an upper metallic level comprising a metallic layer 216 (FIG. 4B) of a superconducting material or comprising 2 superconducting sub-layers (as in FIG. 4A) of which the total thickness will depend on the presence or absence of a via upper level. A structure identical to that of FIG. 3H can thus be obtained with 2 different superconducting materials, for example one for the metallic tracks 114, 126, 126′ and the other for the vias 108, 128, 128′. Advantageously, the second superconductor of the second sub-layer 204.sub.2 for producing the vias is TiN or TaN. As a matter of fact, the inventors have found that the superconducting quality of these materials degraded much less than that of other superconducting materials with the reduction in the dimensions of the material. One or other of these materials thus maintains good properties once the vias have been formed. Furthermore, these materials can easily be integrated in a microelectronics process. Advantageously in association with the TiN or TaN, the first superconducting material 204.sub.1 provided to form the lines is aluminum which is also easy to integrate and which has good etching selectivity relative to that of TiN or TaN.

[0087] Whatever the embodiment of a method or a device according to the invention: [0088] fewer steps are implemented than the technique described above in connection with FIGS. 2A-2F; as a matter of fact, in the course of a same step, a metallic level is defined (in a single superconducting material or in two superconducting materials) in which lines are formed, but also vias; [0089] a superconducting member of inverted T-shape is produced (see FIGS. 3F and 3G in which the tracks of the lower line are formed after the vias), the technique described above in connection with FIGS. 1D and 1E first of all producing a T-shape, with, furthermore, the problems of contact already referred to above and linked to the presence of the layer 18, 18′.

[0090] Whatever the embodiment implemented, the invention makes it possible to produce: [0091] a plurality, or even a network, of tracks having a pitch p (FIG. 3E) less than 1 urn, or less than 500 nm, or comprised between 500 nm and 56 nm, or which may go down to approximately 50 nm; this pitch p measures, parallel to the surface of the substrate S on which the metallic deposit is produced, the distance between identical or similar parts of 2 neighboring tracks; [0092] one or more tracks 114 having a height H.sub.1, measured from said surface of the substrate and perpendicular to it, comprised for example between 40 nm and 300 nm; the vias 108 may have a height H.sub.2, measured in the same direction, comprised between H.sub.1 and H.sub.1/2.