ENHANCED TL-TCAM LOOKUP-TABLE HARDWARE SEARCH ENGINE

Abstract

An enhanced TL-TCAM lookup-table hardware search engine includes a plurality of enhanced TL-TCAM cell circuits. There are m enhanced TL-TCAM cells circuits connected in parallel to form a sub-segment circuit. The word line WL, match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together, the match line ML is connected to the drain electrode of an N-type transistor N15, ML_x is connected to the gate electrode of the N-type transistor N15, and the source electrode of the N-type transistor N15 is connected to ground, ML_x is connected to the drain electrode of an N-type transistor N14, the source electrode of the N-type transistor N14 is connected to ground, and the gate electrode of the N-type transistor N14 is connected to the signal line OneX_in-Sement_b, a plurality of sub-segment circuits are connected in parallel to form a word circuit.

Claims

1. An enhanced TL-TCAM lookup-table hardware search engine, wherein each word circuit comprises a plurality of enhanced TL-TCAM cell circuits, and each of the enhanced TL-TCAM cell circuits comprises four memory cells MC1-MC4 and thirteen N-type transistors N1-N13; the memory cell MC adopts a bistable circuit structure, a stored value is located at a T terminal of the memory cell MC, and an F terminal of the memory cell MC stores its “NOT” value; a gate electrode of the N-type transistor N1 is connected to OneX, a source electrode of the N-type transistor N1 is connected to a power supply, and a drain electrode of the N-type transistor N1 is connected to a source electrode of the N-type transistor N2; a drain electrode of the N-type transistor N2 is connected to a source electrode of the N-type transistor N3, a drain electrode of the N-type transistor N3 is connected to ML_X, and a gate electrode of the N-type transistor N3 is connected to a source electrode of the N-type transistor N7; a gate electrode of the N-type transistor N7 is connected to XSL_11, and a drain electrode of the N-type transistor N7 is connected to an F terminal of the memory cell MC2; a T terminal of the memory cell MC2 is connected to a source electrode of the N-type transistor N6, a gate electrode of the N-type transistor N6 is connected to LSL_11, and a drain electrode of the N-type transistor N6 is connected a source electrode of the N-type transistor N5; a gate electrode of the N-type transistor N5 is connected to LSL_00, and a drain electrode of the N-type transistor N5 is connected to a T terminal of the memory cell MC1, and an F terminal of the memory cell MC1 is connected to a source electrode of the N-type transistor N4; a gate electrode of the N-type transistor N4 is connected to XSL_00, and a drain electrode of the N-type transistor N4 is connected to a source electrode of the N-type transistor N12; a gate electrode of the N-type transistor N12 is connected to a word line WL, and a drain electrode of the N-type transistor N12 is connected to a bit line BL1; the drain electrode of the N-type transistor N4 is connected to the source electrode of the N-type transistor N7 through an MA line; a gate electrode of the N-type transistor N2 is connected to a source electrode of the N-type transistor N8, a gate electrode of the N-type transistor N8 is connected to XSL_10, and a drain electrode of the N-type transistor N8 is connected to an F terminal of the memory cell MC3; a T terminal of the memory cell MC3 is connected to a source electrode of the N-type transistor N9, a gate electrode of the N-type transistor N9 is connected to LSL_10, and a drain electrode of the N-type transistor N9 is connected to a source electrode of the N-type transistor N10; a gate electrode of the N-type transistor N10 is connected to LSL_01, a drain electrode of the N-type transistor N10 is connected to a T terminal of the memory cell MC4; the F terminal of the memory cell MC3 is connected to a source electrode of the N-type transistor N11, a gate electrode of the N-type transistor N11 is connected to XSL_01, and a drain electrode of the N-type transistor N11 is connected to a source electrode of the N-type transistor N13; a gate electrode of the N-type transistor N13 is connected to the word line WL, a drain electrode of the N-type transistor N13 is connected to a bit line BL2; the drain electrode of the N-type transistor N11 is connected to the gate electrode of the N-type transistor N2 through a MB line; the source electrode of the N-type transistor N5 is connected to the drain electrode of the N-type transistor N9 through a match line ML; m enhanced TL-TCAM cells circuits are connected in parallel to form a sub-segment circuit, wherein m is a positive integer; the word line WL, the match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together; the match line ML is connected to a drain electrode of the N-type transistor N15, ML_x is connected to a gate electrode of the N-type transistor N15, and a source electrode of the N-type transistor N15 is connected to ground; ML_x is connected to a drain electrode of the N-type transistor N14, a source electrode of the N-type transistor N14 is connected to ground, and a gate electrode of the N-type transistor N14 is connected to a signal line OneX_in-Sement_b; and the plurality of sub-segment circuits are connected in parallel to form a word circuit.

2. The enhanced TL-TCAM lookup-table hardware search engine according to claim 1, wherein LSL_00, LSL_01, LSL_10, LSL_11, XSL_00, XSL_01, XSL_10, XSL_11, and OneX of a word circuit array are respectively connected to a decoder decode_SLW, and a truth table of the decoder decode_SLW is as follows: TABLE-US-00009 (SLW#1, SLW#2) LSL_00 LSL_01 LSL_10 LSL_11 OneX XSL_00 XSL_11 XSL_01 XSL_10 No (0, 0) 1 — — — — — — — — G_X (0, 1) 1 — — — — — — — (1, 0) 1 — — — — — — (1, 1) 1 — — — — — two (G_X, G_X) — — — — — — — — — G_Xs one (0, G_X) — — — — 1 1 — 1 — G_X (1, G_X) — — — — 1 — 1 — 1 (G_X, 0) — — — — 1 1 — 1 (G_X, 1) — — — — 1 — 1 1 — “—” in the table represents “0”; when there is no G_X in (SLW #1, SLW #2), only one line in LSL_00, LSL_01, LSL_10, and LSL_11 is selected, values of LSL_00, LSL_01, LSL_10, and LSL_11 are 1, OneX, XSL_00, XSL_01, XSL_10, and XSL_11 are all 0, N-type transistors connected thereto are turned on, and a value of the T terminal of corresponding MC cell is selected to the ML; if LSL_00=1, a value of MC1.T is selected to the ML, marked as ML<=MC1.T; if LSL_11=1, ML<=MC2.T; if LSL_10=1, ML<=MC3.T; if LSL_01=1, ML<=MC4.T; in this case, OneX=0, the N-type transistor N1 is turned off, and ML_X is floating, marked as ML_x<=FLOAT; when ML_x<=FLOAT, if ML=1, it is indicated that the value stored in the selected MC cell MC.F=1, that is, a search result of the enhanced TL-TCAM cell circuit is match HIT; and if ML=0, the search result of the enhanced TL-TCAM cell circuit is mismatch MISS; when there are two G_Xs in (SLW #1, SLW #2), LSL_00, LSL_01, LSL_10, LSL_11, XSL_00, XSL_01, XSL_10, XSL_11, and OneX are all 0, the N-type transistor N1 is turned off, ML_X<=FLOAT; the N-type transistor N5, the N-type transistor N6, the N-type transistor N9, and the N-type transistor N10 are turned off, ML<=FLOAT; in this case, the search result of the enhanced TL-TCAM cell circuit is match HIT; when there is one G_X in (SLW #1, SLW #2), LSL_00, LSL_01, LSL_10, and LSL_11 are all 0; the N-type transistor N5, the N-type transistor N6, the N-type transistor N9, and the N-type transistor N10 are turned off, ML<=FLOAT; when only one of XSL_00 and XSL_11 is selected: if XSL_00 is selected, the N-type transistor N4 is turned on, and MA<=MC1.F; if XSL_11 is selected, the N-type transistor N7 is turned on, and MA<=MC2.F; when only one of XSL_10 and XSL_01 is selected: if XSL_10 is selected, the N-type transistor N8 is turned on, and MB<=MC3.F; if XSL_01 is selected, the N-type transistor N11 is turned on, and MB<=MC4.F; OneX=1, and the N-type transistor N1 is turned on; in this case, if the MA line and the MB line are both 1, the N-type transistor N3 and the N-type transistor N2 are both turned on, ML_x<=1, which indicates the search result of the enhanced TL-TCAM cell circuit is mismatch MISS; if one of the MA line and the MB line is 0, or both are 0 at this time, and then at least one of the N-type transistor N2 and the N-type transistor N3 is turned off, ML_x<=FLOAT, which indicates the search result of the enhanced TL-TCAM cell circuit is match HIT.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIGS. 1(a) and 1(b) are schematic diagrams of the TCAM cell, wherein FIG. 1(a) is a NOR-type TCAM cell, and FIG. 2(b) is a NAND-type TCAM cell;

[0024] FIGS. 2(a) and 2(b) are schematic diagrams of the TCAM word circuit structure, wherein FIG. 2(a) is a NOR-type match line and FIG. 2(b) is a NAND-type match line;

[0025] FIG. 3 is a simple CAM block diagram;

[0026] FIG. 4 is a schematic diagram of a low parasitic capacitance TCAM structure;

[0027] FIGS. 5(a) and 5(b) are schematic diagrams of the lookup-table search engine structure, wherein FIG. 5(a) is a NOR-type lookup-table search engine cell structure, FIG. 5(b) is a NAND-type lookup-table search engine cell structure;

[0028] FIG. 6 is a diagram of an ETL-TCAM circuit structure (ETL-TCell);

[0029] FIG. 7 is a simplified symbol diagram of the ETL-TCAM circuit structure;

[0030] FIG. 8 is a circuit structure diagram of the MC circuit, the MC circuit adopts a bistable circuit structure;

[0031] FIG. 9 is a sub-segment circuit composed of a plurality of ETL-TCells;

[0032] FIG. 10 is a structure diagram of a word circuit formed by connecting a plurality of sub-segment circuits in parallel;

[0033] FIG. 11 is a schematic circuit diagram of two conventional TCAM cells (only the memory cell part is simply drawn, and others are omitted);

[0034] FIG. 12 is an ETL-TCell search line generated by search line decoding (decode_SLW) of a conventional TCAM cell.

DETAILED DESCRIPTION

[0035] As shown in FIG. 6 and FIG. 7, an enhanced TL-TCAM lookup-table hardware search engine is provided. Each word circuit includes a plurality of enhanced TL-TCAM cell circuits. Each enhanced TL-TCAM cell circuit includes four memory cells MC1-MC4 and thirteen N-type transistors N1-N13. The memory cell MC adopts a bistable circuit structure. The stored value is located at the T terminal of the memory cell MC, and the F terminal of the memory cell MC stores its “NOT” value. The gate electrode of the N-type transistor N1 is connected to OneX, the source electrode of the N-type transistor N1 is connected to the power supply, the drain electrode of the N-type transistor N1 is connected to the source electrode of the N-type transistor N2, the drain electrode of the N-type transistor N2 is connected to the source electrode of the N-type transistor N3, the drain electrode of the N-type transistor N3 is connected to ML_X, the gate electrode of the N-type transistor N3 is connected to the source electrode of the N-type transistor N7, the gate electrode of the N-type transistor N7 is connected to XSL_11, the drain electrode of the N-type transistor N7 is connected to the F terminal of the memory cell MC2, the T terminal of the memory cell MC2 is connected to the source electrode of the N-type transistor N6, the gate electrode of the N-type transistor N6 is connected to LSL_11, the drain electrode of the N-type transistor N6 is connected the source electrode of the N-type transistor N5 the gate electrode of the N-type transistor N5 is connected to LSL_00, the drain electrode of the N-type transistor N5 is connected to the T terminal of the memory cell MC1, the F terminal of the memory cell MC1 is connected to the source electrode of the N-type transistor N4, the gate electrode of the N-type transistor N4 is connected to XSL_00, the drain electrode of the N-type transistor N4 is connected to the source electrode of the N-type transistor N12, the gate electrode of the N-type transistor N12 is connected to the word line WL, the drain electrode of the N-type transistor N12 is connected to the bit line BL1, the drain electrode of the N-type transistor N4 is connected to the source electrode of the N-type transistor N7 through the MA line, thegate electrode of the N-type transistor N2 is connected to the source electrode of the N-type transistor N8, the gate electrode of the N-type transistor N8 is connected to XSL_10, the drain electrode of the N-type transistor N8 is connected to the F terminal of the memory cell MC3, the T terminal of the memory cell MC3 is connected to the source electrode of the N-type transistor N9, the gate electrode of the N-type transistor N9 is connected to LSL_10, the drain electrode of the N-type transistor N9 is connected to the source electrode of the N-type transistor N10, the gate electrode of the N-type transistor N10 is connected to LSL_01, the drain electrode of the N-type transistor N10 is connected to the T terminal of the memory cell MC4, the F terminal of the memory cell MC3 is connected to the source electrode of the N-type transistor N11, the gate electrode of the N-type transistor N11 is connected to XSL_01, the drain electrode of the N-type transistor N11 is connected to the source electrode of the N-type transistor N13, the gate electrode of the N-type transistor N13 is connected to the word line WL, the drain electrode of the N-type transistor N13 is connected to the bit line BL2 the drain electrode of the N-type transistor N11 is connected to the gate electrode of the N-type transistor N2 through the MB line, the source electrode of the N-type transistor N5 is connected to the drain electrode of the N-type transistor N9 through the match line ML.

[0036] There are m (m is a positive integer) enhanced TL-TCAM cells circuits connected in parallel to form a sub-segment circuit. The word line WL, the match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together. The match line ML is connected to the drain electrode of the N-type transistor N15, the ML_x is connected to the gate electrode of the N-type transistor N15, the source electrode of the N-type transistor N15 is grounded, the ML_x is connected to the drain electrode of the N-type transistor N14, the source electrode of the N-type transistor N14 is connected to ground, the gate electrode of the N-type transistor N14 is connected to the signal line OneX_in-Sement_b, refer to FIG. 9 for details. The plurality of sub-segment circuits is connected in parallel to form a word circuit, refer to FIG. 10 for details.

[0037] The source of data stored in the ETL-TCAM can refer to the data conversion method in the lookup-table TCAM and the conventional TCAM [2-4]. It is assumed that the data is converted and stored in each ETL-TCell cell.

[0038] The search line generation method in the ETL-TCell cell is as follows:

[0039] A conventional TCAM cell consists of two SRAM cells, and can be inputted through two search lines SL1 and SL2, such as the TCAM cell in FIG. 4. Suppose the input search word SLW is represented by (SL1, SL2), and input SLW=0=(SL1, SL2)=(0, 1), input SLW=1=(SL1, SL2)=(1, 0), input SLW=global X=(SL1, SL2)=(0, 0). For convenience, we abbreviate global X as G_X.

[0040] In the present invention, one ETL-TCell cell corresponds to two conventional TCAM cells. Moreover, the search line of one ETL-TCell cell consists of LSL, XSL and OneX. For the convenience of comparison, comparison of two conventional TCAM cells and one ETL-TCell is provided. The circuit diagram of two conventional TCAM cells is as shown in FIG. 11, only the memory cell part is simply drawn, and the corresponding search line representations are shown in Table 2.

TABLE-US-00002 TABLE 2 Search line representations of two conventional TCAM cells TCAM Cell#1 (TCell#1) TCAM Cell#2 (TCell#2) SLW (SL1, SL2) SLW (SL1, SL2) 0 (0, 1) 0 (0, 1) 1 (1, 0) 1 (1, 0) G_X (0, 0) G_X (0, 0)

[0041] As shown in FIG. 12, LSL_00, LSL_01, LSL_10, LSL_11, XSL_00, XSL_01, XSL_10, XSL_11, and OneX of a word circuit array are respectively connected to a decoder decode_SLW, and a truth table of the decoder decode_SLW is as shown in Table 3:

TABLE-US-00003 TABLE 3 Truth table of decoder decode_SLW (SLW#1, SLW#2) LSL_00 LSL_01 LSL_10 LSL_11 OneX XSL_00 XSL_11 XSL_01 XSL_10 No (0, 0) 1 — — — — — — — — G_X (0, 1) 1 — — — — — — — (1, 0) 1 — — — — — — (1, 1) 1 — — — — — 2 (G_X, G_X) — — — — — — — — — G_X 1 (0, G_X) — — — — 1 1 — 1 — G_X (1, 0_X) — — — — 1 — 1 — 1 (G_X, 0) — — — — 1 1 — 1 (G_X, 1) — — — — 1 — 1 1 — “—” in the table represents “0”.

[0042] When there is no G_X in (SLW #1, SLW #2), only one line in LSL_00, LSL_01, LSL_10, and LSL_11 is selected, the value of LSL_00, LSL_01, LSL_10, and LSL_11 is 1, OneX and XSL_00, XSL_01, XSL_10, and XSL_11 are all 0, N-type transistors connected thereto are turned on, and the value of the T terminal of corresponding MC cells is selected to the ML;

[0043] if LSL_00=1, the value of MC1.T is selected to the ML, marked as ML<=MC1.T;

[0044] if LSL_11=1, ML<=MC2.T;

[0045] if LSL_10=1, ML<=MC3.T;

[0046] if LSL_01=1, ML<=MC4.T;

[0047] in this case, OneX=0, the N-type transistor N1 is turned off, and ML_X is floating, marked as ML_x<=FLOAT;

[0048] when ML_x<=FLOAT, if ML=1, it is indicated that the value stored in the selected MC cell MC.F is 1, that is, the search result of the enhanced TL-TCAM cell circuit is match HIT; and if ML=0, the search result of the enhanced TL-TCAM cell circuit is mismatch MISS;

[0049] when there are two G_Xs in (SLW #1, SLW #2), LSL_00, LSL_01, LSL_10, LSL_11, XSL_00, XSL_01, XSL_10 XSL_11, and OneX are all 0, the N-type transistor N1 is turned off, ML_X<=FLOAT; the N-type transistor N5, the N-type transistor N6, the N-type transistor N9, and the N-type transistor N10 are turned off, ML<=FLOAT; in this case, the search result of the enhanced TL-TCAM cell circuit is match HIT;

[0050] when there is one G_X in (SLW #1, SLW #2), LSL_00, LSL_01, LSL_10, and LSL_11 are all 0; the N-type transistor N5, the N-type transistor N6, the N-type transistor N9, and the N-type transistor N10 are turned off, ML<=FLOAT;

[0051] when only one of XSL_00 and XSL_11 is selected:

[0052] if XSL_00 is selected, the N-type transistor N4 is turned on, and MA<=MC1.F;

[0053] if XSL_11 is selected, the N-type transistor N7 is turned on, and MA<=MC2.F;

[0054] when only one of XSL_10 and XSL_01 is selected:

[0055] if XSL_10 is selected, the N-type transistor N8 is turned on, and MB<=MC3.F;

[0056] if XSL_01 is selected, the N-type transistor N11 is turned on, and MB<=MC4.F;

[0057] OneX=1, and the N-type transistor N1 is turned on; in this case, if the MA line and the MB line are 1, both the N-type transistor N3 and the N-type transistor N2 are turned on, ML_x<=1, which indicates that the search result of the enhanced TL-TCAM cell circuit is mismatch MISS. If one of the MA line and the MB line is 0, or both are 0 at this time, and then at least one of the N-type transistor N2 and the N-type transistor N3 is turned off, ML_x<=FLOAT, which indicates that the search result of the enhanced TL-TCAM cell circuit is match HIT.

[0058] Table 4 summarizes the key signal states of the ETL-TCell cell during the search operation.

TABLE-US-00004 TABLE 4 Description of the search state of the ETL-TCell cell N1 (SLW#1, N5 N9 N4 N8 N2 Search result SLW#2) N6 N10 N7 N11 N3 ML ML_x HIT MISS No Four Four N1 is MC.T Floating when when G_X transistors. transistors. turned off, ML = 1 ML = 0 Only one All and gate transistor transistors electrodes is turned are turned of N2 on, and a off and N3 are corresponding floating MC.T value is selected to the ML 2 Four Four N1 is Floating Floating Constant N/A G_X transistors. transistors. turned off, be HIT All All and gate transistors transistors electrodes are turned are turned of N2 and off off N3 are floating 1 Four Only one Only one N1 is Floating 1 or when when G_X transistors. of N4/N7 of N8/N11 turned floating ML_x = ML_x = All is turned is turned on, N2 is FLOAT 1 transistors on, and a on, and a determined are turned corresponding corresponding by MB, and off MC.F is MC.F is N3 is selected selected determined to the MA to the MB by MA

[0059] The search function of the sub-segment circuit of the enhanced TL-TCAM is as follows:

[0060] The value range of ML is {MC.T, FLOAT}, the value range of MC.T is {0, 1}, then the value range of ML is {{0, 1}, FLOAT}. Assuming that when the ML of a certain enhanced TL-TCAM cell circuit is 0, it is marked as ETL-TCell.ML=0, then regardless of the value of the ML of other enhanced TL-TCAM cell circuits in the sub-segment, the ML of the sub-segment circuit may be pulled to a lower voltage, which indicates that the search result of the sub-segment circuit is mismatch MISS. Assuming that it is pre-charged to a high level at the beginning, the ML voltage remains at a high level, and the search result of the sub-segment circuit is match HIT.

[0061] When the N-type transistor N15 is turned on, the ML is also pulled to a lower level, and the search result of the sub-segment circuit is “mismatch”.

[0062] When search words (SLW #1, SLW #2) of each enhanced TL-TCAM cell circuit in the sub-segment circuit only contain an even number of G_Xs, that is, an even number of 0s or 2s, the signal line OneX_in-Sement_b=1, the N-type transistor N14 is turned on, OneX of each enhanced TL-TCAM cell circuit is 0, ML_x of the sub-segment circuit is 0, and the N-type transistor N15 of the sub-segment circuit is turned off. The state of the ML is only determined by the ML line of each ETL-TCell cell. ML of the sub-segment circuit is 1 represents that the sub-segment search result is match HIT, and ML=0 represents that the sub-segment search result is a mismatch MISS.

[0063] When the search words (SLW #1, SLW #2) of at least one enhanced TL-TCAM cell circuit in the sub-segment circuit contains an odd number of G_Xs, that is, an odd number of 1s, the signal line OneX_in-Sement_b=0, the ML of the sub-segment circuit is jointly determined by ML and ML_x of each enhanced TL-TCAM cell circuit. If ML_x in at least one enhanced TL-TCAM cell circuit is 1, the search result of the corresponding ETL-TCell cell is mismatch MISS, and at the same time, ML_x is charged to a high level, and ML_x of the sub-segment circuit is discharged to 0 by the N-type transistor N14 controlled by One_in_Segment_b at the beginning, causing that the N-type transistor N15 is turned on, and the ML of the sub-segment circuit is pulled to a low level, which indicates that the search result of the sub-segment circuit is mismatch MISS.

[0064] If the ML_x of all enhanced TL-TCAM cell circuits in the sub-segment circuit is FLOAT in this case, and the search result of each enhanced TL-TCAM cell circuit is match HIT, then the ML_x of the sub-segment circuit keeps the original low level, ML_x is reset to 0 by the N-type transistor N14 controlled by One_in_Segment_b at the beginning, the N-type transistor N15 is turned off, the ML of all enhanced TL-TCAM cell circuits is also FLOAT, and the ML of the sub-segment circuit also keeps the original high level, which indicates that the search result of the sub-segment circuit is match HIT.

[0065] Table 5 summarizes the above process.

TABLE-US-00005 TABLE 5 Description of the search state of the sub-segment circuit OneX_in_Seg- Search result ment_b ML_x HIT MISS When the search 1 ML_x of each ETL- when ML = 1 when ML = 0 words (SLW#1, TCell cell in the SLW#2) of each sub-segment is ETL-TCell cell in floating the sub-segment only contain an even number of G_Xs (i.e., 0 or 2) When the search 0 When ML_x of at N/A ML = 0, and words (SLW#1, least one ETL- in this case, SLW#2) of at least TCell cell in the search one ETL-TCell the sub-segment result of the cell in the sub- is 1 sub-segment segment only is “mismatch” contain an odd When ML_x of all ML = FLOAT N/A number of G_Xs ETL-TCell in the (keeping the (i.e., 1) sub-segment is original high FLOAT level), and in this case, the search result of the sub- segment is “match”

[0066] The search function of the word circuit of the enhanced TL-TCAM is as follows:

[0067] The search result of the word circuit is represented by the match line ML. The ML of the word circuit is the parallel connection of the ML of each sub-segment circuit. When the ML of the sub-segment circuit is 1, the ML of the word circuit is 1, which indicates that the search result of the word circuit is match HIT. When any ML of the sub-segment circuit is 0, the ML of the word circuit is 0, which indicates that the search result of the word circuit is mismatch MISS.

[0068] The read-write function of the present invention is as follows:

[0069] 1. Read Operation

[0070] In this case, WL=1, alternately setting XSL_00 and XSL_11 to high level can read MC1.F and MC2.F from BL1. At the same time, alternately setting XSL_10 and XSL_01 to high level can read MC3.F and MC4.F from BL2. The read operation function description is as shown in Table 6.

TABLE-US-00006 TABLE 6 Description of the read operation function Read Read WL XSL_00 XSL11 line BL1 XSL_10 XSL_01 line BL2 Read 1 1 — MC1.F 1 — MC3.F Operation — 1 MC2.F — 1 MC4.F Note: “—” in the table represents “0”.

[0071] 2. Write Operation

[0072] During the write operation, WL=1.

[0073] Like the conventional SRAM, the write operation is completed by writing “0” in MC.F or MC. T.

[0074] To write “1” in the MC (MC.T=1), the XSL directly connected to the MC cell is set to 1, and the BL is set to 0 (in this case, LSL is 0). For example:

[0075] XSL_00=1, BL1=0, then MC1.F=0, that is, MC1.T=1;

[0076] XSL_11=1, BL1=0, then MC2.F=0, that is, MC2.T=1;

[0077] XSL_10=1, BL2=0, then MC3.F=0, that is, MC3.T=1;

[0078] XSL_01=1, BL2=0, then MC4.F=0, that is, MC4.T=1.

[0079] To write “0” in the MC (MC.T=0), the SL directly connected to the MC cell is set to 1, and the ML is set to 0 (in this case, XSL is 0). For example:

[0080] LSL_00=1, ML=0, then MC1.T=0;

[0081] LSL_11=1, ML=0, then MC2.T=0;

[0082] LSL_10=1, ML=0, then MC3.T=0;

[0083] LSL_01=1, ML=0, then MC4.T=0.

[0084] Table 7 and 8 summarize the truth tables for the write operation

TABLE-US-00007 TABLE 7 Control line truth table when writing 1 Write operation WL LSL BL XSL_00 XSL_11 XSL_10 XSL_01 Write 1 MC1.F <= 0 1 LSL_00 <= 0 BL1 <= 0 1 — — — MC2.F <= 0 LSL_11 <= 0 BL2 <= 0 — 1 — — MC3.F <= 0 LSL_10 <= 0 BL3 <= 0 — — 1 — MC4.F <= 0 LSL_01 <= 0 BL4 <= 0 — — — 1 Note: “—” in the table represents “0”.

TABLE-US-00008 TABLE 8 Control line truth table when writing 0 Write operation WL XSL ML LSL_00 LSL_11 LSL_10 LSL_01 Write 0 MC1.T <= 0 1 XSL_00 <= 0 0 1 — — — MC2.T <= 0 XSL_11 <= 0 — 1 — — MC3.T <= 0 XSL_10 <= 0 — — 1 — MC4.T <= 0 XSL_01 <= 0 — — — 1 Note: “—” in the table represents “0”.

[0085] The descriptions above are only preferred specific embodiments of the present invention. However, the scope of protection of the present invention is not limited thereto. Any equivalent substitution or variation made by those skilled in the art within the technical scope disclosed by the present invention according to the technical solution and concept thereof of the present invention should all fall within the scope of protection of the present invention.