SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND GENERATION METHOD OF UNIQUE INFORMATION

Abstract

A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

Claims

1. A method of manufacturing a semiconductor device having a function of generating unique information based on an output of a circuit component of a second circuit, the method comprising: manufacturing a first circuit and the second circuit; manufacturing the first circuit in accordance with a first manufacturing condition; and manufacturing the second circuit in accordance with a second manufacturing condition; when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of the circuit component.

2. The method as claimed in claim 1, wherein: the first circuit is designed in accordance with a first design condition; the second circuit is designed in accordance with a second design condition; and when the second design condition is compared with the first design condition, the second design condition further includes a factor which increases a variation of the circuit component.

3. The method as claimed in claim 2, wherein: the first design condition comprises setting a channel width of a first transistor as a channel width W1; the second design condition comprises setting a channel width of a second transistor as a channel width W2 which is less than the channel width W1.

4. The method as claimed in claim 3, wherein: the channel width W1 is a design-allowable value; The channel width W2 is a value that is less than the design-allowable value.

5. The method as claimed in claim 1, wherein: the first manufacturing condition comprises setting the diffusion region of a first transistor having a channel length less than a constant value as an LDD structure and performing channel-ion implantation by forming a first dopant concentration on a surface of a substrate; the second manufacturing condition comprises not setting the diffusion region of a second transistor having a channel length less than the constant value as the LDD structure and performing channel-ion implantation by forming the first dopant concentration at a first position that is deeper than the surface of the substrate.

6. The method as claimed in claim 5, wherein: the first manufacturing condition comprises performing channel-ion implantation by forming a second dopant concentration, which is higher than the first dopant concentration, at a second position that is deeper than the surface of the substrate; the second manufacturing condition comprises performing channel-ion implantation by forming the second dopant concentration on the surface of the substrate.

7. A method of generating unique information of a semiconductor device, comprising: manufacturing a first circuit in accordance with a first manufacturing condition; manufacturing a second circuit in accordance with a second manufacturing condition, wherein when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of a circuit component; and generating the unique information based on an output of a circuit component of the second circuit.

8. The method as claimed in claim 7, wherein the first circuit is designed in accordance with a first design condition and the second circuit is designed in accordance with a second design condition; when the second design condition is compared with the first design condition, the second design condition further includes a factor which increases a variation of a circuit component.

9. The method as claimed in claim 8, wherein: the first design condition comprises setting a channel width of a first transistor as a channel width W1; the second design condition comprises setting a channel width of a second transistor as a channel width W2 which is less than the channel width W1.

10. The method as claimed in claim 7, wherein: the first manufacturing condition comprises setting the diffusion region of a first transistor having a channel length less than a constant value as an LDD structure and performing channel-ion implantation by forming a first dopant concentration on a surface of a substrate; the second manufacturing condition comprises not setting the diffusion region of a second transistor having a channel length less than the constant value as the LDD structure and performing channel-ion implantation by forming the first dopant concentration at a first position that is deeper than the surface of the substrate.

11. A semiconductor device, comprising: a first circuit manufactured in accordance with a first manufacturing condition; a second circuit manufactured in accordance with a second manufacturing condition, wherein when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of a circuit component; and a generation circuit, generating unique information based on an output of a circuit component of the second circuit.

12. The semiconductor device as claimed in claim 11, wherein: the second circuit comprises a plurality of transistors connected in parallel; the generation circuit comprises a detection circuit and a coding unit; the detection circuit is provided to detect drain currents of the transistors which are turned on; the coding unit generates coding information based on an output of the detection circuit.

13. The semiconductor device as claimed in claim 11, wherein: the second circuit comprises multiple sets of inverters, and each set of inverters has two inverters; the generation circuit includes a circuit which compares the voltage differences between different sets of inverters, when the sets of inverters have leakage currents, to generate a comparison result, and the circuit generates coding information based on the comparison result.

14. The semiconductor device as claimed in claim 11, wherein: the first circuit is further manufactured in accordance with a first design condition; and the second circuit is further manufactured in accordance with a second design condition, wherein when the second design condition is compared with the first design condition, the second design condition further includes a factor which increases a variation of a circuit component.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

[0017] FIG. 1 is a block diagram illustrating a functional structure of a semiconductor device according to an embodiment of the present invention.

[0018] FIG. 2 is a block diagram illustrating the internal structure of the unique-information generation circuit according to the embodiment of the present invention.

[0019] FIG. 3 is a flowchart illustrating a design method of a semiconductor device according to the first embodiment of the present invention.

[0020] FIG. 4 illustrates the design condition of the first embodiment of the present invention.

[0021] FIG. 5 illustrates the transistors having different channel width according to the first embodiment of the present invention.

[0022] FIG. 5A illustrates the relationship between the channel width and the variation of the threshold voltage of the transistor.

[0023] FIG. 6 illustrates the variation of the transistor produced by the design condition of the first embodiment of the present invention.

[0024] FIG. 7 is a flowchart illustrating a design method of a semiconductor device according to the second embodiment of the present invention.

[0025] FIG. 8 illustrates the design condition of the second embodiment of the present invention.

[0026] FIG. 9 illustrates a transistor with and without LDD according to the second embodiment of the present invention.

[0027] FIG. 10 illustrates the transistors having different doping depth according to the second embodiment of the present invention.

[0028] FIG. 10A illustrates the relationship between the dopant concentration of the silicon substrate, the dopant concentration of the SOT film, and the threshold voltage of the transistor.

[0029] FIG. 10B illustrates the variation distribution of the threshold value of the transistor.

[0030] FIG. 11 is a flow chart illustrating a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

[0031] FIG. 12 illustrates the operation of the unique-information generation circuit according to the embodiment of the present invention.

[0032] FIG. 13 illustrates the structure of the unique-information generation circuit according to an embodiment of the present invention.

[0033] FIG. 14 illustrates the structure of the unique-information generation circuit according to an embodiment of the present invention.

[0034] FIG. 15 illustrates the authentication system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0035] Herein, the exemplary embodiments of the invention will be described in detail in reference to the accompanying drawings. Moreover, drawings are shown by emphasizing respective portions for easy understanding, and it should be noted that the dimensions thereof are not identical to those of practical devices.

Embodiments

[0036] FIG. 1 illustrates a schematic of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 of the present embodiment can have any function and is not limited to the function thereof. The semiconductor device 100 may be the semiconductor memory, semiconductor logic, semiconductor processing circuit, semiconductor driving circuit, central processing circuit, and the like. The semiconductor device 100 can be used in the IC card medium (e.g., the SIM card, credit card, and the card containing an IC), portable terminal (such as the smartphone), electronic device, computer, and any electronic device which needs security.

[0037] The semiconductor device 100 has the integrated circuit 110 which performs arbitrary functions, input/output circuit 120, and unique-information generation circuit 130 which generates the unique information of the semiconductor device 100. The input/output circuit 120 can receive an input data from the outside and provide the input data to the integrated circuit 110 or the unique-information generation circuit 130. The input/output circuit 120 can output the execution result of the integrated circuit 110 or the unique information generated by the unique-information generation circuit 130 to the outside.

[0038] The semiconductor device 100 is formed by forming a plurality of circuit components (e.g., the transistor, resistor, capacitor, etc.) on the silicon substrate or other substrate (e.g., SiC, GaAs, sapphire, etc.). The circuit component included in the integrated circuit 110 is designed in accordance with the general condition and support the desired function.

[0039] The unique-information generation circuit 130 generates the unique information of the semiconductor device based on the output of the circuit components formed in the semiconductor device 100 (ideally, the output of the transistor and the inverter). FIG. 2 illustrates the internal structure of the unique-information generation circuit 130. The unique-information generation circuit 130 includes the PUF circuit 132 and the code-generation unit 134 which generates code information based on the output of the PUF circuit 132. The PUF circuit 132 is formed by the circuit components which include the transistor. The design condition of the PUF circuit 132 is different from the design condition of the integrated circuit 110, and is designed in accordance with the design condition which increases the variations (or process variation) of the circuit components.

[0040] FIG. 3 illustrates the design method of the integrated circuit 110 and the PUF circuit 132 according to the present embodiment. Here, the transistor represents the circuit component. The n-type or p-type MOS transistor included in the integrated circuit 110 is designed to meet the required operating conditions. Moreover, on the basis of the minimum manufacturing size, the channel length (L) and the channel width (W) of the transistor are designed by using the general design condition (S100). However, it does not mean that all of the transistors are designed with the minimum manufacturing size, but it means that the transistor may be designed with the minimum manufacturing size. On the other hand, the embodiment is designed to meet the required operating conditions. The general design condition reduces the variation (fluctuation) of the transistor of the integrated circuit 110. Therefore, the threshold values of the transistors of the integrated circuit 110 are designed to remain uniform.

[0041] The PUF circuit 132 is designed in accordance with the design condition of the PUF which increases the variation (deviation) of the transistor (S110) and is different from the general design condition of the integrated circuit 110. As a result, the variation of the threshold values of the transistors of the PUF circuit 132 is increased. When the variation of the transistors is used for the unique information, the large variation of the transistors can generate the randomness of the unique information and suppress the effects caused by the operating conditions and the noise, which makes the unique information permanent.

[0042] FIG. 4 illustrates an example of the design condition of the present embodiment. The transistor of the integrated circuit 110 is designed to have channel width W1 to meet the required operating condition. It is known that the channel width can affect the variation of the transistor. When the channel width is increased, the variation of the threshold value of the transistor is reduced. On the contrary, when the channel width is reduced, the variation of the threshold value of the transistor is increased. Therefore, the channel width W1 of the transistors of the integrated circuit 110 is designed to be as large as possible.

[0043] On the other hand, since the transistors of the PUF circuit 132 are designed to have the large variation, the channel width W2 is designed to be as small as possible. However, the channel width W2 is not less than the minimum manufacturing size. The schematic (A) in FIG. 5 shows the transistor of the integrated circuit 110, and the schematic (B) in FIG. 5 shows the transistor of the PUF circuit 132. If the channel length L of the transistor in the integrated circuit 110 is equal to the channel length L of the transistor in the PUF circuit 132, the channel width W2 can be designed to be less than the channel width W1.

[0044] FIG. 5A illustrates the relationship between the channel width and the variation of the threshold value. The horizontal axis is 1/(LW).sup.0.5 (μm.sup.−1), and the channel width W is expressed in reciprocal when the channel length L remains constant. The vertical axis is the threshold value. Tox1, Tox2, Tox3 (Tox1<Tox2<Tox3) are the film thickness of the gate oxide films. Δ indicates the high Vth, □ represents the medium Vth, and ⋄ represents the low Vth. Regarding the same figure, when W becomes smaller (more rightward), the distances between the high Vth, medium Vth, and the low Vth becomes larger, which means that the variation (deviation) of the threshold values Vth is increased. That is, the channel width is inversely proportional to the variation of the threshold value.

[0045] In this embodiment, when the integrated circuit 110 is designed in accordance with the general design condition and the PUF circuit 132 is designed in accordance with the design condition including an increasing-variation factor, the threshold values Vth of the transistors in the integrated circuit 110 have the normal distribution σ1 as shown in graphic (A) of FIG. 6, and the threshold values Vth of the transistors in the PUF circuit 132 have the distribution σ2 showing a large variation (fluctuation). Therefore, the randomness (non-predictability) of the variation of the transistors in the PUF circuit 132 is higher than the randomness (non-predictability) of the variation of the transistors in the integrated circuit 110.

[0046] Next, a method of manufacturing a semiconductor device according to the second embodiment of the present invention is described below. FIG. 7 is a flowchart of the method of manufacturing a semiconductor device according to the second embodiment. In the second embodiment, the integrated circuit 110 is manufactured in accordance with the general manufacturing condition which has the small variation of the transistors, high reproducibility, and high reliability (S200). On the other hand, the PUF circuit 132 is manufactured in accordance with the manufacturing condition of PUF which is different from the general manufacturing condition and includes an increasing-variation factor of the transistors.

[0047] FIG. 8 illustrates an example of the manufacturing condition of the second embodiment. In one example, the source/drain diffusion region of the transistor of the integrated circuit 110 has the lightly doped drain (LDD) structure, and the transistor of the PUF circuit 132 does not have the LDD structure. Schematic (A) in FIG. 9 shows the transistor 200 of the integrated circuit 110. The transistor 200 includes the gate electrode 210 and the diffusion region 220 with the LDD structure. The LDD is manufactured by, for example, forming a dopant diffusion region by the first ion implantation (wherein the gate electrode 210 works as a mask), and then forming the side wall 212 on both sides of the gate electrode 210. Next, the second ion implantation is performed (wherein the gate electrode 210 and the side wall 212 work as mask). As other manufacturing methods, the LDD structure may be formed by the rotating-ion implantation.

[0048] The schematic (B) in FIG. 9 is the transistor 300 of the PUF circuit 132. The transistor 300 includes the gate electrode 310 and the diffusion region 320 which is not formed with the LDD structure. For example, the diffusion region 320 is formed by implanting the dopant ion (wherein the gate electrode 310 works as a mask). In the transistor 300 without LDD structure, a high electric field is generated between the gate electrode 310 and the diffusion region 320. At least due to the hot-electron injection, the variation of the threshold value becomes larger than the transistor with the LDD structure. When the channel length L of the transistor is reduced, it is desirable to form the LDD structure to suppress the variation. If transistor 200 of the integrated circuit 110 and the transistor 300 of the PUF circuit 132 have the channel length L which is less than a certain value, the LDD structure is formed in the transistor 200, and the LDD structure is not formed in the transistor 300.

[0049] In another embodiment, the transistor of the integrated circuit 110 is performed the channel-ion implantation by forming the dopant region with low concentration on the surface of a substrate, and the transistor of the PUF circuit 132 is performed channel-ion implantation by forming the dopant region with low concentration at a position that is deeper than the surface of the substrate. In other embodiments, the transistor of the integrated circuit 110 is performed the channel-ion implantation by forming the dopant region with high concentration at a position that is deeper than the surface of the substrate, and the PUF circuit is performed channel-ion implantation by forming the dopant region with high concentration on the surface of the substrate. In this embodiment, the variation of the transistor is controlled by controlling the depth of the ion implantation. When the concentration of the dopant on the surface of the substrate is increased, the characteristics of the transistor is degraded, which increases the variation.

[0050] The schematic (A) in FIG. 10 illustrates the transistor 200A of the integrated circuit 110. For example, the BOX layer (SiO.sub.2) 232 is formed on the silicon substrate 230 by SIMOX or the substrate bonding method, and the SOI film 234 is formed on the surface of the substrate. The SOI film 234 is the silicon produced by epitaxy. The silicon substrate 230 is doped with a high concentration by the ion implantation, and the SOI film 234 is doped with a low concentration by the ion implantation. The schematic (B) in FIG. 10 illustrates the transistor 300A of the PUF circuit. Regarding the transistor 300A, the silicon substrate 330 is doped with a low concentration by the ion implantation, and the SOI film 334 on the surface of the substrate is doped with a high concentration.

[0051] FIG. 10A illustrates the threshold value Vth of the transistor which is determined by the dopant concentration of the silicon substrate (vertical axis) and the dopant concentration of the SOI film (horizontal axis). As the two types of the dopant concentration increase, the threshold value Vth becomes larger. The graph showing the variation of the transistor's threshold values at the sampling points (1)-(5) in the same figure is shown in FIG. 10B. N.sub.SUB is the concentration of the substrate, N.sub.SOI is the concentration of the SOI film, T.sub.OX is the film thickness of the gate oxide film, T.sub.BOX is the film thickness of the BOX layer, and L.sub.g is the channel length. Referring the same figure, it can be seen that as the N.sub.SOI becomes higher, the variation of the threshold value becomes larger as shown in the statistics. The sampling point (5) represents the maximum, and the sampling point (1) represents the minimum. That is, as the transistor 300A shown in the schematic (B) of FIG. 10, when the dopant concentration of the SOI film 334 becomes higher, the variation of the transistor 300A tends to be larger than that of the transistor 200A.

[0052] The manufacturing method of a semiconductor device according to the third embodiment of the present invention is described below. FIG. 11 illustrates the manufacturing method of the third embodiment. The third embodiment is the combination of the design method of the first embodiment and the manufacturing method of the second embodiment. That is, the transistor of the integrated circuit 110 is designed in accordance with the general design condition and is manufactured in accordance with the general manufacturing condition. The transistor of the PUF circuit 132 is designed in accordance with the design condition of PUF which contains an increasing-variation factor and is manufactured in accordance with the manufacturing condition of PUF which contains an increasing-variation factor. The respective design conditions and manufacturing conditions are described in the first and second embodiments. According to the third embodiment, the variation (fluctuation) of the transistor of the PUF circuit 132 is increased, and the randomness of the variation can be improved.

[0053] The code-generation unit (FIG. 2) of the present embodiment is described below. The code-generation unit 134 receives the output data of the PUF circuit 132 and generates the unique code in the semiconductor device. FIG. 12 is a flowchart showing the operation of the code-generation unit 134 of the present embodiment. In one example, as shown in part (A) of FIG. 12, when the semiconductor device 100 receives the power (S300), the code-generation unit 134 generates the code based on the output data of the PUF circuit 132 (S310), and the input/output circuit 120 transmits the generated code to the outside (S320). That is, the code of the semiconductor device is outputted as the power-up sequence of the semiconductor device 100.

[0054] In the other embodiments, as shown in part (B) of FIG. 12, when the code-generation unit 134 receives the request (through the input/output circuit 120) for outputting the code (S302), the code is generated based on the output data of the PUF circuit 132 (S310), the input/output circuit 120 outputs the generated code to the outside in response to the request (S320). It should be noted that the generated code is not stored in the memory (or the like), and is directly output to the outside through the input/output circuit 120.

[0055] The code-generation unit 134 may directly generate the code based on the output data of the PUF circuit 132 or convert the output data of the PUF circuit 132 into other information to generate the code based on the converted information. For example, the output data of the PUF circuit 132 is encoded (e.g., encoded based on a function) to generate the code. For example, the output data of the PUF circuit 132 is utilized to generate the address information, and the memory section is accessed based on the address information to generate the code. The circuit of the code-generation unit 134 is manufactured by the design condition or manufacturing condition which is applied to the integrated circuit 110.

[0056] FIG. 13 illustrates the embodiment of the code-generation unit 134. In this embodiment, the PUF circuit 132 is consist of n NMOS transistors Q1, Q2, Q3 . . . Qn connected in parallel. As described in the first to the third embodiments, since the transistors Q1-Qn are manufactured based on the increasing-variation (variation) factor, the variation of the threshold values of the transistors Q1-Qn is large. The n transistors Q1-Qn receive the voltage Vdd, and the gate electrodes are commonly connected to the driving signal DV.

[0057] The code-generation unit 134 includes the driving circuit (not shown) which generates the driving signal DV, n current-detection-type sensing amplifiers S/A which are respectively connected to the transistors Q1-Qn, and coding unit 140 encoding the output data of the sensing amplifiers S/A. When the code-generation unit 134 generates the code (e.g., the driving signal DV equal to Vdd is provided to transistors Q1-Qn, which makes the transistors Q1-Qn turn on simultaneously), the variation of the threshold values of the transistors Q1-Qn is increased. Therefore, the variation of the drain currents flowing through the transistors Q1-Qn is increased. The current-detection-type sensing amplifiers S/A respectively detect the drain currents flowing through the transistors Q1-Qn and provide the detection result to the coding unit 140.

[0058] The coding unit 140 performs encoding based on the drain currents detected by the sensing amplifiers S/A. The coding unit 140 sets the drain current detected by one sensing amplifier as binary value (“0” or “1”). When the PUF circuit 132 has n transistors Q1-Qn, the coding unit 140 generates 2.sup.n encoded serial data.

[0059] If the transistors Q1-Qn of the PUF circuit 132 and the integrated circuit 110 are manufactured in accordance with the same general design condition or the general manufacturing condition, the variation of the transistors Q1-Qn performs the normal distribution σ1 as shown in graphic (A) in FIG. 6. Therefore, the variation of the drain currents flowing through the transistors Q1-Qn becomes small, and the coding result of the coding unit 140 has uniformity. That is, the randomness of the generated 2.sup.n serial data is reduced.

[0060] In addition, the operating characteristics of the transistor are easily affected by the change of temperature, and the small drain current may be affected by the noise of the sensing amplifier. As in the present embodiment, when the variation of the transistor is increased, the margin for coding can be increased. Therefore, the effects caused by temperature and noise are difficult to make the coding result to be changed. That is, the output data of the PUF circuit 132 can be maintained at high permanence.

[0061] In the embodiment mentioned above, the coding unit 140 sets the output signal of the sensing amplifier as binary value, but the present invention is not limited to this application. If the variation of the transistor is very large, the output signal of the sensing amplifier may be set as ternary to produce 4-bit data.

[0062] FIG. 14 illustrates other structures of the code-generation circuit. In this embodiment, the PUF circuit 132 includes the inverters IV1 and IV2, wherein the inverters IV1 and IV2 receive electricity from power Vcc. The gate electrodes are commonly connected to the driving signal DV. The code-generation unit 134 includes the driving circuit (not shown) for supplying the driving signal DV, and the comparator (differential amplifier) 150 for receiving the output signals of the inverters IV1 and IV2.

[0063] The code is generated when the code-generation unit 134 outputs the driving signal DV to inverters IV1 and IV2. Ideally, the driving signal is ½Vcc. When the inverters IV1 and IV2 receive the driving signal DV (½ Vcc), the inverters IV1 and IV2 conduct the current which is set as the leakage current. Since the variation of the inverters IV1 and IV2 is large, the variation of the leakage currents flowing through the inverters W1 and IV2 is also large. Therefore, the variation of the voltages generated at the output node N1 of the inverter IV1 and the output node N2 of the inverter IV2 is also large. The differential amplifier 150 receives the voltages from the output node N1 and the output node N2 and outputs the data corresponding to the difference between the voltages. In FIG. 14, only one set of inverters IV1 and IV2 is shown. When the PUF circuit 132 consists of n sets of inverters, the n differential amplifiers 150 output 2n serial data.

[0064] The code-generation unit 134 is shown as FIG. 13 and FIG. 14. In some embodiments, the code-generation unit 134 may be arbitrarily manufactured by the existing circuits.

[0065] The authentication system including the flash memory with a security function is shown in FIG. 15. The flash memory 400 having the security function includes the unique-information generation circuit 130 as described in the first to third embodiments. The host device 500 includes the code-storage circuit 510 for storing the code of the unique information of the flash memory 400, and the host device 500 also includes the authentication unit 520 for verifying the flash memory 400.

[0066] The flash memory 400 outputs the unique information to the host device 500 while being turned on or receiving the request from the host device 500. The authentication unit 520 compares the received unique information with the stored code. If they are matched to each other, then the flash memory 400 is verified. If they are not matched, then the flash memory 400 is identified as the fake or counterfeited product, and the flash memory 400 is not verified. For example, when the flash memory 400 is not authenticated by the host device 500, the host device 500 can disable the operation of the electronic device including the flash memory 400.

[0067] While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.