DISPLAY DEVICE

Abstract

A display device can include a left ripple transistor provided in a left stage to remove ripple occurring in a Q node of the left stage, and a right ripple transistor provided in a right stage to remove ripple occurring in a Q node of the right stage. These ripple transistors perform an on operation and an off operation repeatedly and simultaneously.

Claims

1. A display device comprising: a display panel including a display area and a non-display area adjacent to the display area and including gate lines; a left gate driver provided in a first non-display area of the non-display area to output left gate pulses and left gate off signals to the gate lines; and a right gate driver provided in a second non-display area of the non-display area to output right gate pulses and right gate off signals to the gate lines, wherein the left gate driver comprises an n.sup.th left stage outputting an n.sup.th left gate pulse and the right gate driver comprises an n.sup.th right stage outputting an n.sup.th right gate pulse, where n is a natural number, outputs of the n.sup.th left gate pulse and the n.sup.th right gate pulse are controlled by an n.sup.th left Q nodes included in the n.sup.th left stage and an n.sup.th right Q node included in the n.sup.th right stage, and an n.sup.th left ripple transistor provided in the n.sup.th left stage to remove ripple occurring in the n.sup.th left Q node of the n.sup.th left stage and an n.sup.th right ripple transistor provided in the n.sup.th right stage to remove ripple occurring in the n.sup.th right Q node of the n.sup.th right stage perform an on operation and an off operation repeatedly.

2. The display device of claim 1, wherein a phase of an n.sup.th left gate clock supplied to the n.sup.th left stage to generate the n.sup.th left gate pulse is the same as a phase of an n.sup.th left ripple clock supplied for driving the n.sup.th left ripple transistor, and a phase of an n.sup.th right gate clock supplied to the n.sup.th right stage to generate the n.sup.th right gate pulse is the same as a phase of an n.sup.th right ripple clock supplied for driving the n.sup.th right ripple transistor.

3. The display device of claim 1, wherein a phase of an n.sup.th left ripple clock supplied for driving the n.sup.th left ripple transistor is the same as a phase of an n.sup.th right ripple clock supplied for driving the n.sup.th right ripple transistor.

4. The display device of claim 1, wherein a first terminal of the n.sup.th left ripple transistor is connected to the n.sup.th left Q node, a second terminal of the n.sup.th left ripple transistor is connected to a first voltage terminal, and a gate of the n.sup.th left ripple transistor is connected to a gate of an n.sup.th left pull-down transistor which controls an output of an n.sup.th left gate off signal, and a first terminal of the n.sup.th right ripple transistor is connected to the n.sup.th right Q node, a second terminal of the n.sup.th right ripple transistor is connected to the first voltage terminal, and a gate of the n.sup.th right ripple transistor is connected to a terminal which is supplied with an n.sup.th right ripple clock.

5. The display device of claim 4, wherein a phase of an n.sup.th left gate clock supplied to the n.sup.th left stage to generate the n.sup.th left gate pulse is the same as a phase of an n.sup.th left ripple clock supplied for driving the n.sup.th left ripple transistor, and a phase of an n.sup.th right gate clock supplied to the n.sup.th right stage to generate the n.sup.th right gate pulse is the same as a phase of the n.sup.th right ripple clock supplied to a gate of the n.sup.th right ripple transistor.

6. The display device of claim 4, wherein an n.sup.th left ripple clock is supplied to a gate of the n.sup.th left ripple transistor, the n.sup.th right ripple clock is supplied to a gate of the n.sup.th right ripple transistor, and a phase of the n.sup.th left ripple clock is the same as a phase of the n.sup.th right ripple clock.

7. The display device of claim 4, wherein a gate of the n.sup.th left ripple transistor is connected to a gate of an n.sup.th left pull-down transistor which controls an output of the n.sup.th left gate off signal, and a gate of the n.sup.th right ripple transistor is not connected to a gate of an n.sup.th right pull-down transistor which controls an output of an n.sup.th right gate off signal.

8. The display device of claim 7, wherein a gate of the n.sup.th right pull-down transistor is connected to a gate of an n+1.sup.th right ripple transistor included in an n+1.sup.th right stage.

9. The display device of claim 1, wherein, when the n.sup.th left ripple transistor is turned on, an n.sup.th left gate off signal is output from the n.sup.th left stage to an n.sup.th gate line, and when the n.sup.th right ripple transistor is turned off, an n.sup.th right gate off signal is output from the n.sup.th right stage to the n.sup.th gate line.

10. The display device of claim 1, wherein an n.sup.th left gate off signal output from the n.sup.th left stage and an n.sup.th right gate off signal output from the n.sup.th right stage are alternately output to an n.sup.th gate line.

11. The display device of claim 1, wherein outputs of an n.sup.th left gate off signal and an n.sup.th right gate off signal are controlled by an n.sup.th left Qb node included in the n.sup.th left stage and an n.sup.th right Qb node included in the n.sup.th right stage, a gate of the n.sup.th left ripple transistor and the n.sup.th left Qb node included in the n.sup.th left stage are connected to each other, and the n.sup.th right Qb node included in the n.sup.th right stage is connected to a gate of an n+1.sup.th right ripple transistor included in an n+1.sup.th right stage.

12. The display device of claim 1, wherein the n.sup.th left stage comprises an n.sup.th left signal generator including the n.sup.th left ripple transistor and an n.sup.th left signal output unit configured to output an n.sup.th left gate off signal and the n.sup.th left gate pulse, based on an n.sup.th left control signal generated by the n.sup.th left signal generator, the n.sup.th right stage comprises an n.sup.th right signal generator including the n.sup.th right ripple transistor and an n.sup.th right signal output unit configured to output an n.sup.th right gate off signal and the n.sup.th right gate pulse, based on an n.sup.th right control signal generated by the n.sup.th right signal generator, and the n.sup.th left gate off signal and the n.sup.th right gate off signal are alternately output.

13. The display device of claim 12, wherein the n.sup.th left signal output unit comprises an n.sup.th left pull-up transistor outputting the n.sup.th left gate pulse, a gate of the n.sup.th left pull-up transistor being connected to the n.sup.th left Q node, and the n.sup.th right signal output unit comprises an n.sup.th right pull-up transistor outputting the n.sup.th right gate pulse, a gate of the n.sup.th right pull-up transistor being connected to the n.sup.th right Q node.

14. The display device of claim 13, wherein the n.sup.th left signal output unit comprises an n.sup.th left pull-down transistor outputting the n.sup.th left gate off signal, a gate of the n.sup.th left pull-down transistor being connected to a gate of the n.sup.th left ripple transistor, and the n.sup.th right signal output unit comprises an n.sup.th right pull-down transistor outputting the n.sup.th right gate off signal, a gate of the n.sup.th right pull-down transistor being connected to a gate of an n+1.sup.th right ripple transistor included in an n+1.sup.th right stage.

15. The display device of claim 14, wherein the n.sup.th left signal output unit further comprises an n_2.sup.th left pull-up transistor, a gate of the n_2.sup.th left pull-up transistor being connected to the n.sup.th left Q node, where g is an even number, and n is a natural number of g/2, and the n.sup.th right signal output unit further comprises an n_2.sup.th right pull-up transistor, a gate of the n_2.sup.th right pull-up transistor being connected to the n.sup.th right Q node.

16. The display device of claim 15, wherein the n.sup.th left signal output unit further comprises an n_2.sup.th left pull-down transistor connected to the n_2.sup.th left pull-up transistor, a gate of the n_2.sup.th left pull-down transistor is connected to a gate of the n.sup.th left ripple transistor, the n.sup.th right signal output unit further comprises an n_2.sup.th right pull-down transistor connected to the n_2.sup.th right pull-up transistor, and a gate of the n_2.sup.th right pull-down transistor is connected to a gate of an n−1.sup.th right ripple transistor included in an n−1.sup.th right stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:

[0014] FIG. 1 is a diagram illustrating a configuration of a display device according to an embodiment of the present disclosure;

[0015] FIGS. 2A and 2B are diagrams illustrating examples of a structure of a pixel applied to the display device according to an embodiment of the present disclosure;

[0016] FIG. 3 is a diagram illustrating a structure of a controller applied to the display device according to an embodiment of the present disclosure;

[0017] FIG. 4 is a diagram illustrating a structure of each of gate drivers applied to the display device according to an embodiment of the present disclosure;

[0018] FIG. 5 is a diagram schematically illustrating a structure of each of stages illustrated in FIG. 4;

[0019] FIG. 6 is a diagram illustrating in detail a structure of each of the stages illustrated in FIG. 4;

[0020] FIG. 7 is a diagram showing waveforms applied to a display device according to an embodiment of the present disclosure;

[0021] FIG. 8 is a diagram illustrating a method of outputting a gate off signal in a display device according to an embodiment of the present disclosure;

[0022] FIG. 9 is another diagram illustrating in detail a structure of each of the stages illustrated in FIG. 4; and

[0023] FIG. 10 is a diagram showing waveforms applied to the stages illustrated in FIG. 9.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0025] Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims.

[0026] A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. When “comprise,” “have,” and “include” described in the present specification are used, another part can be added unless “only” is used. The terms of a singular form can include plural forms unless referred to the contrary.

[0027] In construing an element, the element is construed as including an error or tolerance range although there is no explicit description of such an error or tolerance range.

[0028] In describing a position relationship, for example, when a position relation between two parts is described as, for example, “on,” “over,” “under,” and “next,” one or more other parts can be disposed between the two parts unless a more limiting term, such as “just” or “direct(ly)” is used.

[0029] In describing a time relationship, for example, when the temporal order is described as, for example, “after,” “subsequent,” “next,” and “before,” a case that is not continuous can be included unless a more limiting term, such as “just,” “immediate(ly),” or “direct(ly)” is used.

[0030] It will be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0031] In describing elements of the present disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc. can be used. These terms are intended to identify the corresponding elements from the other elements, and basis, order, or number of the corresponding elements should not be limited by these terms. The expression that an element is “connected,” “coupled,” or “adhered” to another element or layer the element or layer can not only be directly connected or adhered to another element or layer, but also be indirectly connected or adhered to another element or layer with one or more intervening elements or layers “disposed,” or “interposed” between the elements or layers, unless otherwise specified.

[0032] The term “at least one” should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first item, a second item, and a third item” denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.

[0033] Features of various embodiments of the present disclosure can be partially or overall coupled to or combined with each other, and can be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure can be carried out independently from each other, or can be carried out together in co-dependent relationship.

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Further, all the components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0035] FIG. 1 is a diagram illustrating a configuration of a display device according to an embodiment of the present disclosure. FIGS. 2A and 2B are diagrams illustrating examples of a structure of a pixel applied to a display device according to the present disclosure. FIG. 3 is a diagram illustrating a structure of a controller applied to a display device according to an embodiment of the present disclosure.

[0036] The display device according to the present disclosure can configure various electronic devices. The electronic devices can include, for example, smartphones, tablet personal computers (PCs), televisions (TVs), and monitors.

[0037] The display device according to the present disclosure, as illustrated in FIG. 1, can include a display panel 100 which includes a display area 120 displaying an image and a non-display area 130 provided outside the display area 120, a plurality of gate drivers 200a and 200b which supply a gate signal to a plurality of gate lines GL1 to GLg provided in the display area 120 of the display panel 100, a data driver 300 which supplies data voltages to a plurality of data lines DL1 to DLd provided in the display panel 100, a controller 400 which controls driving of the gate drivers 200a and 200b and the data driver 300, and a power supply 500 which supplies power to the controller 400, the gate drivers 200a and 200b, the data driver 300, and the display panel 100.

[0038] First, the display panel 100 can include the display area 120 and the non-display area 130. The gate lines GL1 to GLg, the data lines DL1 to DLd, and the pixels 110 can be provided in the display area 120. Accordingly, the display area 120 can display an image. Here, g and d can each be a natural number, e.g., positive integer. In particular, g may be an even number. The non-display area 130 can surround the display area 120.

[0039] The display panel 100 can be a liquid crystal display panel which includes the pixel 110 illustrated in FIG. 2A, or can be a light emitting display panel which includes the pixel 110 illustrated in FIG. 2B.

[0040] For example, when the display panel 100 is the liquid crystal display panel, as illustrated in FIG. 2A, the pixel 110 included in the display panel 100 can include a pixel driving circuit PDC, including a switching transistor Tsw1 and a common electrode, and liquid crystal. The liquid crystal can be included in an emission area. In FIG. 2, Clc can denote liquid crystal which is provided between the common electrode and a pixel electrode connected to the switching transistor Tsw1.

[0041] For example, when the display panel 100 is the light emitting display panel, as illustrated in FIG. 2B, the pixel 110 included in the display panel 100 can include a pixel driving circuit PDC, including a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2, and an emission area including a light emitting device ED.

[0042] A structure of the pixel 110 of the liquid crystal display panel and a structure of the pixel 110 of the light emitting display panel are not limited to a structure illustrated in FIGS. 2A and 2B, and thus, can be implemented as various types.

[0043] For example, the display device according to the present disclosure can be an LCD device including the liquid crystal display panel or can be the light emitting display device including the light emitting display panel, but is not limited thereto and can be a display device including various types of display panels.

[0044] Hereinafter, for convenience of description, a display device including a light emitting display panel will be described as an example of the present disclosure.

[0045] The data driver 300 can be mounted on a chip on film attached on the display panel 100. In this case, the data driver 300 can be connected to the data lines DL1 to DLd included in the display panel 100 and the controller 400 mounted on a main substrate.

[0046] The data driver 300 can be directly equipped in the display panel 100, and then, can be connected to the controller 400 provided in the main substrate.

[0047] The data driver 300 can be implemented as one integrated circuit (IC) along with the controller 400. In this case, the IC can be mounted on the chip on film, or can be directly equipped in the display panel 100.

[0048] The controller 400 can realign input video data Ri, Gi, and Bi transferred from an external system by using a timing synchronization signal TSS transferred from the external system and can generate data control signals DCS which are to be supplied to the data driver 300 and gate control signals GCS which are to be supplied to the gate drivers 200a and 200b.

[0049] To this end, as illustrated in FIG. 3, the controller 400 can include a data aligner 430 which realigns the input video data Ri, Gi, and Bi to generate image data Data and supplies the image data Data to the data driver 300, a control signal generator 420 which generates the gate control signal GCS and the data control signal DCS by using the timing synchronization signal TSS, an input unit 410 which receives the timing synchronization signal TSS and the input video data Ri, Gi, and Bi transferred from the external system and respectively transfers the timing synchronization signal TSS and the input video data Ri, Gi, and Bi to the data aligner 430 and the control signal generator 420, and an output unit 440 which supplies the data driver 300 with the image data Data generated by the data aligner 430 and the data control signal DCS generated by the control signal generator 420 and supplies the gate drivers 200a and 200b with the gate control signals GCS generated by the control signal generator 420.

[0050] The external system can perform a function of driving the controller 400 and an electronic device. For example, when the electronic device is a TV, the external system can receive various sound information, video information, and letter information over a communication network and can transfer the received video information to the controller 400. In this case, the image information can include input video data Ri, Gi, and Bi.

[0051] The power supply 500 can generate various powers and can supply the generated powers to the controller 400, the gate drivers 200a and 200b, the data driver 300, and the display panel 100.

[0052] Finally, the gate driver 200 can be implemented as an IC and can be provided in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 by using a gate in panel (GIP) type. When the GIP type is used, transistors configuring the gate driver 200 can be provided in the non-display area through the same process as transistors included in each pixel 110.

[0053] When the gate pulse generated by each of the gate drivers 200a and 200b is supplied to a gate of the switching transistor Tsw1 included in the pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, a data voltage supplied through a data line DL can be supplied to the pixel 110. When a gate off signal generated by each of the gate drivers 200a and 200b is supplied to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, data voltage Vdata may not be supplied to the pixel 100 any longer. The gate signal GS supplied to the gate line GL can include a gate pulse and a gate off signal.

[0054] In the present disclosure, as illustrated in FIG. 1, two gate drivers 200a and 200b can be provided.

[0055] One gate driver 200a can be provided in a first non-display area 131, provided at a left side of the gate line GL, of the non-display area 130. In the following description, a gate driver provided in the first non-display area 131 can be simply referred to as a left gate driver 200a.

[0056] The other gate driver 200b can be provided in a second non-display area 132, provided at a right side of the gate line GL, of the non-display area 130. In the following description, a gate driver provided in the second non-display area 132 can be simply referred to as a right gate driver 200b.

[0057] In this case, the second non-display area 132 can be provided to face the first non-display area 131, but is not limited thereto. For example, positions of the first non-display area 131 and the second non-display area 132 can be variously changed based on a type where a gate line is provided. Further, in the following description, a left side and a right side can denote one side and the other side of a gate line, and thus, are not limited to a left side and a right side used for expressing a point of the compass.

[0058] Detailed structures and functions of the left gate driver 200a and the right gate driver 200b will be described below with reference to FIGS. 4 to 10. In the following description, the gate driver 200 can be used in a case where all of the left gate driver 200a and the right gate driver 200b are described.

[0059] FIG. 4 is a diagram illustrating a structure of each of gate drivers applied to a display device according to an embodiment of the present disclosure.

[0060] In FIG. 4, reference numerals L_GCS and R_GCS can refer to a left gate control signal supplied to the left gate driver 200a and a right gate control signal supplied to the right gate driver 200b. The left gate control signal L_GCS and the right gate control signal R_GCS can be generated by the control signal generator 420.

[0061] As described above, the display panel 100 can include the display area 120 and the non-display area 130 surrounding the display area 120, and the gate lines GL1 to GLg can be included in the display panel 100.

[0062] The left gate driver 200a can be provided in the first non-display area 131 of the non-display area 130 and can output left gate pulses L_GP1 to L_GPg and left gate off signals L_Goff1 to L_Goffg to the gate lines GL1 to GLg. In FIG. 4, reference numerals L_GS1 to L_GSg can refer to first to g.sup.th left gate signals. For example, the first left gate signal L_GS1 can include a first left gate pulse L_GP1 and a first left gate off signal L_Goff1, and the g.sup.th left gate signal L_GSg can include a g.sup.th left gate pulse L_GPg and a g.sup.th left gate off signal L_Goffg.

[0063] The right gate driver 200b can be provided in the second non-display area 132 of the non-display area 130 and can output right gate pulses R_GP1 to R_GPg and right gate off signals R_Goff1 to R_Goffg to the gate lines GL1 to GLg. In FIG. 4, reference numerals R_GS1 to R_GSg can refer to first to g.sup.th right gate signals. For example, the first right gate signal R_GS1 can include a first right gate pulse R_GP1 and a first right gate off signal R_Goff1, and the g.sup.th right gate signal R_GSg can include a g.sup.th right gate pulse R_GPg and a g.sup.th right gate off signal R_Goffg.

[0064] At least one gate line can be further provided on the first gate line GL1 in the non-display area 130, and at least one gate line can be further provided on the g.sup.th gate line GLg in the non-display area 130. In FIG. 1, the display panel 100 is illustrated where two dummy gate lines GL-1 and GL-2 are provided on the first gate line GL1 and two dummy gate lines GL+1 and GL+2 are provided under the g.sup.th gate line GLg.

[0065] In this case, the left gate driver 200a and the right gate driver 200b can output gate pulses and gate off signals to dummy gate lines.

[0066] The left gate driver 200a can include first to g.sup.th left gate stages L_Stage 1 to L_Stage g. Each of the first to g.sup.th left gate stages L_Stage 1 to L_Stage g can output at least one gate pulse. In the following description, when all gate pulses should be described, the order of gate pulses is not needed, or it is not required to limit a gate driver which outputs a gate pulse, a gate pulse can be used as simple expression. When a generic name for all stages is needed or the order of gate pulses is not needed, a stage can be used as simple expression. When a generic name for all gate off signals is needed or the order of gate off signals is not needed, a gate off signal can be used as simple expression. Further, in the following description, a stage which outputs an n.sup.th left gate pulse L_GPn and an n.sup.th left gate off signal L_Goffn can be referred to as an n.sup.th left stage L_Stage n. Here, n can be a natural number which is less than or equal to g. For example, n can be a positive integer.

[0067] The right gate driver 200b can include first to g.sup.th right gate stages R_Stage 1 to R_Stage g. Each of the first to g.sup.th right gate stages R_Stage 1 to R_Stage g can output at least one gate pulse. In the following description, a stage which outputs an n.sup.th right gate pulse R_GPn and an n.sup.th right gate off signal R_Goffn can be referred to as an n.sup.th right stage R_Stage n.

[0068] Hereinafter, the present disclosure will be described with reference to the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n. The following descriptions of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n can be identically applied to the other stages.

[0069] FIG. 5 is a diagram schematically illustrating a structure of each of the stages illustrated in FIG. 4, and particularly, is a diagram schematically illustrating the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n.

[0070] Each of the stages can include a plurality of transistors, and gate control signals GCS can be supplied to each of the stages. Each of the stages can generate gate pulses by using various kinds of signals and voltages and can sequentially supply the gate pulses to the gate lines GL1 to GLg.

[0071] To this end, as illustrated in FIG. 5, the n.sup.th left stage L_Stage n can include an n.sup.th left signal generator 210a which includes an n.sup.th left ripple transistor L_Trpn and an n.sup.th left signal output unit 220a which outputs an n.sup.th left gate off signal L_Goffn and an n.sup.th left gate pulse L_GPn, based on an n.sup.th left control signal generated by the n.sup.th left signal generator 210a.

[0072] The n.sup.th right stage R_Stage n can include an n.sup.th right signal generator 210b which includes an n.sup.th right ripple transistor R_Trpn and an n.sup.th right signal output unit 220b which outputs an n.sup.th right gate off signal R_Goffn and an n.sup.th right gate pulse R_GPn, based on an n.sup.th right control signal generated by the n.sup.th right signal generator 210b.

[0073] In this case, the n.sup.th left gate off signal L_Goffn and n.sup.th right gate off signal R_Goffn can be alternately output to an n.sup.th gate line GLn.

[0074] The n.sup.th left signal output unit 220a can include an n.sup.th left pull-up transistor L_Tun which outputs the n.sup.th left gate pulse L_GPn and an n.sup.th left pull-down transistor L_Tdn which outputs the n.sup.th left gate off signal L_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the n.sup.th left pull-up transistor L_Tun.

[0075] The n.sup.th left signal generator 210a can generate signals for driving the n.sup.th left pull-up transistor L_Tun and the n.sup.th left pull-down transistor L_Tdn.

[0076] The n.sup.th right signal output unit 220b can include an n.sup.th right pull-up transistor R_Tun which outputs the n.sup.th right gate pulse R_GPn and an n.sup.th right pull-down transistor R_Tdn which outputs the n.sup.th right gate off signal R_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the n.sup.th right pull-up transistor R_Tun.

[0077] The n.sup.th right signal generator 210b can generate signals for driving the n.sup.th right pull-up transistor R_Tun and the n.sup.th right pull-down transistor R_Tdn.

[0078] First, the n.sup.th left signal generator 210a can include a plurality of transistors. In FIG. 5, in order to describe a basic structure and a basic function of the n.sup.th left signal generator 210a applied to the present disclosure, the n.sup.th left signal generator 210a including three transistors Tst, Trs, and L_Trpn and an inverter IN is illustrated. For example, an example of the n.sup.th left signal generator 210a applied to the present disclosure is schematically illustrated in FIG. 5.

[0079] A start transistor Tst can be turned on by a start signal Vst and can supply a high voltage VD to the left signal output unit 220a through an n.sup.th left Q node L_Qn. The high voltage VD passing through the start transistor Tst can be shifted to a voltage, which is lower than the high voltage, by the inverter IN and can be transferred to an n.sup.th left Qb node L_Qbn.

[0080] When the start transistor Tst is turned on and a reset transistor Trs is turned on by a reset signal Rest, a low voltage GVSS can be supplied to the n.sup.th left Qb node L_Qbn through the reset transistor Trs. The low voltage GVSS can be shifted to a voltage, which is higher than the low voltage, by the inverter IN and can be supplied to the n.sup.th left Qb node L_Qbn. The inverter IN can be formed in various structures including at least one transistor so as to perform a function described above.

[0081] A first terminal of the n.sup.th left ripple transistor L_Trpn can be connected to the n.sup.th left Q node L_Qn, a second terminal of the n.sup.th left ripple transistor L_Trpn can be connected to a first voltage terminal, and a gate of the n.sup.th left ripple transistor L_Trpn can be connected to a gate of the n.sup.th left pull-down transistor L_Tdn which controls an output of the n.sup.th left gate off signal L_Goffn.

[0082] Here, the first voltage terminal can be supplied with the low voltage GVSS. For example, the first voltage terminal can be supplied with the low voltage GVSS for turning off the n.sup.th left pull-up transistor L_Tun.

[0083] A gate of the n.sup.th left ripple transistor L_Trpn and a gate of the n.sup.th left pull-down transistor L_Tdn can be connected to a terminal which is supplied with an n.sup.th left ripple clock L_DCLK(n). Accordingly, the gate of the n.sup.th left ripple transistor L_Trpn and the gate of the n.sup.th left pull-down transistor L_Tdn can be supplied with the n.sup.th left ripple clock L_DCLK(n).

[0084] Second, the n.sup.th right signal generator 210b can include a plurality of transistors. In FIG. 5, in order to describe a basic structure and a basic function of the n.sup.th right signal generator 210b applied to the present disclosure, the n.sup.th right signal generator 210b including three transistors Tst, Trs, and L_Trpn and an inverter IN is illustrated. For example, an example of the n.sup.th right signal generator 210b applied to the present disclosure is schematically illustrated in FIG. 5.

[0085] A start transistor Tst can be turned on by the start signal Vst and can supply the high voltage VD to the right signal output unit 220b through an n.sup.th right Q node R_Qn.

[0086] When the start transistor Tst is turned off and a reset transistor Trs is turned on by the reset signal Rest, the low voltage GVSS can be supplied to the n.sup.th right Q node R_Qn through the reset transistor Trs. The inverter IN can be formed in various structures including at least one transistor.

[0087] A first terminal of the n.sup.th right ripple transistor R_Trpn can be connected to the n.sup.th right Q node R_Qn, a second terminal of the n.sup.th right ripple transistor R_Trpn can be connected to the first voltage terminal, and a gate of the n.sup.th right ripple transistor R_Trpn can be connected to a terminal which is supplied with an n.sup.th right ripple clock R_DCLK(n).

[0088] Therefore, the n.sup.th right ripple clock R_DCLK(n) can be supplied to the gate of the n.sup.th right ripple transistor R_Trpn.

[0089] As described above, the gate of the n.sup.th left ripple transistor L_Trpn can be connected to a gate of the n.sup.th left pull-down transistor L_Tdn which controls an output of the n.sup.th left gate off signal L_Goffn.

[0090] However, the gate of the n.sup.th right ripple transistor R_Trpn may not be connected to the gate of the n.sup.th right pull-down transistor R_Tdn which controls an output of the n.sup.th right gate off signal R_Goffn. The gate of the n.sup.th right pull-down transistor R_Tdn can be connected to a gate of an n+1.sup.th right ripple transistor included in a stage (for example, an n+1.sup.th right stage) next to an n.sup.th right stage R_Stage n. In this case, the gate of the n.sup.th right ripple transistor R_Trpn can be connected to a gate of an n−1.sup.th right pull-down transistor included in a previous stage (for example, an n−1.sup.th right stage) with respect to the n.sup.th right stage R_Stage n.

[0091] To provide an additional description, outputs of the n.sup.th left gate off signal L_Goffn and the n.sup.th right gate off signal R_Goffn can be controlled by Qb nodes included in the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n. In this case, a gate of an n.sup.th left ripple transistor L_Trpn and an n.sup.th left Qb node L_Qbn included in the n.sup.th left stage L_Stage n can be connected to each other, and an n.sup.th right Qb node R_Qbn included in the n.sup.th right stage R_Stage n can be connected to a gate of an n+1.sup.th right ripple transistor included in an n+1.sup.th right stage.

[0092] Third, the n.sup.th left signal output unit 220a can include an n.sup.th left pull-up transistor L_Tun which outputs an n.sup.th left gate pulse L_GPn, and a gate of the n.sup.th left pull-up transistor L_Tun can be connected to an n.sup.th left Q node L_Qn.

[0093] The n.sup.th left signal output unit 220a can include an n.sup.th left pull-down transistor L_Tdn which outputs an n.sup.th left gate off signal L_Goffn, and a gate of the n.sup.th left pull-down transistor L_Tdn can be connected to a gate of an n.sup.th left ripple transistor L_Trpn.

[0094] Fourth, the n.sup.th right signal output unit 220b can include an n.sup.th right pull-up transistor R_Tun which outputs an n.sup.th right gate pulse R_GPn, and a gate of the n.sup.th right pull-up transistor R_Tun can be connected to an n.sup.th right Q node R_Qn.

[0095] The n.sup.th right signal output unit 220b can include an n.sup.th right pull-down transistor R_Tdn which outputs an n.sup.th right gate off signal R_Goffn, and a gate of the n.sup.th right pull-down transistor R_Tdn can be connected to a gate of an n+1.sup.th right ripple transistor included in a stage (for example, an n+1.sup.th right stage) next to the n.sup.th right stage R_Stage n.

[0096] FIG. 6 is a diagram illustrating in detail a structure of each of the stages illustrated in FIG. 4. A basic structure of each of n−1.sup.th to n+1.sup.th left stages L_Stage n−1 to L_Stage n+1 and n−1.sup.th to n+1.sup.th right stages R_Stage n−1 to R_Stage n+1 can be the same as a basic structure of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n described above with reference to FIG. 5. Hereinafter, therefore, descriptions which are the same as or similar to descriptions given above with reference to FIG. 5 are omitted or will be briefly given.

[0097] First, the n−1.sup.th to n+1.sup.th left stages L_Stage n−1 to L_Stage n+1 illustrated in FIG. 6 can be implemented as the same type. Hereinafter, therefore, a structure of the n.sup.th left stage L_Stage n will be described. Comparing with the n.sup.th left stage illustrated in FIG. 5, in the n.sup.th left stage L_Stage n illustrated in FIG. 6, a structure of an inverter IN is illustrated in detail.

[0098] For example, the inverter IN of the n.sup.th left stage L_Stage n illustrated in FIG. 6 can include first to fourth transistors T1 to T4.

[0099] A first terminal and a gate of the first transistor T1 can be connected to a terminal to which an n.sup.th left ripple clock L_DCLK(n) is input, and a second terminal thereof can be connected to a first terminal of the second transistor T2.

[0100] The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, a gate thereof can be connected to an n.sup.th left Q node L_Qn, and a second terminal thereof can be connected to a terminal which is supplied with the low voltage GVSS.

[0101] A first terminal of the third transistor T3 can be connected to the terminal to which the n.sup.th left ripple clock L_DCLK(n) is input, a second terminal thereof can be connected to a first terminal of the fourth transistor T4, and a gate thereof can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.

[0102] The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, a gate thereof can be connected to the n.sup.th left Q node L_Qn, and a second terminal thereof can be connected to the terminal which is supplied with the low voltage GVSS.

[0103] The inverter IN of the n.sup.th left stage L_Stage n can be implemented as various types, in addition to a structure described above.

[0104] A first terminal and a gate of a start transistor Tst of the n.sup.th left stage L_Stage n can be supplied with an n−1.sup.th left gate signal L_GS(n−1) output from a previous stage (for example, the n−1.sup.th left stage L_Stage n−1).

[0105] An n+1.sup.th left gate signal L_GS(n+1) output from a next stage (for example, the n+1.sup.th left stage L_Stage n+1) can be input to a gate of a reset transistor Trs of the n.sup.th left stage L_Stage n.

[0106] A structure and a feature of each of the other elements of the n.sup.th left stage L_Stage n, except differences described above, can be the same as a structure and a feature of the n.sup.th left stage described above with reference to FIG. 5, and thus, detailed descriptions thereof are omitted.

[0107] Second, the n−1.sup.th to n+1.sup.th right stages R_Stage n−1 to R_Stage n+1 illustrated in FIG. 6 can be implemented as the same type. Hereinafter, therefore, a structure of the n.sup.th right stage R_Stage n will be described. Comparing with the n.sup.th right stage illustrated in FIG. 5, in the n.sup.th right stage R_Stage n illustrated in FIG. 6, a structure of an inverter IN is illustrated in detail.

[0108] For example, the inverter IN of the n.sup.th right stage R_Stage n illustrated in FIG. 6 can include first to fourth transistors T1 to T4.

[0109] A first terminal and a gate of the first transistor T1 can be connected to a terminal to which an n.sup.th right ripple clock R_DCLK(n) is input, and a second terminal thereof can be connected to a first terminal of the second transistor T2.

[0110] The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, a gate thereof can be connected to an n.sup.th right Q node R_Qn, and a second terminal thereof can be connected to a terminal which is supplied with the low voltage GVSS.

[0111] A first terminal of the third transistor T3 can be connected to the terminal to which the n.sup.th right ripple clock R_DCLK(n) is input, a second terminal thereof can be connected to a first terminal of the fourth transistor T4, and a gate thereof can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.

[0112] The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, a gate thereof can be connected to the n.sup.th right Q node R_Qn, and a second terminal thereof can be connected to the terminal which is supplied with the low voltage GVSS.

[0113] The inverter IN of the n.sup.th right stage R_Stage n can be implemented as various types, in addition to a structure described above.

[0114] In this case, an arrangement structure of the first to fourth transistors T1 to T4 included in the inverter IN of the n.sup.th right stage R_Stage n can be the same as an arrangement structure of the first to fourth transistors T1 to T4 included in the inverter IN of the n.sup.th left stage L_Stage n.

[0115] A first terminal and a gate of a start transistor Tst of the n.sup.th right stage R_Stage n can be supplied with an n−1.sup.th right gate signal R_GS(n−1) output from a previous stage (for example, the n−1.sup.th right stage R_Stage n−1).

[0116] An n+1.sup.th right gate signal R_GS(n+1) output from a next stage (for example, the n+1.sup.th right stage R_Stage n+1) can be input to a gate of a reset transistor Trs of the n.sup.th right stage R_Stage n.

[0117] A structure and a feature of each of the other elements of the n.sup.th right stage R_Stage n, except differences described above, can be the same as a structure and a feature of the n.sup.th right stage described above with reference to FIG. 5, and thus, detailed descriptions thereof are omitted.

[0118] Hereinafter, a driving method of a display device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 8.

[0119] FIG. 7 is a diagram showing waveforms applied to a display device according to an embodiment of the present disclosure, and FIG. 8 is a diagram illustrating a method of outputting a gate off signal in a display device according to an embodiment of the present disclosure. Hereinafter, the present disclosure will be described with reference to an n.sup.th left stage L_Stage n and an n.sup.th right stage R_Stage n. In the following description, descriptions which are the same as or similar to descriptions given above with reference to FIGS. 1 to 6 are omitted or will be briefly given.

[0120] First, in a first process A, an n−1.sup.th gate signal GSn−1 having a high level can be input as a start signal of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n.

[0121] Therefore, an n.sup.th left Q node L_Qn and an n.sup.th right Q node R_Qn can be charged.

[0122] In a second process B, an n.sup.th left gate clock L_SCCLK(n) and an n.sup.th right gate clock R_SCCLK(n) can have a high level. For example, a phase of the n.sup.th left gate clock L_SCCLK(n) can be the same as that of the n.sup.th right gate clock R_SCCLK(n). Therefore, in FIG. 7, the n.sup.th left gate clock L_SCCLK(n) and the n.sup.th right gate clock R_SCCLK(n) are illustrated as an n.sup.th gate clock SCCLK(n). In the following description, when it is not required to differentiate the n.sup.th left gate clock L_SCCLK(n) from the n.sup.th right gate clock R_SCCLK(n), the n.sup.th gate clock SCCLK(n) can be used.

[0123] Therefore, a level of the n.sup.th left Q node L_Qn and the n.sup.th left gate clock L_SCCLK(n) can be boosted, and thus, the n.sup.th left pull-up transistor L_Tun can be turned on.

[0124] Accordingly, an n.sup.th gate pulse GPn can be output to the n.sup.th gate line GLn through the n.sup.th left pull-up transistor L_Tun.

[0125] In this case, the n.sup.th gate pulse GPn can be output from the n.sup.th right stage R_Stage n, based on the same method.

[0126] Subsequently, in a third process C, an n+1.sup.th gate signal GSn+1 having a high level can be input as a reset signal of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n. Accordingly, the n.sup.th left pull-up transistor L_Tun can be turned off. In this case, the n.sup.th right pull-up transistor R_Tun can also be turned off.

[0127] Subsequently, in the third process C, an n+1.sup.th right ripple clock R_DCLK(n+1) having a high level can be input from an n+1.sup.th right stage R_Stage n+1 to an n.sup.th right Qb node R_Qbn.

[0128] Accordingly, an n_1.sup.th right gate off signal R_Goffn_1st can be output from the n.sup.th right stage R_Stage n to the n.sup.th gate line GLn. The n_1.sup.th right gate off signal R_Goffn_1st can configure an n.sup.th right gate off signal R_Goffn.

[0129] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a low level is input to the n.sup.th right stage R_Stage n, a gate off signal may not be output from the n.sup.th right stage R_Stage n.

[0130] Subsequently, in a fourth process D, the n.sup.th left ripple clock L_DCLK(n) having a high level can be input to an n.sup.th left Qb node L_Qbn.

[0131] Accordingly, an n_2.sup.th left gate off signal L_Goffn_2nd can be output from the n.sup.th left stage L_Stage n to the n.sup.th gate line GLn. The n_2.sup.th left gate off signal L_Goffn_2nd can configure an n.sup.th left gate off signal L_Goffn.

[0132] In this case, a low level can be continuously supplied to an n.sup.th left Q node L_Qn.

[0133] However, the n.sup.th left gate clock L_SCCLK(n) having a high level can be input to the first terminal of the n.sup.th left pull-up transistor L_Tun. Accordingly, ripple can occur in the n.sup.th left Q node due to the n.sup.th left gate clock L_SCCLK(n) having a high level.

[0134] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a high level is supplied to the n.sup.th left Qb node L_Qbn, the n.sup.th left ripple transistor L_Trpn can be turned on. Accordingly, ripple occurring in the n.sup.th left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th left ripple transistor L_Trpn.

[0135] In this case, the n.sup.th right ripple transistor R_Trpn can be driven based on the same method as the n.sup.th left ripple transistor L_Trpn. Accordingly, ripple occurring in the n.sup.th right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th right ripple transistor R_Trpn.

[0136] For example, because a phase of the n.sup.th left ripple clock L_DCLK(n) is the same as that of the n.sup.th right ripple clock R_DCLK(n) and the phase of the n.sup.th left gate clock L_SCCLK(n) is the same as that of the n.sup.th right gate clock R_SCCLK(n), as described above, the same operation can be performed by the nth left stage L_Stage n and the nth right stage R_Stage n.

[0137] Subsequently, in a fifth process E, the n+1.sup.th right ripple clock R_DCLK(n+1) having a high level can be input from the n+1.sup.th right stage R_Stage n+1 to the n.sup.th right Qb node R_Qbn.

[0138] Therefore, an n_3.sup.th right gate off signal R_Goffn_3rd can be output from the n.sup.th right stage R_Stage n to the n.sup.th gate line GLn. The n_3.sup.th right gate off signal R_Goffn_3rd can configure the n.sup.th right gate off signal R_Goffn.

[0139] Finally, in a sixth process F, the n.sup.th left ripple clock L_DCLK(n) having a high level can be input to the n.sup.th left Qb node L_Qbn.

[0140] Therefore, an n_4.sup.th left gate off signal L_Goffn_4th can be output from the n.sup.th left stage L_Stage n to the n.sup.th gate line GLn. The n_4.sup.th left gate off signal L_Goffn_4th can configure the n.sup.th left gate off signal L_Goffn.

[0141] In this case, a low level can be supplied to the n.sup.th left Q node L_Qn. However, the n.sup.th left gate clock L_SCCLK(n) having a high level can be input to a first terminal of the n.sup.th left pull-up transistor L_Tun. Accordingly, ripple can occur in the n.sup.th left Q node due to the n.sup.th left gate clock L_SCCLK(n) having a high level.

[0142] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a high level is supplied to the n.sup.th left Qb node L_Qbn, the n.sup.th left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the n.sup.th left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th left ripple transistor L_Trpn.

[0143] In this case, the n.sup.th right ripple transistor R_Trpn can be driven based on the same method as the n.sup.th left ripple transistor L_Trpn. Accordingly, ripple occurring in the n.sup.th right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th right ripple transistor R_Trpn.

[0144] The third to sixth processes C to F can be repeated until another n.sup.th gate pulse is output from the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n, and thus, the n.sup.th gate off signal can be continuously output to the n.sup.th gate line GLn.

[0145] For example, through the processes described above, n.sup.th gate pulses GPn can be output from the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n to the nth gate line GLn.

[0146] Moreover, as illustrated in FIG. 8, the n_1.sup.th right gate off signal R_Goffn_1st and the n_3.sup.th right gate off signal R_Goffn_3rd can be output from the n.sup.th right stage R_Stage n to the n.sup.th gate line GLn, and the n_2.sup.th left gate off signal L_Goffn_2nd and the n_4.sup.th left gate off signal L_Goffn_4th can be output from the n.sup.th left stage L_Stage n to the n.sup.th gate line GLn.

[0147] In this case, the n_1.sup.th right gate off signal R_Goffn_1st, the n_3.sup.th right gate off signal R_Goffn_3rd, the n_2.sup.th left gate off signal L_Goffn_2nd, and the n_4.sup.th left gate off signal L_Goffn_4th can configure the n.sup.th gate off signal Goffn supplied to the n.sup.th gate line GLn.

[0148] In this case, in FIG. 8, for convenience of description, the n_1.sup.th right gate off signal R_Goffn_1st, the n_3.sup.th right gate off signal R_Goffn_3rd, the n_2.sup.th left gate off signal L_Goffn_2nd, and the n_4.sup.th left gate off signal L_Goffn_4th are shown in a high-level pulse form. However, in the embodiment described above, the n_1.sup.th right gate off signal R_Goffn_1st, the n_3.sup.th right gate off signal R_Goffn_3rd, the n_2.sup.th left gate off signal L_Goffn_2nd, and the n_4.sup.th left gate off signal L_Goffn_4th can be substantially continuous signals having a low level.

[0149] For example, the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n can sequentially output the n.sup.th gate off signal Goffn to the n.sup.th gate line GLn. Accordingly, the n.sup.th gate off signal Goffn can be continuously output to the n.sup.th gate line GLn.

[0150] In the present disclosure, outputs of the n.sup.th left gate pulse L_GPn and the n.sup.th right gate pulse R_GPn can be controlled by the Q nodes included in the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n.

[0151] In this case, the n.sup.th left ripple transistor L_Trpn which is provided in the n.sup.th left stage L_Stage n to remove ripple occurring in the n.sup.th left Q node L_Qn of the n.sup.th left stage L_Stage n and the n.sup.th right ripple transistor R_Trpn which is provided in the n.sup.th right stage R_Stage n to remove ripple occurring in the n.sup.th right Q node R_Qn of the n.sup.th right stage R_Stage n can simultaneously and continuously perform an on operation and an off operation.

[0152] Because each of the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn repeats a turn-on operation and a turn-off operation, the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn may not be degraded, and a speed at which the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn are degraded can be reduced. Accordingly, the reliability of the display device according to the present disclosure including the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn can be enhanced.

[0153] Hereinafter, features of the present disclosure will be described.

[0154] First, in the present disclosure, a phase of the n.sup.th left gate clock L_SCCLK(n) supplied to the n.sup.th left stage L_Stage n to generate the n.sup.th left gate pulse L_GPn can be the same as that of the n.sup.th left ripple clock L_DCLK(n) supplied for driving the n.sup.th left ripple transistor L_Trpn, and a phase of the n.sup.th right gate clock R_SCCLK(n) supplied to the n.sup.th right stage R_Stage n to generate the n.sup.th right gate pulse R_GPn can be the same as that of the n.sup.th right ripple clock R_DCLK(n) supplied for driving the n.sup.th right ripple transistor R_Trpn.

[0155] For example, the n.sup.th left ripple transistor L_Trpn can be turned on by the n.sup.th left gate clock L_SCCLK(n) having a high level only when ripple occurs in the n.sup.th left Q node L_Qn, and the n.sup.th right ripple transistor R_Trpn can be turned on by the n.sup.th right gate clock R_SCCLK(n) having a high level only when ripple occurs in the n.sup.th right Q node R_Qn. Accordingly, as described above, a speed at which the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn are degraded can be reduced.

[0156] Second, a phase of the n.sup.th left ripple clock L_DCLK(n) supplied for driving the n.sup.th left ripple transistor L_Trpn can be the same as that of the n.sup.th right ripple clock R_DCLK(n) supplied for driving the n.sup.th right ripple transistor R_Trpn.

[0157] For example, the n.sup.th left ripple clock L_DCLK(n) can be supplied to a gate of the n.sup.th left ripple transistor L_Trpn, the n.sup.th right ripple clock R_DCLK(n) can be supplied to a gate of the n.sup.th right ripple transistor R_Trpn, and a phase of the n.sup.th left ripple clock L_DCLK(n) can be the same as that of the n.sup.th right ripple transistor R_Trpn.

[0158] Therefore, the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn can simultaneously perform an on operation and an off operation.

[0159] Third, when the n.sup.th left ripple transistor L_Trpn is turned on, the n.sup.th left gate off signal L_Goffn can be output from the n.sup.th left stage L_Stage n to the n.sup.th gate line GLn, and when the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn are turned off, the n.sup.th right gate off signal R_Goffn can be output from the n.sup.th right stage R_Stage n to the n.sup.th gate line GLn.

[0160] For example, the n.sup.th left gate off signal L_Goffn output from the n.sup.th left stage L_Stage n and the n.sup.th right gate off signal R_Goffn output from the n.sup.th right stage R_Stage n can be alternately output to the n.sup.th gate line GLn.

[0161] To provide an additional description, in the present disclosure, because a gate off signal is alternately output from two stages which are provided at both sides of a gate line, the gate off signal can be continuously supplied to the gate line. Therefore, the gate line may not be floated, and thus, switching transistors connected to the gate line may not be abnormally driven. Accordingly, the reliability of a display device can be enhanced.

[0162] FIG. 9 is another diagram illustrating in detail a structure of each of the stages illustrated in FIG. 4. A basic structure of each of n−1.sup.th to n+1.sup.th left stages L_Stage n−1 to L_Stage n+1 and n−1.sup.th to n+1.sup.th right stages R_Stage n−1 to R_Stage n+1 illustrated in FIG. 9 can be the same as a basic structure of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n described above with reference to FIG. 5. Hereinafter, therefore, descriptions which are the same as or similar to descriptions given above with reference to FIGS. 5 and 6 are omitted or will be briefly given, and particularly, features of stages illustrated in FIG. 9 will be briefly described. In FIG. 9, n can be a natural number which is less than or equal to g/2 and can be an even number.

[0163] First, a structure of an n.sup.th left signal generator 210a of the n.sup.th left stage L_Stage n illustrated in FIG. 9 can be the same as that of the n.sup.th left signal generator 210a of the n.sup.th left stage L_Stage n illustrated in FIG. 6.

[0164] Second, the n.sup.th left signal output unit 220a illustrated in FIG. 6 can include only the n.sup.th left pull-up transistor L_Tun.

[0165] However, an n.sup.th left signal output unit 220a illustrated in FIG. 9 can include an n.sup.th left pull-up transistor L_Tun and an n_2.sup.th left pull-up transistor L_Tun_2.

[0166] In describing the n.sup.th left signal output unit 220a illustrated in FIG. 9, the n.sup.th left pull-up transistor L_Tun can be referred to as an n_1.sup.th left pull-up transistor L_Tun_1. For example, a gate of the n_1.sup.th left pull-up transistor L_Tun_1 illustrated in FIG. 9 can be connected to an n.sup.th left Q node.

[0167] A gate of the n_2.sup.th left pull-up transistor L_Tun_2 can also be connected to the n.sup.th left Q node.

[0168] Third, the n.sup.th left signal output unit 220a illustrated in FIG. 6 can include only the n.sup.th left pull-down transistor L_Tdn.

[0169] However, the n.sup.th left signal output unit 220a illustrated in FIG. 9 can include an n.sup.th left pull-down transistor L_Tdn and an n_2.sup.th left pull-down transistor L_Tdn_2. The n_2.sup.th left pull-down transistor L_Tdn_2 can be connected to the n.sup.th left pull-up transistor L_Tun.

[0170] In describing the n.sup.th left signal output unit 220a illustrated in FIG. 9, the n.sup.th left pull-down transistor L_Tdn can be referred to as an n_1.sup.th left pull-down transistor L_Tdn_1. For example, a gate of the n_1.sup.th left pull-down transistor L_Tdn_1 illustrated in FIG. 9 can be connected to an n.sup.th left Qb node L_Qbn.

[0171] A gate of the n_2.sup.th left pull-down transistor L_Tdn_2 can also be connected to the n.sup.th left Qb node L_Qbn. Therefore, the gate of the n_2.sup.th left pull-down transistor L_Tdn_2 can also be connected to a gate of an n.sup.th left ripple transistor L_Trpn.

[0172] Fourth, a structure of an n.sup.th right signal generator 210b of the n.sup.th right stage R_Stage n illustrated in FIG. 9 can be the same as that of the n.sup.th right signal generator 210b of the n.sup.th right stage R_Stage n illustrated in FIG. 6.

[0173] Fifth, the n.sup.th right signal output unit 220b illustrated in FIG. 6 can include only the n.sup.th right pull-up transistor R_Tun.

[0174] However, the n.sup.th right signal output unit 220b illustrated in FIG. 9 can include an n.sup.th right pull-up transistor R_Tun and an n_2.sup.th right pull-up transistor R_Tun_2.

[0175] In describing the n.sup.th right signal output unit 220b illustrated in FIG. 9, the n.sup.th right pull-up transistor R_Tun can be referred to as an n_1.sup.th right pull-up transistor R_Tun_1. For example, a gate of the n_1.sup.th right pull-up transistor R_Tun_1 illustrated in FIG. 9 can be connected to an n.sup.th right Q node R_Qn.

[0176] A gate of the n_2.sup.th right pull-up transistor R_Tun_2 can also be connected to the n.sup.th right Q node R_Qn.

[0177] Sixth, the n.sup.th right signal output unit 220b illustrated in FIG. 6 can include only the n.sup.th right pull-down transistor R_Tdn.

[0178] However, the n.sup.th right signal output unit 220b illustrated in FIG. 9 can include an n.sup.th right pull-down transistor R_Tdn and an n_2.sup.th right pull-down transistor R_Tdn_2. The n_2.sup.th right pull-down transistor R_Tdn_2 can be connected to the n_2.sup.th right pull-up transistor R_Tun_2.

[0179] In describing the n.sup.th right signal output unit 220b illustrated in FIG. 9, the n.sup.th right pull-down transistor R_Tdn can be referred to as an n_1.sup.th right pull-down transistor R_Tdn_1. In this case, a gate of the n_1.sup.th right pull-down transistor R_Tdn_1 illustrated in FIG. 9 can be connected to a gate of an n+1.sup.th right ripple transistor R_Trpn+1 included in an n+1.sup.th stage.

[0180] A gate of the n_2.sup.th right pull-down transistor R_Tdn_2 can be connected to a gate of an n−1.sup.th right ripple transistor R_Trpn−1 included in an n−1.sup.th right stage R_Stage n−1.

[0181] For example, the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n illustrated in FIG. 9 can be connected to two gate lines GL2n−1 and GL2n and can output a gate pulse and a gate off signal to each of the two gate lines GL2n−1 and GL2n.

[0182] Hereinafter, a driving method of a display device according to an embodiment of the present disclosure including the stages illustrated in FIG. 9 will be described with reference to FIGS. 9 and 10.

[0183] FIG. 10 is a diagram showing waveforms applied to the stages illustrated in FIG. 9. Hereinafter, the present disclosure will be described with reference to an n.sup.th left stage L_Stage n and an n.sup.th right stage R_Stage n. In the following description, descriptions which are the same as or similar to descriptions given above with reference to FIGS. 1 to 9 are omitted or will be briefly given.

[0184] First, in a first process H, an n−1.sup.th gate signal GSn−1 having a high level can be input as a start signal of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n.

[0185] Therefore, an n.sup.th left Q node L_Qn and an n.sup.th right Q node R_Qn can be charged.

[0186] In a second process I, an n.sup.th left gate clock L_SCCLK(n) and an n+1.sup.th left gate clock L_SCCLK(n+1) can be sequentially shifted to a high level, and an n.sup.th right gate clock R_SCCLK(n) and an n+1.sup.th right gate clock R_SCCLK(n+1) can be sequentially shifted to a high level. For example, a phase of the n.sup.th left gate clock L_SCCLK(n) can be the same as that of the n.sup.th right gate clock R_SCCLK(n), and a phase of the n+1.sup.th left gate clock L_SCCLK(n+1) can be the same as that of the n+1.sup.th right gate clock R_SCCLK(n+1). Therefore, in FIG. 9, the n.sup.th left gate clock L_SCCLK(n) and the n.sup.th right gate clock R_SCCLK(n) are illustrated as an n.sup.th gate clock SCCLK(n), and the n+1.sup.th left gate clock L_SCCLK(n+1) and the n+1.sup.th right gate clock R_SCCLK(n+1) are illustrated as an n+1.sup.th gate clock SCCLK(n+1). In the following description, when it is not required to differentiate the n.sup.th left gate clock L_SCCLK(n) from the n.sup.th right gate clock R_SCCLK(n), the n.sup.th gate clock SCCLK(n) can be used, and when it is not required to differentiate the n+1.sup.th left gate clock L_SCCLK(n+1) from the n+1.sup.th right gate clock R_SCCLK(n+1), the n+1.sup.th gate clock SCCLK(n+1) can be used.

[0187] Therefore, a level of the n.sup.th left Q node L_Qn can be boosted along with the n.sup.th left gate clock L_SCCLK(n) and the n+1.sup.th left gate clock L_SCCLK(n+1), and thus, the n_1.sup.th left pull-up transistor L_Tun_1 and the n_2.sup.th left pull-up transistor L_Tun_2 can be turned on.

[0188] Accordingly, a 2n−1.sup.th gate pulse GP2n−1 and an 2n.sup.th gate pulse GP2n can be sequentially output to the 2n−1.sup.th gate line GL2n−1 and the 2n.sup.th gate line GL2n through the n.sup.th left pull-up transistor L_Tun.

[0189] In this case, the 2n−1.sup.th gate pulse GP2n−1 and the 2n.sup.th gate pulse GP2n can be output from the n.sup.th right stage R_Stage n, based on the same method.

[0190] Subsequently, in a third process J, an n+1.sup.th gate signal GSn+1 having a high level can be input as a reset signal of each of the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n. Accordingly, the n_1.sup.th left pull-up transistor L_Tun_1 and the n_2.sup.th left pull-up transistor L_Tun_2 can be turned off.

[0191] In this case, the n_1.sup.th right pull-up transistor R_Tun_1 and the n_2.sup.th right pull-up transistor R_Tun_2 can also be turned off.

[0192] Subsequently, in the third process J, an n+1.sup.th right ripple clock R_DCLK(n+1) having a high level can be input from an n+1.sup.th right stage R_Stage n+1 to an n.sup.th right Qb node R_Qbn. Therefore, a 2n-1_1.sup.th right gate off signal R_Goff2n−1_1st can be output from the n.sup.th right stage R_Stage n to a 2n−1.sup.th gate line GL2n−1. The 2n−1_1.sup.th right gate off signal R_Goff2n-1_1st can configure a 2n−1.sup.th right gate off signal.

[0193] In this case, an n−1.sup.t right ripple clock R_DCLK(n−1) having a high level can be input from the n−1.sup.th right stage R_Stage n−1 to an n_2.sup.th right Qb node R_Qbn_2. Therefore, a 2n_1.sup.th right gate off signal R_Goff2n_1st can be output from the n.sup.th right stage R_Stage n to the 2n.sup.th gate line GL2n. The 2n_1.sup.th right gate off signal R_Goff2n_1st can configure a 2n.sup.th right gate off signal.

[0194] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a low level is supplied to the n.sup.th left stage R_Stage n, a gate off signal may not be output from the n.sup.th left stage R_Stage n.

[0195] Subsequently, in a fourth process K, the n.sup.th left ripple clock L_DCLK(n) having a high level can be input to the n.sup.th left Qb node L_Qbn. Therefore, a 2n−1_2.sup.th left gate off signal L_Goff2n−1_2nd can be output from the n.sup.th left stage R_Stage n to the 2n−1.sup.th gate line GL2n−1. The 2n−1_2.sup.th left gate off signal L_Goff2n−1_2nd can configure a 2n−1.sup.th left gate off signal.

[0196] In this case, a 2n_2.sup.th left gate off signal L_Goff2n_2nd can be output from the n.sup.th left stage R_Stage n to the 2n.sup.th gate line GL2n. The 2n_2.sup.th left gate off signal L_Goff2n_2nd can configure a 2n.sup.th left gate off signal.

[0197] In this case, a low level can be continuously supplied to the n.sup.th left Q node L_Qn. However, the n.sup.th left gate clock L_SCCLK(n) and the n+1.sup.th left gate clock L_SCCLK(n+1) each having a high level can be sequentially input to a first terminal of the n_1.sup.th left pull-up transistor L_Tun_1 and the n_2.sup.th left pull-up transistor L_Tun_2. Accordingly, ripple can occur in the n.sup.th left Q node L_Qn due to the n.sup.th left gate clock L_SCCLK(n) and the n+1.sup.th left gate clock L_SCCLK(n+1) each having a high level.

[0198] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a high level is supplied to the n.sup.th left Qb node L_Qbn, the n.sup.th left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the n.sup.th left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th left ripple transistor L_Trpn.

[0199] In this case, the n.sup.th right ripple transistor R_Trpn can be driven based on the same method as the n.sup.th left ripple transistor L_Trpn. Accordingly, ripple occurring in the n.sup.th right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th right ripple transistor R_Trpn.

[0200] Subsequently, in a fifth process L, the n+1.sup.th right ripple clock R_DCLK(n+1) having a high level can be input from the n+1.sup.th right stage R_Stage n+1 to an n_1.sup.th right Qb node R_Qbn_1. Therefore, a 2n−1_3.sup.th right gate off signal R_Goff2n−1_3rd can be output from the n.sup.th right stage R_Stage n to the 2n−1.sup.th gate line GL2n−1. The 2n−1_3.sup.th right gate off signal R_Goff2n−1_3rd can configure a 2n−1.sup.th right gate off signal.

[0201] In this case, the n-1th right ripple clock R_DCLK(n−1) having a high level can be input from the n−1.sup.th right stage R_Stage n−1 to the n_2th right Qb node R_Qbn_2. Therefore, a 2n_3.sup.th right gate off signal R_Goff2n_3rd can be output from the n.sup.th right stage R_Stage n to the 2n.sup.th gate line GL2n. The 2n_3.sup.th right gate off signal R_Goff2n_3rd can configure a 2n.sup.th right gate off signal.

[0202] Finally, in a sixth process M, the n.sup.th left ripple clock L_DCLK(n) having a high level can be input to the n.sup.th left Qb node L_Qbn.

[0203] Therefore, a 2n−1_4.sup.th left gate off signal L_Goff2n−1_4th can be output from the n.sup.th left stage L_Stage n to the 2n−1.sup.th gate line GL2n−1. The 2n−1_4.sup.th left gate off signal L_Goff2n−1_4th can configure a 2n−1.sup.th gate off signal.

[0204] Moreover, a 2n_4.sup.th left gate off signal L_Goff2n_4th can be output from the n.sup.th left stage to the 2n.sup.th gate line GL2n. The 2n_4.sup.th left gate off signal L_Goff2n_4th can configure a 2n.sup.th left gate off signal.

[0205] In this case, a low level can be continuously supplied to the n.sup.th left Q node L_Qn. However, the n.sup.th left gate clock L_SCCLK(n) having a high level can be input to a first terminal of the n_1.sup.th left pull-up transistor L_Tun_1, and the n+1.sup.th left gate clock L_SCCLK(n+1) having a high level can be input to a first terminal of the n_2.sup.th left pull-up transistor L_Tun_2. Accordingly, ripple can occur in the n.sup.th left Q node L_Qn due to the n.sup.th left gate clock L_SCCLK(n) and the n+1.sup.th left gate clock L_SCCLK(n+1) each having a high level.

[0206] In this case, because the n.sup.th left ripple clock L_DCLK(n) having a high level is supplied to the n.sup.th left Qb node L_Qbn, the n.sup.th left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the n.sup.th left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th left ripple transistor L_Trpn.

[0207] In this case, the n.sup.th right ripple transistor R_Trpn can be driven based on the same method as the n.sup.th left ripple transistor L_Trpn. Accordingly, ripple occurring in the n.sup.th right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the n.sup.th right ripple transistor R_Trpn.

[0208] The third to sixth processes J to M can be repeated until another n.sup.th gate pulse is output from the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n, and thus, the 2n−1.sup.th gate off signal can be continuously output to the 2n−1.sup.th gate line GL2n−1 and the 2n.sup.th gate off signal can be continuously output to the 2n.sup.th gate line GL2n.

[0209] In this case, the 2n−1_1.sup.th right gate off signal R_Goff2n−1_1st, the 2n−1_3.sup.th right gate off signal R_Goff2n−1_3rd, the 2n−1_2.sup.th left gate off signal L_Goff2n−1_2nd, and the 2n-1_4.sup.th left gate off signal L_Goff2n−1_4th can configure a 2n−1.sup.th gate off signal supplied to the 2n−1.sup.th gate line.

[0210] For example, the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n can sequentially output the 2n−1.sup.th gate off signal to the 2n−1.sup.th gate line GL2n−1. Accordingly, the 2n-1.sup.th gate off signal can be continuously output to the 2n−1.sup.th gate line GL2n−1.

[0211] In this case, the 2n_1.sup.th right gate off signal R_Goff2n_1st, the 2n_3.sup.th right gate off signal R_Goff2n_3rd, the 2n_2.sup.th left gate off signal L_Goff2n_2nd, and the 2n_4.sup.th left gate off signal L_Goff2n_4th can configure a 2n.sup.th gate off signal supplied to the 2n.sup.th gate line.

[0212] For example, the n.sup.th left stage L_Stage n and the n.sup.th right stage R_Stage n can sequentially output the 2n.sup.th gate off signal to the 2n.sup.th gate line GL2n. Accordingly, the 2n.sup.th gate off signal can be continuously output to the 2n.sup.th gate line GL2n.

[0213] In this case, the n.sup.th left ripple transistor L_Trpn which is provided in the n.sup.th left stage L_Stage n to remove ripple occurring in the n.sup.th left Q node L_Qn of the n.sup.th left stage L_Stage n and the n.sup.th right ripple transistor R_Trpn which is provided in the n.sup.th right stage R_Stage n to remove ripple occurring in the n.sup.th right Q node R_Qn of the n.sup.th right stage R_Stage n can simultaneously and continuously perform an on operation and an off operation.

[0214] Because each of the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn repeats a turn-on operation and a turn-off operation, the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn may not be degraded, and a speed at which the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn are degraded can be reduced. Accordingly, the reliability of the display device according to the present disclosure including the n.sup.th left ripple transistor L_Trpn and the n.sup.th right ripple transistor R_Trpn can be enhanced.

[0215] According to the present disclosure, a ripple transistor for removing ripple occurring in a Q node can repeat an on operation and an off operation, based on a ripple clock. Accordingly, a degradation in the ripple transistor can be prevented, and thus, the reliability of a display device can be enhanced.

[0216] According to the present disclosure, a phase of a gate clock supplied to a pull-up transistor connected to the Q node can be the same as that of a ripple clock for driving the ripple transistor. Therefore, even when the gate clock is supplied to the pull-up transistor, an abnormal signal caused by ripple may not be supplied to the Q node. Accordingly, the pull-up transistor connected to the Q node may not abnormally operate, thereby enhancing the reliability of a display device.

[0217] According to the present disclosure, because a gate off signal is alternately output from two stages which are provided at both sides of a gate line, the gate off signal can be continuously supplied to the gate line. Therefore, the gate line may not be floated, and thus, switching transistors connected to the gate line may not be abnormally driven. Accordingly, the reliability of a display device can be enhanced.

[0218] The above-described feature, structure, and effect of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of the present disclosure can be implemented through combination or modification of other embodiments by those skilled in the art. Therefore, content associated with the combination and modification should be construed as being within the scope of the present disclosure.

[0219] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Thus, it is intended that the present disclosure covers the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.