VERTICAL SILICON JOSEPHSON JUNCTION DEVICE FOR QUBIT APPLICATIONS

Abstract

A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Claims

1. A device comprising: a substrate of epitaxial silicon; a lower superconducting electrode that comprises a superconducting region of the epitaxial silicon; an upper superconducting electrode that comprises a metallic superconductor; and a junction layer, wherein a section of the junction layer between the lower and upper superconducting electrodes forms a junction of the superconducting device.

2. The device of claim 1, wherein the superconducting device is a vertical Josephson Junction (JJ) qubit device.

3. The device of claim 1, wherein the junction layer is a layer of epitaxial silicon grown over the superconducting region of the epitaxial silicon.

4. The device of claim 1, wherein the junction layer is a layer of dielectric.

5. The device of claim 1, wherein the superconducting region is fabricated by implanting the substrate with boron or gallium.

6. The device of claim 1, further comprising a resonator and wiring that comprises the metallic superconductor.

7. The device of claim 1, further comprising a wire in contact with the lower superconducting electrode, the wire comprising the metallic superconductor.

8. The device of claim 1, wherein the junction layer is epitaxial silicon grown at a temperature less than 500 degree Celsius.

9. The device of claim 1, wherein the junction layer is epitaxial silicon having a same crystalline structure as the substrate.

10. The device of claim 1, wherein the metallic superconductor comprises aluminum.

11. A method of fabricating a superconducting device, comprising: providing a substrate of epitaxial silicon; doping the substrate to form a superconducting region as a lower electrode of the superconducting device; growing epitaxial silicon over the substrate and the doped superconducting region as a junction layer of the superconducting device; and depositing a metallic superconductor at the substrate over the junction layer as an upper electrode of the superconducting device.

12. The method of claim 11, wherein the superconducting region is doped with boron or gallium.

13. The method of claim 11, wherein the substrate, the superconducting region, and the junction layer share a contiguous crystalline structure.

14. The method of claim 11, wherein the junction layer is epitaxial silicon grown at a temperature less than 500 degree Celsius.

15. The method of claim 11, further comprising patterning regions of the epitaxial silicon substrate with resist to define contact openings to the superconducting region.

16. The method of claim 15, further comprising performing reactive-ion etching (ME) to remove the grown epitaxial silicon at the defined contact openings.

17. The method of claim 16, wherein the metallic superconductor is deposited over a lift-off lithography stack and the contact openings to form a pattern for a resonator and a wire for the resonator

18. A method of fabricating a superconducting device, comprising: providing a substrate of epitaxial silicon; doping the substrate to form a superconducting region as a lower electrode of the superconducting device; depositing a dielectric layer over the substrate and the doped superconducting region as a junction layer of the superconducting device; and depositing a metallic superconductor at the substrate over the junction layer as an upper electrode of the superconducting device.

19. The method of claim 18, wherein the superconducting region is doped with boron or gallium.

20. The method of claim 18, wherein the metallic superconductor comprises aluminum.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.

[0008] FIG. 1 illustrates an example vertical JJ qubit device that is fabricated from crystalline silicon material.

[0009] FIG. 2A shows the substrate of epitaxial silicon and a pattern of resist over the substrate defining a region for implant.

[0010] FIG. 2B shows B or Ga implanted onto the substrate at the region defined by the resist.

[0011] FIG. 2C shows a layer of epitaxial silicon being grown over the substrate, including over the implanted superconducting region.

[0012] FIG. 2D shows resist being applied to the substrate over the epitaxial layer to form pattern for creating contact openings, including a contact opening.

[0013] FIG. 2E shows etching process being applied to remove the grown epitaxial silicon at the contact openings defined by the resist pattern.

[0014] FIG. 2F shows lift-off lithography stack being applied to the substrate to define pattern for the upper electrode and wiring.

[0015] FIG. 2G shows metal being deposited over the lift-off lithography stack, including over contact openings.

[0016] FIG. 2H shows the lithography stack being lifted off, leaving upper electrode and wiring in contact with the implanted region as the lower electrode.

[0017] FIG. 3 conceptually illustrates a process for fabricating a vertical JJ qubit device.

DETAILED DESCRIPTION

[0018] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0019] There are three types of doped-semiconductor material that behave drastically different at low temperatures: (i) a doped semiconductor that becomes insulator at low temp; (ii) a doped semiconductor that continues to be conductive at low temp; and (iii) a special highly doped semiconductor that becomes superconducting at low temp. The normal doped semiconductor has dopant and holes concentration from about 1×10.sup.19/cm.sup.3 to about 3×10.sup.20/cm.sup.3. The doped semiconductor (that becomes insulator at low temp) has dopant and holes concentration below 1×10.sup.19/cm.sup.3.

[0020] The superconducting dopant-semiconductor alloy is typically only possible for p-type dopants. For Silicon (Si), Silicon-Germanium (SiGe), or Silicon-Germanium-Tin (SiGeSn) semiconductors, the corresponding p-type dopants are Boron (B), Aluminum (Al), Gallium (Ga), and Indium (In). For pure Si, B may be preferred due to its high solid solubility in Si. For SiGe, a mixture of B, Al, Ga can be used. For pure Ge, Al or Ga may be preferred due to their high solid solubility in Ge. These superconducting materials are “metastable,” meaning that the concentration of homogeneously distributed dopants in the crystal lattice exceeds the maximum solid solubility of such dopant in particular host semiconductor. The excess amount of dopants (in excess of solid solubility at a particular temperature) will precipitate out, forming clusters/inclusions when annealed, which is not desirable. Hence, these materials are created using non-equilibrium, kinetic growth techniques, such as gas phase, solid phase, or liquid phase epitaxy. Solid and liquid phase epitaxy may employ amorphization by ion implanter and short-scale (from nanosecond to millisecond) laser annealing to re-grow of reform the material. Once formed, the metastable alloys are to be preserved, minimizing any prolonged exposure (e.g., minutes) to elevated temperature (e.g., above 400° C.). The concentration of free holes in such materials exceeds 5×10.sup.20 holes/cm.sup.3 and often exceeds 1×10.sup.21 holes/cm.sup.3. Abundance of free holes making such material superconducting at a low temperature.

[0021] A vertical Josephson Junction (JJ) device may have a vertical structure of (iii)-(ii)-(i)-(ii)-(iii) layers. The (ii) layer is to be minimized but never reach zero due to a finite vertical abruptness of p-type dopants. In other words, in one aspect, the dopant abruptness is to be improved down to less than 1-2 nm/decade (lower being better as it is more abrupt), which put certain limits of how these doped layers are created and what processes are allowed afterwards to keep the abruptness in check to minimize dopant diffusion.

[0022] In most Josephson Junction (JJ) devices the electrodes are formed by a convectional low temperature superconductor and the tunnel barrier is formed by a metal oxide (most common is Al.sub.2O.sub.3). Some embodiments of the disclosure provide a vertical JJ qubit device that is fabricated from crystalline silicon material. In some embodiments, such a JJ qubit device is fabricated with epitaxial silicon as the junction material, doped epitaxial silicon as a lower superconducting electrode, and metallic superconductor as an upper electrode. Defect is minimized because the substrate, the epitaxial silicon of the junction layer, and the doped epitaxial silicon of the lower super conducting electrode share a contiguous crystalline structure. In some embodiments, resonator and/or capacitor of the JJ device is also fabricated using the metallic superconductor. In some embodiments, the doped epitaxial silicon is implanted with gallium or boron.

[0023] FIG. 1 illustrates an example vertical JJ qubit device 100 that is fabricated from crystalline silicon material. The figure shows a top plan view and a cross section view of the JJ qubit device 100. As illustrated, the vertical JJ device 100 a superconducting device that includes a substrate of epitaxial silicon 110, a lower superconducting electrode 120 that is a superconducting region 115 of the epitaxial silicon, and an upper superconducting electrode 130 that is a metallic superconductor. The device 100 also includes a junction layer 140. A section 150 of the junction layer 140 between the lower and upper superconducting electrodes forms a junction of the JJ qubit device 100.

[0024] The superconducting region 115 may be fabricated by doping the substrate 110 with boron or gallium (so the superconducting region 115 is also referred to as the implanted region or the doped region of the epitaxial silicon substrate). The junction layer 140 is a layer of epitaxial silicon grown over the superconducting region 115 of the epitaxial silicon substrate. In some embodiments, the epitaxial silicon of the junction layer is grown in temperature less than 500 degree Celsius. In some embodiments, the junction layer 140 has a same crystalline (monocrystalline) structure as the substrate 110. In some other embodiments, the junction layer is a layer of dielectric (e.g., Silicon Germanium, Silicon Oxide, Aluminum Oxide, etc.).

[0025] The metallic superconductor used to form the upper electrode 130 may be aluminum or another elemental superconductor (e.g., Mercury, Molybdenum, Niobium, Lead, Tin, Thallium, Titanium, Vanadium, etc.). The metallic conductor may also be used to form a wiring for a capacitor or resonator in the device 100. For example, the metallic conductor forms a wire 160 that is in contact with the lower superconducting electrode 120. Superconducting resonators have multitude of applications in superconducting quantum circuits, such as readout and qubit coupling.

[0026] FIGS. 2A-2H illustrates stages of fabricating the example vertical JJ qubit device 100. Each figure shows a top plan view and a frontal cross section view of the device.

[0027] FIG. 2A shows the substrate of epitaxial silicon 110 and a pattern of resist 210 over the substrate defining a region for implant. FIG. 2B shows B or Ga implanted onto the substrate at the region defined by the resist (and with the resist removed). The implanted region forms a superconducting region to be lower electrode 120. The implanted B or Ga is then annealed into the silicon substrate.

[0028] FIG. 2C shows a layer of epitaxial silicon being grown over the substrate 110, including over the implanted superconducting region. This layer of epitaxial silicon is to be the junction layer 140. In some embodiments, the layer of epitaxial silicon is grown at low temperature (e.g., <500° C.). The grown epitaxial silicon 140 may have a same crystalline structure as the substrate 110.

[0029] FIG. 2D shows resist 230 being applied to the substrate over the epitaxial layer to form pattern for creating contact openings, including a contact opening 240. FIG. 2E shows etching process being applied to remove the grown epitaxial silicon at the contact openings defined by the resist pattern. The contact opening 240 now exposes the implanted region 120 for metallic contact. The resist material is removed. In some embodiments, the etching process is reactive-ion etching (RIE), which is an etching technology used in microfabrication. RIE uses chemically reactive plasma to remove material deposited on wafers. The plasma is generated under low pressure (e.g., vacuum) by an electromagnetic field. High-energy ions from the plasma attack the wafer surface and react with it.

[0030] FIG. 2F shows lift-off lithography stack 260 being applied to the substrate (over the epitaxial silicon layer and contact openings) to define pattern for the upper electrode 130 and wiring. Lift off lithography or lift-off process is a method of creating structures (patterning) of a target material on the surface of a substrate using a sacrificial material (e.g., photoresist). It is an additive technique as opposed to more subtracting technique like etching.

[0031] FIG. 2G shows metal being deposited over the lift-off lithography stack, including over contact openings. FIG. 2H shows the lithography stack 260 being lifted off, leaving upper electrode 130 and wiring 160 in contact with the implanted region 120 as the lower electrode. A Josephson Junction is formed at the junction layer between the upper electrode 130 and the lower electrode.

[0032] FIG. 3 conceptually illustrates a process 300 for fabricating a vertical JJ qubit device, consistent with an illustrative embodiment. In some embodiments, one or more semiconductor manufacturing equipment are used to perform the process 300.

[0033] At block 310, the process provides a substrate of epitaxial silicon. Epitaxy refers to a type of crystal growth or material deposition in which new crystalline layers are formed with one or more well-defined orientations with respect to the crystalline seed layer. The substrate may be a slice of an epitaxial silicon wafer, which is a wafer of semiconducting material made by epitaxial growth for use in microelectronics.

[0034] At block 320, the process implants or dopes the substrate with boron or gallium to form a superconducting region as a lower electrode of the superconducting device. The process may apply resist to form patterns of regions of the epitaxial silicon substrate to define the superconducting region. Implanting the substrate to form a superconducting region is described above by reference to FIGS. 2A-B.

[0035] At block 330, the process grows epitaxial silicon over the substrate and the doped superconducting region as a junction layer of the superconducting device. In some embodiments, the junction layer is grown in temperature less than 500 degree Celsius. The epitaxial silicon of the junction layer may be the same material as the substrate, typically monocrystalline silicon, or another type of material with specific desirable qualities. Growing the junction layer is described above by reference to FIG. 2C.

[0036] At block 340, the process deposits a metallic superconductor at the substrate over the junction layer as an upper electrode of the superconducting device. The metallic superconductor may be aluminum or another elemental superconductor such as Mercury, Molybdenum, Niobium, Lead, Tin, Thallium, Titanium, Vanadium, etc. In some embodiments, the metallic superconductor is deposited to form a resonator and/or capacitor and a wire. The process may apply resist to form patterns of regions of the epitaxial silicon substrate to define contact openings to the superconducting region and perform reactive-ion etching (ME) to remove the grown epitaxial silicon at the contact openings. Etching for contact openings is described above by reference to FIG. 2D-E. The metallic superconductor may be deposited over a lift-off lithography stack and the contact openings for forming pattern for the resonator and/or capacitor and the wire. Depositing superconductors is described above by reference FIG. 2F-H.

[0037] The flowchart in FIG. 3 illustrates the operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart may represent a module, segment, or portion of instructions for implementing the specified operation(s). In some alternative implementations, the operations noted in the blocks may occur out of the order noted in the FIG. 3. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the operations involved.

[0038] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.