Method for balancing a chain-link converter in delta configuration

Abstract

A method for controlling a chain-link power converter including three phase legs, each of which phase legs includes a plurality of series-connected converter cells, each of the cells including a DC capacitor, the phase legs being connected in a delta configuration. The method includes detecting an unsymmetrical voltage condition at a terminal of the converter; determining a ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter, based on the detected unsymmetrical voltage condition; calculating the compound current comprising the zero sequence component and the negative sequence component in accordance with the determined ratio; and injecting the compound current into the converter to control the converter in view of the detected unsymmetrical voltage condition.

Claims

1. A method for controlling a chain-link power converter, said converter comprising three phase legs, each of which phase legs comprising a plurality of series-connected converter cells, each of the cells comprising a DC capacitor, the phase legs being connected in a delta configuration, the method comprising: detecting an unsymmetrical voltage condition at a terminal of the converter; determining a ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter, wherein an amount of the negative sequence component is not zero, based on the detected unsymmetrical voltage condition; calculating the compound current comprising the zero sequence component and the negative sequence component in accordance with the determined ratio; and injecting the compound current into the converter to control the converter in view of the detected unsymmetrical voltage condition.

2. The method of claim 1, wherein the method is performed by a control apparatus connected to or comprised in the chain-link power converter.

3. The method of claim 2, wherein the ratio between zero sequence current and negative sequence current is determined to be within the range of 2:8 to 8:2.

4. The method of claim 2, wherein the determining a ratio comprises determining an amount of negative sequence current in the compound current set by the variable K, 0<K<1, where K is calculated according to equation 3: K=max(K.sub.2,(1−K.sub.I0I2)) Equation 3.

5. The method of claim 1, wherein the ratio between zero sequence current and negative sequence current is determined to be within the range of 2:8 to 8:2.

6. The method of claim 2, wherein the unsymmetrical voltage condition is a 1-phase, a 2-phase-to-ground or a 2-phase-to-phase fault condition corresponding to a voltage dip of at least 30%.

7. The method of claim 5, wherein the unsymmetrical voltage condition is a 1-phase, a 2-phase-to-ground or a 2-phase-to-phase fault condition corresponding to a voltage dip of at least 30%.

8. The method of claim 5, wherein the determining a ratio comprises determining an amount of negative sequence current in the compound current set by the variable K, 0<K<1, where K is calculated according to equation 3: K=max(K.sub.2,(1−K.sub.I0I2)) Equation 3.

9. The method of claim 1, wherein the unsymmetrical voltage condition is a 1-phase, a 2-phase-to-ground or a 2-phase-to-phase fault condition corresponding to a voltage dip of at least 30%.

10. The method of claim 9, wherein the determining a ratio comprises determining an amount of negative sequence current in the compound current set by the variable K, 0<K<1, where K is calculated according to equation 3: K=max(K.sub.2,(1−K.sub.I0I2)) Equation 3.

11. The method of claim 1, wherein the determining a ratio comprises determining an amount of negative sequence current in the compound current set by the variable K, 0<K<1, where K is calculated according to equation 3: K=max(K.sub.2,(1−K.sub.I0I2) Equation 3.

12. A computer program product comprising a non-transitory computer-readable storage medium having computer-executable components for causing a control apparatus to perform the method of claim 1 when the computer-executable components are run on processor circuitry comprised in the control apparatus.

13. The method of claim 1, wherein the ratio between zero sequence current and negative sequence current is determined to be within the range of 2:8 to 5:5.

14. The method of claim 1, wherein the unsymmetrical voltage condition is a 1-phase, a 2-phase-to-ground or a 2-phase-to-phase fault condition corresponding to a voltage dip of between 40% and 80%.

15. A control apparatus for controlling a chain-link power converter, said converter comprising three phase legs, each of which phase legs comprising a plurality of series-connected converter cells, each of which cells comprising a DC capacitor, the phase legs being connected in a delta configuration, the control apparatus comprising: processor circuitry; and a storage unit storing instructions that, when executed by the processor circuitry, cause the apparatus to: detect an unsymmetrical voltage condition at a terminal of the converter; determine a ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter, wherein an amount of the negative sequence component is not zero, based on the detected unsymmetrical voltage condition; calculate the compound current comprising the zero sequence component and the negative sequence component in accordance with the determined ratio; and inject the compound current into the converter to control the converter in view of the detected unsymmetrical voltage condition, wherein the control apparatus is integrated in the chain-link power converter.

16. A non-transitory computer-readable storage medium having stored thereon a computer program for controlling a chain-link converter, said converter comprising three phase legs, each of which phase legs comprising a plurality of series-connected converter cells, each of which cells comprising a DC capacitor, the phase legs being connected in a delta configuration, the computer program comprising computer program code which is able to, when run on processor circuitry of a control apparatus for the converter, cause the control apparatus to: detect an unsymmetrical voltage condition at a terminal of the converter; determine a ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter, wherein an amount of the negative sequence component is not zero, based on the detected unsymmetrical voltage condition; calculate the compound current comprising the zero sequence component and the negative sequence component in accordance with the determined ratio; and inject the compound current into the converter to control the converter in view of the detected unsymmetrical voltage condition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic top view of an embodiment of a power converter in accordance with the present invention.

(3) FIG. 2 is a schematic flow chart of an embodiment of a method of the present invention.

(4) FIG. 3 is a schematic illustration of an embodiment of a computer program product of the present invention.

(5) FIG. 4 is a simulation example graph showing the phase leg current at different voltage dips for different control currents.

DETAILED DESCRIPTION

(6) Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

(7) FIG. 1 schematically illustrates an embodiment of a chain-link converter 1 of the present invention. In the embodiment of FIG. 1, the chain-link converter 1 is in a delta configuration and in a full-bridge configuration. The converter 1 is configured to transform DC current to three-phase AC current. The converter 1 comprises three phase legs 2a-c. Each of the phase legs 2 comprises a plurality of series-connected converter cells 3, each comprising a DC capacitor. In one of the converter cells 3, the DC capacitor has been marked with “+” and “−” signs as well as a notation that there is a direct current U.sub.DC. Of course, the same is relevant for all cells 3, even if not marked. Each phase leg also comprises a coil 4 for evening out the sinus wave AC constructed by the cells 3 and for controlling the current through the phase leg. Each phase leg 2 corresponds to a line A-C of the electrical network and connecting to the power converter 1 at respective terminals in the “corners” of the delta configuration. The phase legs 2 can be connected in delta-configuration, and can be in either full-bridge confirmation (as in FIG. 1) or in a half-bridge configuration. A control apparatus or controller 10 is associated with the converter 1 in order to control the operation of the converter 1 and inject the compound current discussed herein. The controller 10 comprises processor circuitry ii and a storage unit 12, as well as other circuitry which may be appropriate. In accordance with the present invention, the controller 10 balances the converter 1 by calculating and injecting a compound current into the converter 1 for optimizing the operation of the converter.

(8) FIG. 2 is a flow chart illustrating an embodiment of the method of the present invention. An unsymmetrical voltage condition is detected 101 at a terminal of the converter 1. There may e.g. be sensors such as volt and/or current meters performing measurements at each terminal of the lines A-C, which sensors continuously or periodically reports its measurements to the control apparatus 10. The fault condition may e.g. be a one-phase or two-phase fault, e.g. resulting in voltage drop in one or two of the phases. A ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter 1 is determined 102, based on the detected 101 unsymmetrical voltage condition. Thus, the compound current comprises a negative sequence part and a zero sequence part, but these parts may not be of equal size. Rather the ratio may be determined 102 in accordance with empirical or theoretical functions using the sensor measurements as in-data for optimizing the converter operations such as maximizing the positive sequence output into the network. The compound current comprising the zero sequence component and the negative sequence component is calculated 103 in accordance with the determined 102 ratio. In this way, the compound current is obtained and made ready for injection into the converter 1. The compound current is then injected 104 into the converter 1 to control the converter in view of the detected 101 unsymmetrical voltage condition.

(9) In some embodiments of the present invention, the method is performed by the control apparatus 10, which is connected to or comprised in the chain-link power converter 1. The control apparatus may thus be either remotely situated and controlling the converter 1 from a distance, or the control apparatus 10 may be a part of or integrated into the power converter 1.

(10) In some embodiments of the present invention, the ratio between zero sequence current and negative sequence current is determined 102 to be within the range of 2:8 to 8:2, such as within in the range of 2:8 to 5:5. These may be convenient ranges to use for optimizing the converter. See e.g. example 7 below and FIG. 4.

(11) In some embodiments of the present invention, the unsymmetrical voltage condition is a 1-phase fault condition (or, in other embodiments, a 2-phase-to-ground or a 2-phase-to-phase fault condition) corresponding to a voltage dip of at least 30%, such as between 40% and 80%. The present invention may be especially advantageous for large fault conditions, in which cases the phase leg current may be greatly reduced in comparison to if only zero sequence or only negative sequence current is used. See e.g. example 7 below and FIG. 4.

(12) FIG. 3 illustrates a computer program product 30. The computer program product comprises a computer readable medium 32 comprising a computer program 31 in the form of computer-executable components 31. The computer program/computer-executable components 31 may be configured to cause a control apparatus 10, e.g. as discussed herein for controlling a power converter 1, to perform an embodiment of the method of the present disclosure. The computer program/computer-executable components may be run on the processor circuitry ii of the control apparatus 10 for causing the apparatus to perform the method. The computer program product may e.g. be comprised in the storage unit or memory 12 comprised in the apparatus 10 and associated with the processor circuitry ii. Alternatively, the computer program product 30 may be, or be part of, a separate, e.g. mobile, storage means, such as a computer readable disc, e.g. CD or DVD or hard disc/drive, or a solid state storage medium, e.g. a RAM or Flash memory.

EXAMPLES

(13) The below examples present a feed-forward control function where a compound current comprising both zero sequence and negative sequence components in accordance with the present invention. The examples use simulation in Matlab and the function source is a Matlab m-file, which has been converted into C-code using Matlab Coder.

(14) The FeedForward control function is part of the converter current limiter function, developed for the chain-link converter 1. The FeedForward function computes the negative sequence and zero sequence currents needed to balance the power among the phases during unbalanced operating condition. Since both negative and zero sequence currents can be used, an optimization procedure is presented in order to minimize the current flowing in the legs 2 and in order to not inject negative sequence current into the network unless it is necessary. The feed-forward compensation signals are summed with the reference currents provided by the external control and limited by the ReferenceLimiter control function.

Example 1—Function Description

(15) The negative-sequence current (I.sup.−) is computed according to Equation 1:

(16) $\begin{array}{cc}{I}_{\mathrm{FFW}}^{-}=-\frac{{\stackrel{\_}{U}}_{\mathrm{Bus}}^{-}}{{\stackrel{\_}{U}}_C^{{+}^{\prime }}-j{x}_C.Math.{\stackrel{\_}{I}}_C^{{+}^{\prime }}}{\stackrel{\_}{I}}_C^{{+}^{\prime }}.Math.K& \mathrm{Equation}1\end{array}$
where: FFW stands for Feed Forward j is a complex operator=square root of −1 Ū.sub.Bus.sup.− is the negative-sequence voltage at the converter bus, i.e. the secondary side of the transformer (at terminal A-B-C in FIG. 1). x.sub.C is the converter phase reactance in power units (p.u.) Ū.sub.C.sup.+′ is the complex conjugate of the positive sequence voltage across the legs 2.

(17) Please note that Ū.sub.C.sup.+ is computed outside the FeedForward control function by subtracting the voltage drop across the phase reactor from the positive sequence voltage at the converter bus computed by the PLL: according to: Ū.sub.C.sup.+=Ū.sub.Bus.sup.+−jx.sub.C.Math.Ī.sup.+ Ī.sub.C.sup.+′ is the complex conjugate of the positive-sequence current flowing in the delta connection. K is a control parameter which sets the amount of negative-sequence current used to balance the power. K can vary between 0 and 1, when K=1 the compensation is fulfilled by the negative-sequence current only. When K=0 the compensation is made only by the zero-sequence current and when 0<K<1 both negative and zero sequence currents are used.

(18) The zero sequence current is computed according to Equation 2:

(19) $\begin{array}{cc}{I}_{\mathrm{FF}}^0=\frac{\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}.Math.e^{j{\phi }_U^{-}}}{{\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}\right)}^2-1}\stackrel{\_}{U}-\frac{1}{{\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}\right)}^2-1}{\stackrel{\_}{U}}^{\prime }\mathrm{where}\text{:}\stackrel{\_}{U}=-\frac{{\stackrel{\_}{U}}_C^{-}}{{\stackrel{\_}{U}}_C^{+}}.Math.{\stackrel{\_}{I}}_C^{{+}^{\prime }}-\frac{{\stackrel{\_}{U}}_C^{{+}^{\prime }}}{{\stackrel{\_}{U}}_C^{+}}.Math.{\stackrel{\_}{I}}_C^{-}& \mathrm{Equation}2\end{array}$ φ is the phase angle relative to the reference angle in the control system provided by the Phase Lock Loop (PLL) control.

(20) The feed-forward currents are then summed with the reference currents, which are the outputs of the ReferenceLimiter control function.

(21) Matlab Code Description:

(22) The Matlab code starts with the calculation of the parameter K, which is calculated according to Equation 3.
K=max(K.sub.2,(1−K.sub.I0I2))  Equation 3
Where: K.sub.2 is an input of the control function. Since in normal operation K.sub.I0I2=1, it sets the amount of negative-sequence current to balance the power during normal or small unbalance operation. K.sub.I0I2 is an input of the control function and it is related to the controllability of the power unbalance through the zero-sequence current. When this parameter goes to zero it is not possible to use zero-sequence current, the overall parameter K.sub.I0I2 goes to one and thus only the negative-sequence current is fed forward.

(23) The parameter K.sub.I0I2 is now further explained. The system controllability is related to the ratio between negative- and positive-sequence voltages across the phase leg 2. The same method is used in the FeedForward control function in order to set the amount of negative-sequence current used to balance the power among the phases.

(24) The Matlab code starts by computing:

(25) $a_{10}=\{\begin{array}{cc}1-\frac{{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}^2}{{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}^2}& \mathrm{if}.Math.{\stackrel{\_}{U}}_C^{+}.Math.>0.1\\ 0& \mathrm{else}\end{array}$

(26) When a.sub.10 approaches zero, the dc voltage is not controllable by the zero-sequence current. In order to avoid sudden fluctuations of the control parameter, a limit is applied, and then the resulting signal is processed by a low-pass filter.

(27) Starting from a.sub.10, the parameter K.sub.I0 is computed according to the following equation, whose coefficients are hard-coded in the Matlab file.

(28) $K_{I0}=\{\begin{array}{cc}0& \mathrm{if}{a}_{10}\le 0.6\\ \frac{a_{10}-0.6}{0.3}& \mathrm{if}0.6<V\le 0.9\\ 1& \mathrm{if}{a}_{10}>0.9\end{array}$

(29) The signal K.sub.I0 is then filtered, the output is K.sub.I0I2 (below also called K.sub.I0F).

(30) $\stackrel{K_{I0}}{.Math.}\frac{1}{1+s\tau }\stackrel{K_{10F}}{.Math.}$
Where:

(31) $\tau =\frac{T_S\left(1-k\right)}{k}\approx 5\mathrm{ms}$
based on a sampling time T.sub.S=100 μs (50 Hz system) and a hard-coded value of k=0.02.

(32) The parameter K.sub.I0I2 is thus used to select the dc voltage controller.

(33) Once the parameter K is known it is possible to compute the negative-sequence current according to Equation 4

(34) $\begin{array}{cc}{\stackrel{\_}{I}}_{\mathrm{FFL}}^{-}=\{\begin{array}{cc}-\frac{{\stackrel{\_}{U}}_{\mathrm{Bus}}^{-}}{{\stackrel{\_}{U}}_C^{{+}^{\prime }}-j{x}_C.Math.{\stackrel{\_}{I}}_C^{{}^{\prime }}}{\stackrel{\_}{I}}_C^{{+}^{\prime }}.Math.K.Math.+{\stackrel{\_}{I}}_C^{-}.Math.K_{I0I2}& \mathrm{if}.Math.{\stackrel{\_}{U}}_C^{{+}^{\prime }}-j{x}_C.Math.{\stackrel{\_}{I}}_C^{{+}^{\prime }}.Math.>0.01\\ 0& \mathrm{else}\end{array}& \mathrm{Equation}4\end{array}$
where: Ī.sub.C.sup.− is the negative-sequence current reference provided by the ReferenceLimiter control function.

(35) Once the negative-sequence current is known, it is possible to compute the negative-sequence voltage across the legs 2:
Ū.sub.C.sup.−=Ū.sub.Bus.sup.−−jx.sub.C.Math.Ī.sub.FFL.sup.−  Equation 5

(36) If the positive-sequence voltage across the legs 2 (also called the valve) is greater than 0.01 p.u. it is possible to compute the zero-sequence current according to Equation 2. Before that it is necessary to check come parameters in order not to divide by zero:

(37) $\begin{array}{cc}{I}_{\mathrm{temp}}^0=\{\begin{array}{cc}\frac{1}{{\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}\right)}^2-1}\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}.Math.e^{j{\phi }_U^{-}}\stackrel{\_}{U}-{\stackrel{\_}{U}}^{\prime }\right)& \mathrm{if}{\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}\right)}^2<0.8\\ \frac{1}{0.8-1}\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}.Math.e^{j{\phi }_U^{-}}\stackrel{\_}{U}-{\stackrel{\_}{U}}^{\prime }\right)& \mathrm{if}{\left(\frac{.Math.{\stackrel{\_}{U}}_C^{-}.Math.}{.Math.{\stackrel{\_}{U}}_C^{+}.Math.}\right)}^2\ge 0.8\end{array}& \mathrm{Equation}6\end{array}$

(38) Besides, a check on the value of the parameter K in order to avoid to use zero-sequence when not needed.

(39) $\begin{array}{cc}{I}_{\mathrm{FF}}^0=\{\begin{array}{cc}{I}_{\mathrm{temp}}^0& \mathrm{if}K<0.98\\ 0& \mathrm{if}K\ge 0.98\end{array}& \mathrm{Equation}7\end{array}$

(40) Then, the output signals are generated:
Ī.sub.S.sup.+=Ī.sub.C.sup.+
Ī.sub.S.sup.−=Ī.sub.FFL.sup.−
Ī.sub.S.sup.0=Ī.sub.FF.sup.0  Equation 8
Input Signals

(41) TABLE-US-00001 Name Unit Symbol Comment uPosC p.u. Ū.sub.C.sup.+ Positive-sequence voltage vector across the valve uNeg p.u. Ū.sub.Bus.sup.− Negative-sequence voltage vector at the converter bus iPos p.u. Ī.sub.C.sup.+ Positive-sequence current reference vector iNeg p.u. Ī.sub.C.sup.− Negative-sequence current reference vector iZero p.u. Ī.sup.0 Zero-sequence current reference vector xc p.u. x.sub.C Converter phase reactance K2 K.sub.2 iNeg/iZero ratio in normal operation Ts ms T.sub.s Process sampling time, signal not used in the function FLICKER Logical Flicker control active, signal not used in the function KI0I2 K.sub.I0I2 If ‘1’ .fwdarw. power balanced through zero- sequence current. If ‘0’ .fwdarw. power balanced through negative- sequence current.
Output Signals

(42) TABLE-US-00002 Name Unit Symbol Comment iPosS p.u. Ī.sub.S.sup.+ Total positive-sequence current reference vector iNegS p.u. Ī.sub.S.sup.− Total negative-sequence current reference vector iZeroS p.u. Ī.sub.S.sup.0 Total zero-sequence current vector iNegFF .sup.1 p.u. Feed-forward negative-sequence current vector I0FF .sup.1 p.u. Feed-forward zero-sequence current vector Kmax .sup.1 K iNeg/iZero ratio KI2 .sup.1 K.sub.I2 Controllability of dc voltage unbalance means of zero-sequence current .sup.1 Used only for debugging purposes.

Example 2

(43) The Matlab function Test_FeedForward.m is provided to test the FeedForward.m function. In order to run Test_FeedForward.m both the CRC_FeedForward.m and FeedForward.m Matlab functions are needed.

(44) The function simulates the following sequence: Step the positive-sequence voltage to 1 p.u. @ t=20 ms Simulate an event @ t=150 ms:

(45) Case 0. Balanced operation. The positive-sequence voltage is constant and does not change during the simulation

(46) Case 1. Unbalanced operation due to mix of positive- and negative-sequence voltages.

(47) Case 2. Unbalanced operation due to mix of positive- and negative-sequence voltages, this case represents a bolted phase to phase fault at the primary side of a Yd transformer.

(48) Case 3. Unbalanced operation. The negative-sequence voltage increases from zero to 0.4 p.u., and at the same time the positive-sequence voltage decreases from one to 0.6 p.u. The event is cleared @ t=300 ms

(49) The positive-sequence current has been set to 0.2 p.u. during all the simulation and the sampling time is 100 μs.

Example 3—Balanced Operation

(50) During balanced operation, the feed-forward is disabled, thus both the negative- and zero-sequence currents are zero. The phase to phase voltages are balanced at 120° angle to each other. For the DC-voltages, the signals are constant except for the instant in which the system starts to operate.

Example 4—Unbalanced Operation

(51) The unbalance operation is caused by the presence of positive- and negative-sequence voltages between t=150 ms and t=300 ms. In this period of time, zero-sequence current is generated in order to keep the DC-voltages constant. The negative-sequence current in this operating condition is zero, why only zero sequence current is used. The filtered DC-voltages are constant during the simulation. They change only when disturbances occur, i.e. when the control starts to operate, when the fault occurs and when the fault is cleared.

Example 5—Bolted Two-Phase Fault

(52) In this case the behaviour of the control function is almost the same as in example 4. The difference is that now the amount of negative-sequence voltage is not equal to zero. Moreover, at about t=0.175 ms, the control parameter becomes one, and thus the compensation is fulfilled by the negative-sequence only.

Example 6—Ramp Response

(53) In this test the positive-sequence voltage is decreased to 0.6 p.u. while the negative-sequence voltage is increased to 0.4 p.u. The aim of this test is to check that the zero- and negative-sequence currents increase together with the unbalance of the system. Moreover, it is possible to test the computation of the parameter controls K.sub.I2 and K. Until t=0.23 ms the negative-sequence voltage is not that high and the zero-sequence current is enough to balance the power. Starting from t=0.23 ms the parameter steps to zero and both negative- and zero-sequence currents are used to compensate the power among the phases.

Example 7

(54) FIG. 4 shows the maximum phase leg current (iV max) in the power converter 1 for different magnitudes of a voltage dip simulating a 1-phase fault condition in the network.

(55) Maximum converter phase leg current magnitude when the positive-sequence current output of the converter 1 is 1.0 p.u. for 1-phase to ground fault in the feeding network. The x-axis is the voltage dip of the faulty phase.

(56) “Exponential” dashed curve: Maximum phase leg current when only zero-sequence current (I.sup.o) is used.

(57) “Proportional” dashed/dotted curve: Maximum phase leg current when only negative-sequence current (I.sup.−) is used.

(58) Bottom, solid curve: Maximum phase leg current with compound current; comprising 31% zero sequence current and 69% negative sequence current.

(59) As is evident from FIG. 4, the compound current results in a substantial and surprising reduction in phase leg current, even for very high voltage dips. Regardless of the magnitude of the voltage dip, the compound current always results in the lowest phase leg current.

(60) Below follows another aspect of the present invention.

(61) According to an aspect of the present invention, there is provided a control apparatus (10) for controlling a chain-link power converter (1), said converter comprising three phase legs (2), each of which phase legs comprising a plurality of series-connected converter cells (3), each of which cells comprising a DC capacitor, the phase legs (2) being connected in a delta configuration. The control apparatus comprises: means (11) for detecting (101) an unsymmetrical voltage condition at a terminal of the converter (1); means (11) for determining (102) a ratio between a zero sequence and a negative sequence component of a compound current to be injected into the converter (1), based on the detected (101) unsymmetrical voltage condition; means (11) for calculating (103) the compound current comprising the zero sequence component and the negative sequence component in accordance with the determined (102) ratio; and means (11) for injecting (104) the compound current into the converter (1) to control the converter in view of the detected (101) unsymmetrical voltage condition.

(62) The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.