Solid-state imaging element and manufacturing method for solid-state imaging element

Abstract

Provided are a solid-state imaging element, which suppresses occurrence of a dark current and a white spot and even suppresses occurrence of a residual image, and a manufacturing method for the solid-state imaging element. A solid-state imaging element (1) is provided with: a gate electrode (4) above a substrate (2); a charge storage region (5) formed at a position inside the substrate (2) and apart from a top surface (2a) of the substrate (2); a read region (6) formed at a position inside the substrate (2) and on the opposite side to the charge storage region (5) with the gate electrode (4) interposed therebetween; a channel region (7, 8) formed inside the substrate (2) and immediately below the gate electrode (4); and a shield region (9) and an intermediate region (10) formed inside the substrate (2) and between the top surface (2a) of the substrate (2) and the charge storage region (5). The intermediate region (10) is formed at a position inside the substrate (2) and between the channel region (7, 8) and the shield region (9), and is in contact with each of the channel region (7, 8) and the shield region (9), and a concentration of first conductive type impurities in the intermediate region (10) is lower than a concentration of the first conductive type impurities in the shield region (9).

Claims

1. A solid-state imaging element, comprising: a substrate including a semiconductor of a first conductive type; a gate insulating film on a top surface of the substrate; a gate electrode on the gate insulating film; a side wall on a side surface of the gate electrode; a charge storage region including a semiconductor of a second conductive type different from the first conductive type inside the substrate and apart from the top surface of the substrate; a read region including the second conductive type semiconductor inside the substrate and on an opposite side to the charge storage region with the gate electrode interposed therebetween; a channel region including the first conductive type semiconductor inside the substrate and immediately below the gate electrode; a shield region including the first conductive type semiconductor inside the substrate and between the top surface of the substrate and the charge storage region; and an intermediate region including the first conductive type semiconductor inside the substrate and between the top surface of the substrate and the charge storage region, wherein the charge storage region extends to immediately below the gate electrode inside the substrate and is in contact with a lower end of the channel region, the intermediate region is inside the substrate and between the channel region and the shield region and is immediately below the side wall, and is in contact with each of the channel region and the shield region, and a concentration of impurities of the first conductive type in the intermediate region is lower than a concentration of the impurities of the first conductive type in the shield region, the channel region includes a first channel region that is in contact with the charge storage region, and a second channel region that is in contact with the read region and the first channel region, and the second channel region includes a portion protruding toward the charge storage region with respect to an end of the first channel region on a side of the read region, an upper surface of the portion is directly in contact with a lower surface of the first channel region, and the portion and the charge storage region are separate from each other.

2. The solid-state imaging element according to claim 1, wherein the concentration of the first conductive type impurities in the intermediate region is higher than a concentration of the first conductive type impurities in the channel region.

3. The solid-state imaging element according to claim 2, wherein the concentration of the first conductive type impurities in the shield region is not lower than 1×10.sup.18 cm.sup.−3 and not higher than 1×10.sup.19 cm.sup.−3, the concentration of the first conductive type impurities in the intermediate region is not lower than 3×10.sup.17 cm.sup.−3 and not higher than 3×10.sup.18 cm−3, and the concentration of the first conductive type impurities in the channel region is not lower than 3×10.sup.16 cm.sup.−3 and not higher than 3×10.sup.17 cm−3.

4. The solid-state imaging element according to claim 1, wherein a portion of the charge storage region, which extends to immediately below the gate electrode, has a length not smaller than 50 nm and not larger than 250 nm.

5. The solid-state imaging element according to claim 1, wherein an end of the first channel region on a side closest to the read region protrudes toward the read region more than an end of the charge storage region on a side closest to the read region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A to 1C are sectional views showing a structural example and potential examples of a solid-state imaging element according to an embodiment of the present invention.

(2) FIG. 2 is a sectional view showing an example of a manufacturing method for a solid-state imaging element according to the embodiment of the present invention.

(3) FIG. 3 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(4) FIG. 4 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(5) FIG. 5 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(6) FIG. 6 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(7) FIG. 7 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(8) FIG. 8 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(9) FIG. 9 is a sectional view showing an example of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(10) FIGS. 10A to 10C are diagrams showing a structure and potentials of the conventional solid-state imaging element.

DESCRIPTION OF EMBODIMENT

(11) <Structural Example of Solid-State Imaging Element>

(12) A structural example of a solid-state imaging element according to an embodiment of the present invention will be described with reference to the drawings. However, for embodying the description, a case will be shown hereinafter where a solid-state imaging element as a CMOS image sensor is provided with an n-type charge storage region in a p-type substrate, and the charge storage region stores electrons. It is to be noted that the “p-type substrate” means a substrate where a portion to be formed with an element structure is the p type, and it is not restricted to a substrate being entirely the p type, but it naturally includes a substrate with a well being the p type (e.g., a substrate which is formed with a p-type well by injecting the p-type impurities into a substrate being entirely the n type). However, it is assumed that in each drawing to be referenced in the following description, the substrate is illustrated as if being entirely the p type.

(13) Further, silicon can be used as a material for the substrate. In this case, boron or the like can be used as the p-type impurities. Further, in this case, phosphorus or arsenic can be used as the n-type impurities. Moreover, these impurities can be injected into the substrate by using a method such as ion plantation. It is to be noted that for embodying the description, a case where the substrate is composed of silicon will be illustrated hereinafter.

(14) FIGS. 1A to 1C are sectional views showing a structural example and potential examples of the solid-state imaging element according to the embodiment of the present invention. FIG. 1A is a view showing a cross section of the solid-state imaging element, and a broken arrow in the drawing indicates an electron channel (read channel) at the time of reading electrons stored in a charge storage region 5 into a read region 6 (at the time of read). FIG. 1B shows a potential on the read channel at the time of storing the electrons in the charge storage region 5 (at the time of storage). FIG. 1C shows a potential on the read channel at the time of read.

(15) As shown in FIG. 1A, a solid-state imaging element 1 is provided with: a p-type substrate 2; a gate insulating film 3 formed on a top surface 2a of the substrate 2; a gate electrode 4 formed on the gate insulating film 3; the n-type charge storage region 5 formed at a position inside the substrate 2 and apart from the top surface 2a of the substrate 2; the n-type read region 6 formed at a position inside the substrate 2 and on the opposite side to the charge storage region 5 with the gate electrode 4 interposed therebetween; a p-type first channel region 7 and a p-type second channel region 8 formed at a position inside the substrate 2 and immediately below the gate electrode 4; a p-type shield region 9 formed at a position inside the substrate 2 and between the top surface 2a of the substrate 2 and the charge storage region 5; a p-type intermediate region 10 formed at a position inside the substrate 2 and between the top surface 2a of the substrate 2 and the charge storage region 5; side walls 11, 12 formed on a side surface of the gate electrode 4; and an element separation part 13 formed by STI (Shallow Trench Isolation) or the like around an element region of the substrate 2 which is formed with each of the above parts 3 to 12.

(16) The gate insulating film 3 is made up of silicon oxide, for example, and the gate electrode 4 is made up of polysilicon, for example. Further, the gate electrode 4 has a film thickness not smaller than 100 nm and not larger than 250 nm, for example.

(17) A concentration of the n-type impurities in the charge storage region 5 is not lower than 1×10.sup.17 cm.sup.−3 and not higher than 1×10.sup.18 cm.sup.−3, for example, and is lower than a concentration of the n-type impurities in the read region 6. Further, the charge storage region 5 extends to a place immediately below the gate electrode 4 inside the substrate 2, and is in contact with a lower end of the first channel region 7. The existence of this portion extending to the place immediately below the gate electrode 4 leads to formation of a read channel for reading electrons from the charge storage region 5 into the first channel region 7 via this portion. This portion of the charge storage region 5, which extends to the place immediately below the gate electrode 4, has a length not smaller than 50 nm and not larger than 250 nm. It is more preferably not smaller than 100 nm and not larger than 200 nm.

(18) When the portion of the charge storage region 5 which extends to the place immediately below the gate electrode 4 has the length being the above value, the charge storage region 5 can be formed by injecting the n-type impurities into the top surface 2a of the substrate 2 after formation of the gate electrode 4 (a detailed description will be given in an example of a manufacturing method to be described later). That is, it becomes possible to eliminate the need for forming the charge storage region 5 by injecting the n-type impurities into the top surface 2a of the substrate 2 prior to formation of the gate electrode 4. Hence it becomes possible to suppress variation in relative position of the charge storage region 5 with respect to the gate electrode 4 in each pixel inside the solid-state imaging element 1.

(19) The first channel region 7 is formed at a position inside the substrate 2 and in contact with the charge storage region 5. Further, the second channel region 8 is formed at a position inside the substrate 2 and in contact with the read region 6 and the first channel region 7. Moreover, the second channel region 8 is formed expanding to a position more apart from the top surface 2a of the substrate 2 than the first channel region 7. In such a manner, inside the substrate 2, when the second channel region 8 on the read region 6 side is formed so as to be deeper than the first channel region 7 on the charge storage region 5 side, it becomes possible to suppress punch-through between the charge storage region 5 and the read region 6.

(20) The intermediate region 10 is formed at a position inside the substrate 2 and between the first channel region 7 and the shield region 9, and is in contact with each of the first channel region 7 and the shield region 9. Further, the intermediate region 10 is formed at a position inside the substrate 2 and immediately below the side wall 11 formed on a side surface of the gate electrode 4 on the charge storage region 5 side. It is to be noted that the side walls 11, 12 are made up of silicon oxide or silicon nitride, or one formed by laminating these, for example. Moreover, the side wall 12 is one formed on a side surface of the gate electrode 4 on the read region 6 side.

(21) A concentration of p-type impurities in the intermediate region 10 is lower than a concentration of the p-type impurities in the shield region 9, and is higher than a concentration of the p-type impurities in the first channel region 7 and the second channel region 8. Specifically, the concentration of the p-type impurities in the intermediate region 10 is not lower than 3×10.sup.17 cm.sup.−3 and not higher than 3×10.sup.18 cm.sup.−3, the concentration of the p-type impurities in the shield region 9 is not lower than 1×10.sup.18 cm.sup.−3 and not higher than 1×10.sup.19 cm.sup.−3, and the concentration of the p-type impurities in the first channel region 7 and the second channel region 8 is not lower than 3×10.sup.16 cm.sup.−3 and not higher than 3×10.sup.17 cm.sup.−3.

(22) In the solid-state imaging element 1, in order to suppress supply of electrons which cause a dark current and a white spot from interface states formed on the top surface 2a of the substrate 2 to the charge storage region 5, the concentration of the p-type impurities in the shield region 9 needs to be made sufficiently high as the above value. Meanwhile, in order to efficiently read the electrons at the time of read, the concentration of the p-type impurities in the first channel region 7 and the second channel region 8 needs to be made sufficiently low as the above value. For this reason, as described with reference to FIGS. 10A to 10C, when it is structured that the shield region 108 and the first channel region 106 are adjacent with each other, the potential barrier B is formed in the first channel region 106 due to an influence by the shield region 108, to cause occurrence of a residual image in image data.

(23) Therefore, in the solid-state imaging element 1 according to the embodiment of the present invention, the intermediate region 10 where the concentration of the p-type impurities are lower than that in the shield region 9 is formed between the shield region 9 and the first channel region 7. Hence it becomes possible to reduce the potential barrier B (cf. FIGS. 10A to 10C) in the first channel region 7 as shown in FIGS. 1B and 1C. In particular, by setting the concentration of the p-type impurities in the intermediate region 10 to the above value, it becomes possible to effectively reduce the potential barrier B (cf. FIGS. 10A to 10C) in the first channel region 7.

(24) From the above, in the solid-state imaging element 1 according to the embodiment of the present invention, it becomes possible to reduce the potential barrier B (cf. FIG. 10) in the first channel region 7 while providing the shield region 9 for suppressing a dark current and a white spot. Hence it becomes possible to suppress occurrence of a dark current and a white spot and even suppress occurrence of a residual image.

(25) Moreover, it is preferable to make the concentration of the p-type impurities in the intermediate region 10 higher than the concentration of the p-type impurities in the first channel region 7 and the second channel region 8 as described above. While a detailed description will be given in an example of the manufacturing method to be described later, formation of the gate electrode 4 and the gate insulating film 3 requires etching, and when the etching is performed, the top surface 2a of the substrate 2 except for the place immediately below the gate electrode 4 is damaged, thereby to increase a density of the interface states. That is, as compared to the top surface 2a of the substrate 2 which is immediately below the gate electrode 4 (immediately above the first channel region 7 and the second channel region 8), the other top surface 2a of the substrate 2 (immediately above the intermediate region 10 and the charge storage region 5) becomes easier to supply the electrons that cause a dark current and a white spot. Therefore, by making the concentration of the p-type impurities in the intermediate region 10 higher than the concentration of the p-type impurities in the first channel region 7 and the second channel region 8, it becomes possible to suppress supply of the electrons that cause a dark current and a white spot. In particular, by setting the concentration of the p-type impurities in the intermediate region 10 to the above value, it becomes possible to effectively suppress supply of the electrons that cause a dark current and a white spot.

(26) It should be noted that, although not particularly shown in FIG. 1A, the top surface 2a of the substrate 2 which is immediately above the charge storage region 5 may be provided with an optical member such as a color filter or a microlens via an interlayer insulating film made up of silicon oxide, for example. That is, the solid-state imaging element 1 may be a front-surface irradiation type CMOS image sensor. Alternatively, as opposed to this, the opposite-side surface of the substrate 2 to the top surface 2a may be provided with the optical member such as the color filter or the microlens via the interlayer insulating film made up of silicon oxide, for example. That is, the solid-state imaging element 1 may be a rear-surface irradiation type CMOS image sensor. In either CMOS image sensor, light having passed through the optical member is subjected to photoelectric conversion by a photodiode made up of the charge storage region 5 and the substrate 2, and electrons generated thereby are stored into the charge storage region 5.

(27) <Example of Manufacturing Method for Solid-State Imaging Element>

(28) Next, the manufacturing method for the solid-state imaging element 1 shown in FIG. 1A will be described with reference to FIGS. 2 to 9. FIGS. 2 to 9 are sectional views showing examples of the manufacturing method for the solid-state imaging element according to the embodiment of the present invention.

(29) First, as shown in FIG. 2, a resist R1 is formed by photolithography or the like on the top surface 2a of the substrate 2 formed with the element separation part 13. This resist R1 is open immediately above a position to be eventually formed with the read region 6 and the second channel region 8 (cf. FIGS. 1A to 1C). Then, the p-type impurities are injected with this resist R1 used as a mask, to form the second channel region 8. Thereafter, this resist R1 is removed.

(30) Next, as shown in FIG. 3, a resist R2 is formed by photolithography or the like with respect to the top surface 2a of the substrate 2. This resist R2 is open immediately above a position to be eventually formed with the first channel region 7, the shield region 9 and the intermediate region 10 (cf. FIGS. 1A to 1C). Then, the p-type impurities are injected with this resist R2 used as a mask, to form the first channel region 7. Thereafter, this resist R2 is removed.

(31) Next, as shown in FIG. 4, the gate electrode 4 is formed via the gate insulating film 3 at a position immediately above a position which is on the top surface 2a of the substrate 2 and is to be eventually formed with the first channel region 7 and the second channel region 8 (cf. FIGS. 1A to 1C). For example, at this time, the top surface 2a of the substrate 2 is thermally oxidized to form a silicon oxide film, and a polysilicon film is further formed thereabove by CVD (Chemical Vapor Deposition) or the like. Then, a resist is formed on a top surface of a portion to eventually become the gate electrode 4 (cf. FIGS. 1A to 1C) by photolithography or the like, which is further dry-etched, thereby selectively removing the polysilicon film and the silicon oxide film, to form the gate insulating film 3 and the gate electrode 4. Thereafter, the resist is removed.

(32) Next, as shown in FIG. 5, a resist R3 is formed by photolithography or the like with respect to the top surface 2a of the substrate 2 and the gate electrode 4. This resist R3 is open immediately above a position to be eventually formed with the charge storage region 5 (cf. FIGS. 1A to 1C). Then, the n-type impurities are injected with this resist R3 and the gate electrode 4 used as a mask, to form the charge storage region 5.

(33) However, at this time, the n-type impurities are injected from an injection direction which is inclined from a vertical direction to the top surface 2a of the substrate 2 so as to be away from the gate electrode 4 by just a predetermined angle (e.g., not smaller than 3 degrees and not larger than 10 degrees). Thereby, the charge storage region 5, which extends to the place immediately below the gate electrode 4 and is in contact with the lower end of the first channel region 7, is formed with respect to the gate electrode 4 in a self-matching manner. Thereafter, the resist R3 is removed.

(34) After injection of the n-type impurities, the charge storage region 5 expands around itself (the n-type impurities are diffused) by thermal treatment performed at arbitrary timing, and a length of the portion extending to the place immediately below the gate electrode 4 becomes a length of not smaller than 50 nm and not larger than 250 nm. It should be noted that the length of the portion of the charge storage region 5 which extends to the place immediately below the gate electrode 4 at a point in time immediately after injection of the n-type impurities is not smaller than 5 nm and not larger than 50 nm, for example.

(35) Next, as shown in FIG. 6, a resist R4 is formed by photolithography or the like with respect to the top surface 2a of the substrate 2 and the gate electrode 4. This resist R4 is open immediately above a position to be eventually formed with the read region 6 (cf. FIGS. 1A to 1C). The n-type impurities are injected with this resist R4 and the gate electrode 4 used as a mask, to form the read region 6 with respect to the gate electrode 4 in a self-matching manner. Thereafter, the resist R4 is removed.

(36) Next, as shown in FIG. 7, a resist R5 is formed by photolithography or the like with respect to the top surface 2a of the substrate 2 and the gate electrode 4. This resist R5 is open immediately above a position to be eventually formed with the shield region 9 and the intermediate region 10 (cf. FIGS. 1A to 1C). The p-type impurities are injected with this resist R5 and the gate electrode 4 used as a mask, to form the intermediate region 10 with respect to the gate electrode 4 in a self-matching manner. Thereafter, the resist R5 is removed.

(37) Next, as shown in FIG. 8, the side walls 11, 12 are formed with respect to the side surface of the gate electrode 4. At this time, for example, a film made up of silicon oxide or silicon nitride, or one formed by laminating these, is formed by CVD or the like with respect to the entire surface of the top surface 2a of the substrate 2. The entire surface of the film is dry-etched to selectively leave the film at an etching-resistant step portion formed by the top surface 2a of the substrate 2 and the side surface of the gate electrode 4, thereby forming each of the side walls 11, 12. That is, the side walls 11, 12 are formed with respect to the gate electrode 4 in a self-matching manner.

(38) Next, as shown in FIG. 9, a resist R6 is formed by photolithography or the like with respect to the top surface 2a of the substrate 2 and the gate electrode 4. This resist R6 is open immediately above a position to be eventually formed with the shield region 9 (cf. FIGS. 1A to 1C). The p-type impurities are injected with this resist R6, the gate electrode 4 and the side wall 11 used as a mask, to form the shield region 9 with respect to the side wall 11 in a self-matching manner. Thereafter, the resist R6 is removed.

(39) In the above manufacturing method for the solid-state imaging element 1, it becomes possible to form the respective regions 5, 6, 9, 10 inside the substrate 2 with respect to the gate electrode 4 in a self-matching manner. Hence it becomes possible to suppress relative displacement, so as to accurately manufacture the solid-state imaging element 1 which can suppress occurrence of a dark current and a white spot and can even suppress occurrence of a residual image.

(40) Especially, by forming the intermediate region 10 with respect to the gate electrode 4 in a self-matching manner as shown in FIG. 7 and also forming the shield region 9 with respect to the side wall 11 in a self-matching manner as shown in FIG. 9, it becomes possible to suppress variation in relative positional relations of the intermediate region 10 and the shield region 9 with respect to the first channel region 7. Therefore, it becomes possible to accurately reduce the potential barrier B (cf. FIGS. 10A to 10C) in the first channel region 7, so as to prevent a residual image from occurring as varying in each pixel inside the solid-state imaging element 1.

(41) In addition, although the case has been illustrated in FIGS. 2 and 3 where the second channel region 8 is formed prior to the first channel region 7, the first channel region 7 may be formed prior to the second channel region 8. Further, although the case has been illustrated in FIGS. 4 and 5 where the charge storage region 5 is formed prior to the read region 6, the read region 6 may be formed prior to the charge storage region 5.

(42) <Modification, Etc.>

(43) The solid-state imaging element 1, structured to form the first channel region 7 and the second channel region 8 at the position inside the substrate 2 and immediately below the gate electrode 4, and the manufacturing method for the solid-state imaging element 1 have been illustrated in FIGS. 1A to 9, but it may be structured to form only one channel region at the position inside the substrate 2 and immediately below the gate electrode 4.

(44) Further, the solid-state imaging element 1 where electrons are stored in the n-type charge storage region 5 has been illustrated in FIGS. 1A to 9, but the p-type and the n-type of the substrate 2 and the respective regions 5 to 10 inside the substrate 2 may be reversed. In this case, the solid-state imaging element 1 becomes one to store holes in the p-type charge storage region 5.

(45) However, even in this case, it is assumed that the concentration of the n-type impurities in the intermediate region 10 is lower than the concentration of the n-type impurities of the conductive type in the shield region 9. Further, it is preferably assumed that the concentration of the n-type impurities in the intermediate region 10 is higher than the concentration of the n-type impurities in the first channel region 7 and the second channel region 8.

(46) Specifically, it is preferable that the concentration of the n-type impurities in the intermediate region 10 is not lower than 3×10.sup.17 cm.sup.−3 and not higher than 3×10.sup.18 cm.sup.−3, the concentration of the n-type impurities in the shield region 9 is not lower than 1×10.sup.18 cm.sup.−3 and not higher than 1×10.sup.19 cm.sup.−3, and the concentration of the n-type impurities in the first channel region 7 and the second channel region 8 is not lower than 3×10.sup.16 cm.sup.−3 and not higher than 3×10.sup.17 cm.sup.−3.

(47) As the description of the solid-state imaging element 1 and the manufacturing method for the solid-state imaging element 1 according to the embodiment of the present invention, the case of the solid-state imaging element 1 being the CMOS image sensor has been illustrated, but the present invention is not restricted to the CMOS image sensor, and it is also applicable to another solid-state imaging element such as a CCD image sensor.

INDUSTRIAL APPLICABILITY

(48) A solid-state imaging element and a method for manufacturing the solid-state imaging element according to the present invention can, for example, be used for a CMOS image sensor, a CCD image sensor and the like which are mounted in a variety of electronic equipment having an imaging function.

DESCRIPTION OF SYMBOLS

(49) 1 solid-state imaging element 2 substrate 2a top surface 3 gate insulating film 4 gate electrode 5 charge storage region 6 read region 7 first channel region 8 second channel region 9 shield region 10 intermediate region 11 side wall 12 side wall 13 element separation part