PoDL system with active dV/dt and dI/dt control

Abstract

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

Claims

1. A Power over Data Lines (PoDL) system, which enables power and differential data transmission over a single wire pair, comprising: a passive coupling network in Power Sourcing Equipment (PSE) coupled to the wire pair for coupling a DC power signal and differential data to the wire pair; a passive decoupling network in a Powered Device (PD) coupled to the wire pair for decoupling the DC power signal and differential data from the wire pair; a PD load powered by the DC power signal; and dV/dt limiting circuitry, separate from the passive coupling network and the passive decoupling network, comprising one or more active components, wherein the dV/dt limiting circuitry limits dV/dt in the power signal, the dV/dt limiting circuitry being configured to limit the dV/dt of the DC power signal at all currents drawn by the load.

2. The system of claim 1 wherein the dV/dt limiting circuitry comprises: a transistor in series with a power signal line in the PSE; and a control circuit in the PSE responsive to dV/dt on the power signal line, wherein the control circuit controls a conductivity of the transistors in response to the dV/dt such that the dV/dt is limited.

3. The system of claim 2 wherein the control circuit comprises a capacitor having a first terminal coupled to the power signal line and a second terminal coupled to a control terminal of the transistor.

4. The system of claim 3 further comprising a current source supplying current to the control terminal of the transistor, wherein the capacitor diverts current from the current source to limit the dV/dt.

5. The system of claim 1 wherein the PD includes a DC-DC converter for converting incoming PoDL voltage to a target voltage for the PD load, wherein the dV/dt limiting circuitry comprises: a duty cycle slew rate limiting circuit coupled to the DC-DC converter for limiting a slew rate of the duty cycle of the converter in response to changes in PD load current, thus reducing a dl/dt into the PD load, resulting in a reduced dV/dt in the power signal.

6. The system of claim 5 wherein the duty cycle slew rate limiting circuit comprises: a differentiator circuit that outputs a first signal proportional to dV/dt in the power signal; and a DC-DC converter controller circuit that receives a first feedback signal corresponding to an output voltage of the converter and regulates the output voltage to be a target voltage, wherein the first signal is provided to the converter controller to limit the dV/dt to a maximum value by limiting the slew rate of the duty cycle of the converter in response to changes in the PD load.

7. The system of claim 5 wherein the duty cycle slew rate limiting circuit comprises: a slew rate limited differential amplifier, wherein the slew rate limited differential amplifier outputs a control signal in the converter that controls the duty cycle.

8. The system of claim 7 comprises a second differential amplifier receiving a voltage corresponding to an output voltage of the converter and receiving a reference voltage, wherein an output of the second differential amplifier is coupled to an input of the slew rate limited differential amplifier.

9. The system of claim 8 wherein the slew rate limited differential amplifier comprises a capacitor coupled to its output, where the output is coupled to an input of the slew rate limited differential amplifier.

10. The system of claim 1 wherein the dV/dt limiting circuitry limits dI/dt into the PD load.

11. The system of claim 1 wherein the passive coupling network and the passive decoupling network comprises: inductors for passing the power signal but blocking the differential data; and capacitors for passing the differential data but blocking the power signal.

12. The system of claim 1 wherein the DC power signal is generated by a voltage source in the PSE.

13. The system of claim 1 wherein the differential data comprises Ethernet data.

14. The system of claim 1 wherein the dV/dt limiting circuitry comprises d.sup.2I/dt.sup.2 limiting circuitry in the PD that limits PD load current variations.

15. A Power over Data Lines (PoDL) system, which enables power and differential data transmission over a single wire pair, comprising: a passive coupling network in Power Sourcing Equipment (PSE) coupled to the wire pair for coupling a DC power signal and differential data to the wire pair; a passive decoupling network in a Powered Device (PD) coupled to the wire pair for decoupling the DC power signal and differential data from the wire pair; a PD load powered by the DC power signal; and d.sup.2I/dt.sup.2 limiting circuitry, separate from the passive coupling network and the passive decoupling network, comprising one or more active components, wherein the d.sup.2I/dt.sup.2 limiting circuitry limits dV/dt in the DC power signal, the d.sup.2I/dt.sup.2 limiting circuitry being configured to limit the dV/dt in the DC power signal at all currents drawn by the load.

16. The system of claim 15 wherein the PD includes a DC-DC converter for converting incoming PoDL voltage to a target voltage for the PD load, wherein the d.sup.2I/dt.sup.2 limiting circuitry comprises: a duty cycle slew rate limiting circuit coupled to the DC-DC converter for limiting a slew rate of the duty cycle of the converter in response to changes in PD load current, thus reducing a dI/dt into the PD load, resulting in a reduced dV/dt in the power signal.

17. The system of claim 16 wherein the duty cycle slew rate limiting circuit comprises: a differentiator circuit that outputs a first signal proportional to dV/dt in the power signal; and a DC-DC converter controller circuit that receives a first feedback signal corresponding to an output voltage of the converter and regulates the output voltage to be a target voltage, wherein the first signal is provided to the converter controller to limit the d.sup.2I/dt.sup.2 to a maximum value by limiting the slew rate of the duty cycle of the converter in response to changes in the PD load.

18. The system of claim 16 wherein the duty cycle slew rate limiting circuit comprises: a slew rate limited differential amplifier, wherein the slew rate limited differential amplifier outputs a control signal in the converter that controls the duty cycle.

19. The system of claim 18 wherein the slew rate limited differential amplifier comprises a capacitor coupled to its output, where the output is coupled to an input of the slew rate limited differential amplifier.

20. The system of claim 15 wherein the d.sup.2I/dt.sup.2 limiting circuitry limits dI/dt into the PD load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a conventional PoDL-enabled Ethernet system using a single wire pair for supplying power and data to the PD.

(2) FIG. 2 illustrates a technique, in accordance with one embodiment of the invention, for pre-conditioning the power signal in the PSE during start-up to remove dV/dt noise prior to reaching the coupling/decoupling network.

(3) FIG. 3A illustrates a technique, in accordance with another embodiment of the invention, for limiting dV/dt at the PD due to dI/dt by the PD load to lower noise in the power signal.

(4) FIG. 3B illustrates a differentiator circuit that may be used in the circuit of FIG. 3A.

(5) FIG. 4 illustrates another technique, in accordance with another embodiment of the invention, for limiting dV/dt at the PD due to dI/dt by the PD load to lower noise in the power signal.

(6) Elements that are the same or equivalent are labeled with the same numeral.

DETAILED DESCRIPTION

(7) FIG. 2 illustrates the power generating portion of a PSE 20 in a PoDL system. The PD (not shown) may be similar to the conventional PD 12 in FIG. 1, although the filter requirements in the PD's decoupling network of the PD are eased by the present invention. The differential data portion of the PoDL system is not relevant to the present invention and may be conventional.

(8) An analysis of the PHYs' terminal voltage response to a change in the PSE voltage dV.sub.PsE/dt can assume one of three forms depending on the circuit's damping ratio: under-damped, critically damped, or over-damped, but at steady state it can be shown that:

(9) $V_{\mathrm{PHY}}=\frac{d{V}_{\mathrm{PSE}}}{dt}\times \frac{50\Omega \times C_{\mathrm{PHY}}}{2},$
where the impedance of the PHY is assumed to be 2×50Ω, and C.sub.PHY is the capacitance of the PHY's DC blocking capacitors C1-C4.

(10) Hence a slew rate limitation on dV.sub.PSE/dt is required in order to constrain the magnitude of voltage perturbations at either PHY.

(11) For the PSE, various circuit topologies may be used to limit the dV.sub.PSE/dt as needed in order to ensure that the magnitude of the resulting voltage transients at the PHY terminals are limited.

(12) FIG. 2 illustrates circuit architecture in a PSE 20 where a low-side N-channel MOSFET M3 is enhanced with a pull-up current I1 by current source 22 only during start-up of the PSE 20, when variations in the power signal voltage occur. During start-up, the switch 24 is opened to allow the current I1 to pull-up the gate of the MOSFET M3 to ramp up its conductivity between ground and the bottom terminal of inductor L2. At start-up, the dV/dt at the drain of the MOSFET M3 is fairly large so current will be conducted by the capacitor C5 between the drain and the gate to reduce the percentage of the current from the current source 22 applied to the gate. This limits the turn on time of the MOSFET M3. As dV/dt is reduced (and the current into the capacitor C5 is reduced), the percentage of the current from the current source 22 applied to the gate is increased until the MOSFET M3 is completely turned on (i.e., V.sub.PSE− is approximately ground). Thus, capacitor C5 provides feedback from the drain of MOSFET M3 to the gate in order to limit dV/dt to less than approximately I(I1)/C5. This technique uses the well-known Miller effect for MOSFETs. The current source 22 or capacitor C5 can be selected to ramp up the conductivity of the MOSFET M3 at any desired rate to limit dV/dt. Limiting dV/dt preserves data integrity and eases the filtering requirements of the coupling/decoupling networks.

(13) At the end of the start-up ramp, the switch 24 remains open and the current I1 fully turns on the MOSFET M3 to cause it to operate in its linear region. The capacitor C5 then acts as an open circuit. The closing of the switch 24 is for discharging the gate to turn off the MOSFET M3 to terminate the power signal to the PD. The added components may be fabricated on the same chip as the PSE controller, since capacitor C5 can be small.

(14) Many other types of circuits may be used in place of the limiting circuit of FIG. 2 to limit the time rate of change of V.sub.PSE− or V.sub.PSE+ during start-up or during any other time.

(15) Further, if noise generated by the DC voltage source 13 is an issue, a voltage regulator may be included to smooth the voltage applied to the V.sub.PSE+ and V.sub.PSE− terminals.

(16) FIGS. 3A and 4 show circuits that limit dV/dt at the PD, caused by rapid changes in the PD load current during or after start-up.

(17) For a PD, the relationship between V.sub.PD (i.e., PD voltage after filtering by the decoupling network) and V.sub.PHY (i.e., voltage across the wire pair) is the same as for the V.sub.PSE and V.sub.PHY. Ignoring the effects of parasitic resistance, the steady state relationship between dV.sub.PD/dt and PD current I.sub.PD is:

(18) $\frac{d{V}_{\mathrm{PD}}}{dt}=-4L\times \frac{d^2{I}_{\mathrm{PD}}}{d{t}^2}$

(19) Hence, the second derivative of the PD current should be constrained in order to limit the magnitude of voltage transients seen at the PHYs' terminals.

(20) Circuit architectures that limit the time rate of change in PD current offer a means of limiting PHY voltage transients.

(21) FIG. 3A illustrates a circuit architecture where dV.sub.PD/dt in the PD 30 is limited. A PD load (not shown) is connected to the Vout terminals of a DC-DC converter. The converter converts the incoming PoDL voltage to a regulated target voltage (e.g., 5 volts) used by the PD load. Such a load may automatically go into or come out of a standby mode and quickly change its current. Such a rapid change in load current typically causes a rapid change in the PoDL voltage.

(22) In FIG. 3A, an input capacitor C.sub.IN partially smoothes the voltage across the V.sub.PD+ and V.sub.PD− lines. A differentiator circuit 32 detects the voltage across the V.sub.PD+ and V.sub.PD− lines and outputs a voltage proportional to dV/dt. A common differentiator circuit is shown in FIG. 3B. The values of R and C in the circuit of FIG. 3B are adjustable to obtain the desired ratio of Vout vs dV/dt.

(23) The output of the differentiator circuit 32 is differenced with respect to a fixed slew limit reference voltage (a threshold voltage) by a difference amplifier 34. The output of the amplifier 34 is fed into a negative input of a control amplifier 36 for a voltage-mode buck DC-DC converter, thus limiting the time rate of change of the converter's duty cycle so that the dV/dt of V.sub.PD) does not exceed the threshold.

(24) A fixed reference voltage REF is applied to the positive input of the control amplifier 36. The output voltage V.sub.OUT of the converter is applied to another negative input of the control amplifier 36.

(25) The analog output of the control amplifier 36 acts as a control signal for a pulse width modulator (PWM) 38. The PWM 38 may be conventional and may compare the control voltage to a sawtooth waveform. When the PWM 38 output is low, the NMOS transistor M1 turns off and the PMOS transistor M2 turns on to start a new charging cycle for the inductor L5. An output capacitor C.sub.OUT smoothes the output of the converter for the PD load. By limiting the change in duty cycle, such as when the PD load comes out of a standby mode to draw more current, there will be a smoother ramp-up of current into the load, at the expense of rapid output voltage regulation, as the converter tries to increase the charging time of the inductor L5. This smoother ramp-up of current dynamically reduces dV/dt across the V.sub.PD+ and V.sub.PD− lines so that the dV/dt of the V.sub.PD+ and V.sub.PD− lines does not exceed a threshold limit. This limits the dI/dt (and d.sup.2I.sub.PD/dt.sup.2) of the PD load current. Thus, changes in the PD load (e.g., going in or out of a standby mode) will have a limited effect on the dV/dt so that the filtering requirements for the decoupling components C3, C4, L3, and L4 are reduced.

(26) Many other types of DC-DC converters may be used instead of the buck type shown in FIG. 3A.

(27) As shown in FIG. 4, another approach to limiting d.sup.2I.sub.PD/dt.sup.2 involves directly limiting the slew rate of the DC-DC converter's control voltage in order to limit the time rate of change of the PWM duty cycle. Assuming that changes in V.sub.PD) are small due to changes in I.sub.PD), the relationship between d.sup.2I.sub.PD/dt.sup.2 and a buck DC-DC converter's duty cycle is approximately:

(28) $\frac{d^2{I}_{\mathrm{PD}}}{d{t}^2}=\frac{d\mathrm{DC}}{dt}\times \frac{V_{\mathrm{PD}}}{L5}$

(29) Hence, it can be seen that directly limiting the time rate of change of the converter's duty cycle may be sufficient for limiting the magnitude of voltage transients at the PHYs.

(30) FIG. 4 illustrates a voltage-mode buck converter where the loop amplifier's control voltage slew rate is limited by a slew rate limited amplifier 44 in order to limit the time rate of change of the PWM duty cycle, where the duty cycle is proportional to the control voltage. The output voltage V.sub.OUT is applied to the negative input of the difference amplifier 46, and a fixed reference voltage REF is applied to the positive input. The output of the difference amplifier 46 represents the deviation of V.sub.OUT from a target voltage. The slew rate limited amplifier 44 is a transconductance amplifier that feeds back its output to its negative input terminal, and a slew capacitor C.sub.SLEW determines the maximum rate of change at the output. The output supplies the control voltage to the PWM 38 to determine the duty cycle of the DC-DC converter. By controlling the time rate of change of the duty cycle, the dV/dt of the power signal is limited. Thus, data integrity is maintained by the lowered dV/dt in the power signal not being passed by the DC blocking capacitors C3 and C4.

(31) Many other types of circuits may be used to limit the slew rate of the duty cycle of the DC-DC converter in the PD to prevent sudden changes in the PD load from resulting in a problematic dV/dt in the power signal.

(32) The terms PSE and PD are used throughout this disclosure to identify equipment that supplies power and equipment that receives the power, and such equipment/devices are not limited to Ethernet equipment/devices unless specified.

(33) While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.