Cut first alternative for 2D self-aligned via

Abstract

A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO.sub.2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO.sub.2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Claims

1. A device comprising: a silicon (Si) substrate; a silicon oxide (SiO.sub.2) layer formed over the Si substrate; a plurality of amorphous silicon (a-Si) dummy metal lines formed over the SiO.sub.2 layer, each a-Si dummy metal line having an upper surface and one or more of the a-Si dummy metal lines having a via; a first etch stop layer formed over the upper surface of the a-Si dummy metal lines and in the via; a second etch stop layer formed over the first etch stop layer; and a silicon oxycarbide (SiOC) layer between the a-Si dummy metal lines, wherein the a-Si dummy metal lines are formed by: etching the second etch stop layer, the first etch stop layer and an a-Si dummy metal layer down to the SiO.sub.2 layer, and wherein the first etch stop layer formed in the via interrupts an a-Si dummy metal line including the via.

2. The device according to claim 1, wherein the plurality of a-Si dummy metal lines are formed by self-aligned double patterning (SADP).

3. The device according to claim 1, wherein the first etch stop layer is formed of SiOC and the second etch stop layer is formed of silicon nitride (SiN).

4. A device comprising: a silicon (Si) substrate; a silicon oxide (SiO.sub.2) layer formed over the Si substrate; a plurality of amorphous silicon (a-Si) dummy metal lines formed over the SiO.sub.2 layer, each a-Si dummy metal line having an upper surface and at least one of the a-Si dummy metal lines having a via; a first etch stop layer formed of SiOC over the upper surface of the a-Si dummy metal lines and in the via; a second etch stop layer formed of silicon nitride (SiN) over the first etch stop layer; and a silicon oxycarbide (SiOC) layer between the a-Si dummy metal lines, wherein the a-Si dummy metal lines are formed by: etching the second etch stop layer, the first etch stop layer and an a-Si dummy metal layer down to the SiO.sub.2 layer, and wherein more than one of the a-Si dummy metal lines has a via, and wherein the first etch stop layer formed in the vias interrupts a-Si dummy metal lines including the vias.

5. The device according to claim 4, wherein the first and second etch stop layers are formed in different processing steps.

6. The device according to claim 4, wherein the first and second etch stop layers are formed in a single processing step.

7. The device according to claim 4, wherein the a-Si dummy metal lines are formed by self-aligned double patterning (SADP).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

(2) FIGS. 1 through 17 schematically illustrate a process flow for cutting a Mx line before the Mx line is defined by patterning, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

(3) In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

(4) The present disclosure addresses and solves the current problem of cost associated with forming a Mx line, cutting the Mx line, filling the cut, and polishing back the fill to uncover the top of the Mx line before Mx metallization attendant upon forming a 2DSAV device.

(5) Methodology in accordance with embodiments of the present disclosure includes forming an a-Si dummy metal layer over a SiO.sub.2 layer. A first softmask stack is formed over the a-Si dummy metal layer. A plurality of vias are patterned through the first softmask stack down to the SiO.sub.2 layer. The first soft mask stack is removed and first and second etch stop layers are formed over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias. A-Si mandrels are formed on the second etch stop layer and oxide spacers are formed on opposite sides of each a-Si mandrel. The a-Si mandrels are removed and a-Si dummy metal lines are formed in the a-Si dummy metal layer below the oxide spacers. A SiOC layer is formed between the a-Si dummy metal lines.

(6) Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

(7) Adverting to FIG. 1 (FIG. 1 is an orthographic view of a Mx stack), a SiO.sub.2 layer 101 is formed on a Si substrate 103. An a-Si dummy Mx layer 105 is then formed over the SiO.sub.2 layer 101. Next, a softmask stack 201 is formed over the a-Si dummy Mx layer 105, as depicted in FIG. 2. The softmask stack 201 may be formed, for example, of a SiOH layer 203, a SiON layer 205, a BARC layer 207, and a photoresist layer 209. Vias 211 are then patterned or cut through the softmask stack 201 down to the SiO.sub.2 layer 101, as depicted in FIG. 3. Consequently, the a-Si dummy Mx layer 105 and, therefore, future dummy Mx lines are cut before the Mx dummy lines have been defined by patterning.

(8) Adverting to FIG. 4A, once the soft mask stack 201 is removed, a SiOC layer 401 is formed over the a-Si dummy Mx layer 105, filling the vias 211 as depicted by the dashed circle 403 in FIG. 4B. (FIG. 4A is an orthographic view of the Mx stack and FIG. 4B is a cross-sectional view along the dashed line 405 of FIG. 4A). The SiOC layer 401 may be formed, for example, to a thickness of 8 nm to 15 nm, e.g., 12 nm. The lines 407 represent indentations in the surface of the SiOC layer 401 where the SiOC layer 401 filled the vias 211 of the a-Si dummy Mx layer 105.

(9) Adverting to FIG. 5, a SiN layer 501 is formed over the SiOC layer 401. Lines 503, like lines 407, represent indentations in the SiN layer 501 where the SiOC layer 401 filled the vias 211. The SiOC layer 401 and the SiN layer 501 may alternatively be formed, for example, in a single process step. Next, an a-Si layer 601 is formed over the SiN layer 501, as depicted in FIG. 6. Lines 603, like the lines 407 and 503, represent indentations in the a-Si layer 601 where the SiOC 401 layer filled the vias 211.

(10) A softmask stack 701 is then formed over the a-Si layer 601, as depicted in FIG. 7. Similar to the softmask stack 201, the softmask stack 701 may be formed, for example, of a SiOH layer 703, a SiON layer 705, a BARC layer 707, and a photoresist layer 709. Once the softmask stack 701 is formed, the photoresist layer 709 may be patterned down the BARC layer 707, the patterning forming parallel lines 709′. Thereafter, a-Si mandrels 601′ are formed by etching between the parallel lines 709′ down to the SiN layer 501, as depicted in FIG. 8. Adverting to FIG. 9, once the softmask stack 701 is removed, an oxide layer 901 is formed over the a-Si mandrels 601′. The oxide layer 901 is then anisotropically etched down to the a-Si mandrels 601′ and the SiN layer 501, respectively, to form spacers 901′ on opposite sides of each a-Si mandrel 601′, as depicted in FIG. 10. The oxide spacers 901′ may then be used to form the future a-Si dummy Mx lines by spacer image transfer (SIT) for SADP.

(11) Adverting to FIG. 11, the future a-Si dummy Mx lines may be formed, for example, by first removing or pulling-out the a-Si mandrels 601′. Adverting to FIG. 12, the SiN layer 501 is etched down to the SiOC layer 401 so that the SiN layer 501 only remains under the spacers 901′. Next, the SiOC layer 401 is etched, e.g., by a punch etch, down to the SiO.sub.2 layer 105, as depicted in FIG. 13. Consequently, the SiOC layer 401, like the SiN layer 501, only remains under the spacers 901′. Adverting to FIG. 14, the spacers 901′ are removed, e.g., by etching. The SiN layer 501 acts as an etch stop layer. The resulting a-Si dummy Mx lines 1501 are then formed, e.g., by a-Si etching the a-Si layer 105 down to the SiO.sub.2 layer 101, with the SiN layer 501 acting as a hardmask, as depicted in FIG. 15A. (FIG. 15A is an orthographic view of the Mx stack, and FIG. 15B is an overhead view of FIG. 15A). In particular, the a-Si layer 105 is etched selective to oxide. Consequently, the SiOC layer 401 formed in the vias 211 of the a-Si dummy Mx layer 105 (under the indentation lines 503) interrupts the respective a-Si dummy Mx lines 1501, as depicted in FIG. 15B. Alternatively, the Mx line etch steps of FIGS. 11 through 15B may be combined into a single integrated etching process and/or performed in a single etch chamber.

(12) Adverting to FIG. 16, a SiOC layer 1601 may be formed, for example, over and between the a-Si dummy Mx lines 1501. The SiOC layer 1601 may also be formed, for example, of SiO.sub.2 or SiN; however, SiOC has a lower K value than either SiO.sub.2 or SiN. Therefore, the resulting device should have a lower capacitance if SiOC is used to fill between the a-Si dummy Mx lines 1501 rather than SiO.sub.2 or SiN. Lines 1603 represent indentations in the SiOC layer 1601 above where the SiOC layer 401 filled the vias 211. The SiOC layer 1601 is then planarized, e.g., by CMP, down to the SiN layer 501, as depicted in FIG. 17. The dashed circles 1701 illustrate where the SiOC layer 401 interrupts the respective a-Si dummy Mx lines 1501. Consequently, in contrast to the formation steps of the known approach, by cutting the future Mx lines in the a-Si dummy Mx layer 105 before the Mx lines are defined by patterning, the SiOC layer 401 formed over the a-Si dummy Mx layer 105 and filled in the vias 211 no longer needs to be polished back to uncover the top of the Mx dummy lines since the Mx dummy lines have yet to be formed. Rather, the SiOC layer 401 is now used as a hardmask for forming the subsequent Mx dummy lines and, therefore, saving at least one etching step of the overall process.

(13) The embodiments of the present disclosure can achieve several technical effects including reducing costs by avoiding at least one etch step and possibly a deposition and an etch step. In addition, the present disclosure may have alignment advantages since the Mx line is aligned with the Mx cut. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices in the 10 nm technology node and beyond.

(14) In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.