Strong white-box cryptography

Abstract

A method is provided for generating an output from an input according to a secret using a white-box implementation of a cryptographic function having a first operation, a second operation, and a third operation. The method applies the input to a first operation to generate a first intermediate result, applies the first intermediate result to a second operation to generate a second intermediate result, and applies the second intermediate result to a third operation to generate the output, wherein at least two of the first operation, the second operation, and the third operation is implemented by a plurality of interconnected logic elements, the interconnection of the plurality of logic elements being comprised of one of a non-algebraic interconnection of logic elements and an algebraic interconnection of logic elements having obfuscated boundaries between the at least one of the first operation, the second operation and the third operation.

Claims

1. A method for providing digital signal security comprising: generating at least one output from at least one input and at least one secret that uses a white-box implementation of a randomized cryptographic function, the randomized cryptographic function obtained by at least one random operation performed on the whole of a nonrandomized function; providing the randomized cryptographic function as a plurality of interconnected logic elements, the interconnection of the plurality of logic elements being comprised of non-algebraic interconnection of logic elements and algebraic interconnection of logic elements having obfuscated boundaries between the at least one input and output; wherein the non-algebraic interconnected logic elements comprises a cyclic connection of at least a portion of the plurality of interconnected logic elements that produces an equivalent input-output relationship of a non-cyclic connection of logic elements; wherein the logic elements are Boolean circuit gates; and wherein the randomized cryptographic function has fewer Boolean circuit gates than the whole of the nonrandomized function.

2. The method of claim 1 wherein the logic elements are implemented by associated lookup tables.

3. The method of claim 1, wherein the randomized cryptographic function is implemented by a subset (S) of the plurality of interconnected logic elements.

4. The method of claim 3, wherein the subset (S) of the plurality of interconnected logic elements is defined by: slicing a graph of the plurality of interconnected logic elements into the subset (S) of the plurality of interconnected logic elements; and converting the subset (S) into a logic element having a fan-in equal to a number of inputs to the slice.

5. The method of claim 4, wherein each of the plurality of interconnected logic elements are Boolean hardware circuit gates.

6. The method of claim 4, wherein the each of the plurality of interconnected logic elements are implemented by an associated lookup table.

7. The method of claim 1, wherein the plurality of interconnected logic elements is randomized by performing a plurality of Mal'tsev superposition operations on a non-randomized interconnection of plurality of logic elements for computing the randomized cryptographic function.

8. The method of claim 1, wherein the plurality of interconnected logic elements is a randomized plurality of interconnected logic elements, randomized by: generating a non-randomized plurality of interconnected logic elements C1 for computing the randomized cryptographic function; performing at least one of the following on the non-randomized plurality of interconnected logic elements—C1 to generate the randomized plurality of interconnected logic elements: introduction of a variable to the non-randomized plurality of interconnected logic elements C1; permutation of a variable of the non-randomized plurality of interconnected logic elements C1; deletion of a logic element of the non-randomized plurality of interconnected logic elements C1, the deleted logic element being an input gate having all outgoing edges removed and assigned to another input gate of the plurality of interconnected logic elements C1; and substitution of a logic gate of the plurality of interconnected logic elements C1 by a second interconnection of logic elements C2.

9. An apparatus for providing digital signal security comprising: a processor; a memory, communicatively coupled to the processor, the memory storing instructions comprising instructions for: generating at least one output from at least one input according to a secret that uses a white-box implementation of a randomized cryptographic function, the randomized cryptographic function obtained by at least one random operation performed on the whole of a nonrandomized function; providing the randomized cryptographic function as a plurality of interconnected logic elements, the interconnection of the plurality of logic elements being comprised of anon-algebraic interconnection of logic elements and an algebraic interconnection of logic elements having obfuscated boundaries between the at least one input and output; wherein the non-algebraic plurality of interconnected logic elements comprises a cyclic connection of at least a portion of the plurality of interconnected logic elements that produces an equivalent input-output relationship of a non-cyclic connection of logic elements, wherein the logic elements are Boolean circuit gates; and wherein the randomized cryptographic function has fewer Boolean circuit gates than the whole of the nonrandomized function.

10. The apparatus of claim 9, wherein the randomized cryptographic function is implemented by a subset (S) of the plurality of interconnected logic elements.

11. The apparatus of claim 10, wherein the subset (S) of the plurality of interconnected logic elements is defined by: slicing a graph of the plurality of interconnected logic elements into the subset (S) of the plurality of interconnected logic elements; and converting the subset (S) into a logic element having a fan-in equal to a number of inputs to the slice.

12. The apparatus of claim 11, wherein the each of the plurality of interconnected logic elements are implemented by an associated lookup table.

13. A non-transitory computer readable medium containing program instructions for causing a computer to perform the method of: generating at least one output from at least one input according to a secret that uses a white-box implementation of a randomized cryptographic function, the randomized cryptographic function obtained by at least one random operation performed on the whole of a nonrandomized function; providing the randomized cryptographic function as a plurality of interconnected logic elements, the interconnection of the plurality of logic elements being comprised of non-algebraic interconnection of logic elements and algebraic interconnection of logic elements having obfuscated boundaries between at the least one input and output; wherein the non-algebraic interconnected logic elements comprises a cyclic connection of at least a portion of the plurality of interconnected logic elements, wherein the logic elements are Boolean circuit gates; and wherein the randomized cryptographic function has fewer Boolean circuit gates than the whole of the nonrandomized function.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

(2) FIGS. 1A and 1B are diagrams of a cryptographic system for and its corresponding white-box implementation;

(3) FIGS. 2A and 2B are diagrams showing a white-box lookup table;

(4) FIG. 3 is a diagram presenting a method for generating strong white-box implementation;

(5) FIGS. 4A and 4B are diagrams presenting a generated Boolean circuit;

(6) FIG. 5 is a diagram illustrating the implementation of cryptographic operations using a white-box at least partially implemented by logic gates such as hardware logic gates;

(7) FIG. 6 is a diagram illustrating an improved white box system using Boolean circuits;

(8) FIG. 7 is a diagram illustrating exemplary process steps that can be used to generate the randomized Boolean circuit comprising the plurality of interconnected logic gates;

(9) FIGS. 8A and 8B are diagrams illustrating a simple case of how selective random cyclic substitutions may be used to reduce the number of gates in the randomized Boolean circuit and also hide or remove function boundaries;

(10) FIG. 9 is a diagram presenting a circuit partitioning example illustrating a white-box encoded circuit computing ƒ.sub.1∘ƒ.sub.2∘ƒ.sub.3, with original function boundaries a.sub.1, a.sub.2, . . . , a.sub.8;

(11) FIG. 10 is a diagram illustrating exemplary operations that can be performed to define the partition (S) of interconnected logic gates; and

(12) FIG. 11 is a diagram illustrating an exemplary computer system that could be used to implement elements of this disclosure.

DETAILED DESCRIPTION

(13) In the following description, reference is made to the accompanying drawings which form a part hereof, and which is shown, by way of illustration, several embodiments of the present invention. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

(14) FIGS. 1A and 1B are diagrams of a cryptographic system processing an (input) to produce an output, and its corresponding white-box implementation. Similar cryptographic systems are defined in “White-box cryptography,” by Steven D Galbraith and L. Aaron Anderson, 2013, pages 1-12, which is hereby incorporated by reference herein.

(15) As shown in FIG. 1A, the algorithm performs functions ƒ.sub.1, ƒ.sub.2 and ƒ.sub.n (102A, 102B, and 102N, respectively) using secret s.

(16) In FIG. 1B, each operation ƒ.sub.1, ƒ.sub.2, . . . , ƒ.sub.n in an original algorithm is encoded as a lookup-table T.sub.1, T.sub.2, . . . , T.sub.n (104A, 104B, and 104N, respectively) in the white-box implementation of that algorithm. The encodings are generated as two sequences of random bijections, δ.sub.1, δ.sub.2, . . . , δ.sub.n+1 that are applied to the inputs and output of each operation, where ρ(s) represents an encoded secret (e.g. a secret key), which is either linked statically or provided dynamically to the white-box implementation.

(17) In the white-box implementation shown in FIG. 1B this is implemented by applying bijections δ.sub.1 and ρ(s) as an input to lookup table T.sub.1 to obtain an intermediate output, applying the intermediate output and ρ(s) to lookup table T.sub.2 to produce a second intermediate output, then providing the second intermediate output and ρ(s) to lookup table T.sub.3 to produce output δ.sub.n+1.sup.−1 (⋅). Lookup table T.sub.1 inverts the bijection δ.sub.1 of the input by δ.sub.1.sup.−1, inverts the bijection ρ of s (ρ(s)) by ρ.sub.1.sup.−1, applies ƒ.sub.1 and then applies bijection δ.sub.2 to produce the first intermediate output. Similarly, lookup table T.sub.2 inverts the bijection δ.sub.2 of the first intermediate input by δ.sub.2.sup.−1, inverts the bijection ρ of s (ρ(s)) by ρ.sub.2.sup.−1, applies ƒ.sub.2 and then applies bijection δ.sub.3 to produce the first intermediate output. Generally, final lookup table T.sub.n inverts the bijection δ.sub.n of the n−1.sup.th intermediate input by δ.sub.n.sup.−1, inverts the bijection ρ of s (ρ(s)) by ρ.sub.n.sup.−1, applies ƒ.sub.n and then applies bijection δ.sub.n+1 to produce the intermediate output δ.sub.n+1.sup.−1(⋅).

(18) For concreteness, we focus on white box implementations of symmetric-key cryptosystems, such as AES.

(19) Notation: A PPT (probabilistic-polynomial-time) algorithm is an algorithm that runs in polynomial time in the length of its inputs, with a probability distribution D={A(x)} for all inputs x. The PPT is said to be uniform if D is uniform.

(20) Let (Enc, Dec, Gen, K, M, M′) be a heuristically strong symmetric-key cryptosystem, with cipher-pair (Enc, Dec), key generator Gen, key k∈K message m∈M and ciphertext m′∈M′. Then for k←Gen, let m′=Enc(k, m) be an encrypted message, such as a media stream.

(21) Definition 1 (White-Box System):

(22) The system (wbGen, wbCompile, wbEncode, δ, γ) is a white box system, with uniform PPT white-box key-generator wbGen, uniform PPT white-box compiler wbCompile, uniform PPT white-box encoder wbEncode, external input encoding δ and external output encoding γ, if and only if the following properties hold for all white-box instances φ←wbGen:

(23) 1. Efficiently computable: For a PT algorithm of size n the white-box implementation ′ wbCompile (φ; ) is efficiently computable with blowup l=poly (n).

(24) 2. Functionally equivalent. Let Dec′←wbCompile(φ, Dec) be a white-box implementation of the inverse-cipher Dec, then for all messages m∈M, all keys k∈K, each encrypted message m′=Enc (k,m) and each white-box encoded key k′←wbEncode (φ, k), it holds that m=Dec(k, m′)=(Dec′(k′, (m′)))

(25) 3. Hard to invert: It is computationally hard to obtain the secret key k∈K given full access to any white-box inverse-cipher implementation Dec′ of Dec and encoded key k′. This is a variation on the definition described in “Cryptographic schemes based on the ASASA structure: Black-box, white-box, and public-key,” by Alex Biryukov, Charles Bouillaguet, and Dmitry Khovratovich, Advances in Cryptology 2014, which is hereby incorporated by reference herein.

(26) White-Box Key-Recovery Attacks

(27) A goal of a white-box attacker is to recover the secret s from a white-box implementation, where s is encoded with a bijection ρ. Since ρ is randomly chosen, it is infeasible for an attacker to brute-force the encoding for a randomly chosen s from a sufficiently large keyspace.

(28) FIGS. 2A and 2B are diagrams showing a white-box lookup table. In the illustrated example the lookup table ƒ′: {0, 1}.sup.3×{0, 1}.sup.3.fwdarw.{0,1}.sup.3 that satisfies the encoding: ƒ′(δ(x.sub.6, x.sub.5, x.sub.4), ρ(x.sub.3,x.sub.2,x.sub.1,))=(y.sub.3, y.sub.2, y.sub.1)=γ((x.sub.6, x.sub.6, x.sub.6)⊕(x.sub.6, x.sub.6, x.sub.6,))

(29) where δ:=(2 3 4 0)(5 1)(6 7), ρ:=(4 2 6 5 7 1 0)(3)(6 7) and γ:=(0)(7 5 6 2 1)(3)(4) are random bijections, defined in cycle notation. For example, in cycling notation, a permutation with the following rules: 1.fwdarw.3, 2.fwdarw.6, 3.fwdarw.4, 4.fwdarw.5, 5.fwdarw.1, 6.fwdarw.2, 7.fwdarw.7 and 8.fwdarw.8 can be written in cycle notation as: (3 4 5 1) (6 2) (7) (8).

(30) In real-word implementations, white-box lookup-tables typically represent word sized operations, such as ƒ: {0, 1}.sup.16.fwdarw.{0, 1}.sup.8, which can be stored in a memory array of 64K bytes.

(31) To attain a computationally feasible key recovery work factor, knowledge of the algebra of the underlying cipher is used to gain information about the secret key. Such attacks against white-box AES are known collectively as the Billet, Gilbert and Ech-Chatbi or “BGE” attacks. Such attacks have been described in “Cryptanalysis of a white box AES implementation. In Selected Areas in Cryptography,” by O Billet, H Gilbert, and C Ech-Chatbi, volume 3357, pages 227-240. Springer, 2005; “Cryptanalysis of a perturbated white-box AES implementation. Progress in Cryptology-INDOCRYPT,” by Yoni De Mulder, Brecht Wyseur, and Bart Preneel, 2010; “Revisiting the BGE Attack on a White-Box AES Implementation,” by Yoni De Mulder, Peter Roelse, and Bart Preneel, eprint.iacr.org, 2013; and “Another Nail in the Coffin of White-Box AES Implementations,” by Tancrède Lepoint and Matthieu Rivain, eprint.iacr.org, 2013, all of which are hereby incorporated by reference. The only assumption of these attacks is that the precise location and structure of the lookup tables T.sub.1, T.sub.2, . . . , T.sub.n is known, as described in “A Framework for Measuring Software Obfuscation Resilience Against Automated Attacks,” by Sebastian Banescu, M Ochoa, and Alexander Pretschner, In Software Protection (SPRO), 2015 IEEE/ACM 1st International Workshop on, pages 45-51. IEEE, 2015.

(32) Given this knowledge of a white-box AES implementation (as described in “White-Box Cryptography, and an AES Implementation,” by Stanley Chow, Philip Eisen, Harold Johnson, and Paul C Van Oorschot, In Selected Areas in Cryptography, pages 250-270, Springer, 2003, which is hereby incorporated by reference herein), an attack can recover the hidden 128-bit secret key with a work factor of 2.sup.22, which is an upper bound on the lower bound for the work factor of automatic secret key recovery attacks against this white-box. Such a possible attack is described in “Revisiting the BGE Attack on a White-Box AES Implementation,” by Yoni De Mulder, Peter Roelse, and Bart Preneel, eprint.iacr.org, 2013.

(33) Partitioned Boolean Circuit Construction

(34) Lookup-tables in white-box implementations are “obvious” algebraic structures that can be identified with the likes of dynamic binary analysis and other similar attacks. To attain resilience against algebraic cryptanalysis we dispense with lookup tables and instead propose a partitioned Boolean circuit construction to hide or completely remove the boundaries between the white-box encoded operations in the final implementation.

(35) More formally, let B be a set of Boolean functions. By [B] we denote the class of all Boolean functions that can be obtained by the following rule: If (x.sub.1, . . . , x.sub.n)∈[B] and x.sub.1, are either Boolean variables or elements from [B], then ƒ(x.sub.1, . . . , x.sub.n)∈[B].

(36) We say that B is a closed basis if [B]=B, where it is interesting to note that [B] is exactly the class of Boolean functions that can be computed by circuits with gates from B.

(37) Definition 2 (Boolean Circuit)

(38) An n-input Boolean circuit over a closed basis B is a directed graph, where each node is labelled either with a variable x.sub.i, or a function from B, called a gate. The edges connecting the nodes are called wires. The number of wires pointing into a gate is called its fan-in, and the number of wires leaving a gate is called its fan-out. The Boolean circuit may be implemented by one or more “gates” which may be implemented by hardware logic gates or by use of a processor implementing analogous functionality using lookup tables.

(39) Suppose we have a Boolean circuit C.sub.1 computing the n-ary Boolean function ƒ.sub.c.sub.1, and another Boolean circuit C.sub.2 computing an m-ary function ƒ.sub.c.sub.2. We can derive new Boolean circuits that may be used to obfuscate the functionality of the circuit in a number of ways including the use of the following Mal'tsev superposition operations:

(40) A new circuit C′.sub.1 may be obtained by adding a variable to C.sub.1. Since no new edges are added, the new node has no influence on the computed Boolean function besides the higher arity. We call this operation introduction and obtain:
∀x.sub.1, . . . ,x.sub.n+1∈{0,1}: ƒc′.sub.1(x.sub.1, . . . ,x.sub.n+1)=ƒ.sub.c.sub.1(x.sub.1, . . . ,x.sub.n+1)

(41) Circuit C′.sub.1 may also be obtained from C.sub.1 by arbitrarily permuting the variables. This operation will be called permutation; and if π∈S.sub.n is our permutation, we have:
∀x.sub.1, . . . ,x.sub.n∈{0,1}: ƒc′.sub.1(x.sub.1, . . . ,x.sub.n)=ƒ.sub.c.sub.1(x.sub.π.sub.1.sub.−1, . . . ,x.sub.π.sub.n.sub.−1).

(42) Since the fan-out of gates is not restricted, we can remove all outgoing edges of one input gate g of C.sub.1 and assign them to another input gate g.sub.j. After this operation, g.sub.i is a fictive gate and is deleted. The derived circuit C′.sub.1 thus computes a function of arity n−1, given by:
∀x.sub.1, . . . ,x.sub.n∈{0,1}: ƒ′.sub.c.sub.1(x.sub.1, . . . ,x.sub.i−1,x.sub.i+1, . . . ,x.sub.n)=ƒ.sub.c.sub.1(x.sub.1, . . . ,x.sub.i−1,x.sub.j, . . . ,x.sub.n).

(43) This operation may be referred to as deletion.

(44) A gate g.sub.n of C.sub.1 can be replaced by the whole circuit C.sub.2, to obtain a new Boolean circuit C′ of arity n+m−1. For the Boolean function ƒ′.sub.c obtained in this way, we have a substitution operation:
∀x.sub.1, . . . ,x.sub.n∈{0,1}: ƒ′.sub.c.sub.1(x.sub.1, . . . ,x.sub.n+m−1)=ƒ.sub.c.sub.1(x.sub.1, . . . ,x.sub.i−1,ƒ.sub.c.sub.2(x.sub.n, . . . ,a.sub.n+m−1).

(45) Since every Boolean circuit can be obtained by a sequence of the above superposition operations, they may be used to generate a circuit for uniform PPT white-box implementation.

(46) Given n functions {ƒ.sub.1, . . . , ƒ.sub.n} in an original algorithm , FIG. 3 is a diagram presenting a method for generating white-box encoded circuits C={c.sub.1, . . . , c.sub.n} under a closed basis B with maximum fan-in k, such that for 1≤i≤n, it holds that
∀a,b∈{0,1}.sup.k: c.sub.i(δ.sub.i(a),ρ.sub.i(b))=δ.sub.i+1(ƒ.sub.i(a,b))  (1)

(47) Let S.sub.k represent the symmetric group of degree k, with symbols in {0, . . . , k−1}, then: 1. Generate a random external input encoding (bijection) δ.sub.1 by uniformly random sample from S.sub.k. 2. For each 1≤i≤n a. Generate a random secret encoding ρ.sub.i by uniformly random sample from S.sub.k. b. Generate a random output encoding δ.sub.i+1 by uniformly random sample from S.sub.k. c. Generate a white-box encoded circuit c.sub.i under basis B that computes (1). 3. Return a. The generated circuits {c.sub.1, . . . , c.sub.n}. b. The generated input and output encodings {δ.sub.0, δ.sub.n+1.sup.−1}. c. The generated secret encodings {Σ.sub.1, . . . , ρ.sub.n}.

(48) FIGS. 4A and 4B are diagrams presenting a generated Boolean circuit to yielding the white box encoding in equation 1 and summarized in the lookup table of FIGS. 2A and 2B using the foregoing method.

(49) FIG. 5 is a diagram illustrating the implementation of cryptographic operations using a white-box at least partially implemented by logic gates such as hardware logic gates. FIG. 6 will be discussed in conjunction with FIG. 6, which is an illustration of an improved white box system using Boolean circuits. Like the non-white-box implementation illustrated in FIG. 1A, the white-box implementation performs functions ƒ.sub.1, ƒ.sub.2 and ƒ.sub.n (102A, 102B, and 102N) using secrets. Unlike the white-box implementation illustrated in FIG. 1B, two or more of the functions ƒ.sub.1, ƒ.sub.2 and ƒ.sub.n (102A, 102B, and 102N) is performed using Boolean circuits C.sub.1, C.sub.2 and C.sub.n, respectively rather than lookup tables T.sub.1, T.sub.2, T.sub.n. As such functions may be performed by either a processor using a lookup table stored in a memory or Boolean circuits, the entities that perform these functions are hereinafter referred to as modules 502, 502B and 502C, respectively.

(50) Referring now to FIG. 6, an input 501 and ρ(S) 503 are provided to a first operation ƒ.sub.1 implemented by module 502A to generate a first intermediate result 504. In block 704, the first intermediate result 504 and the secret 503 are applied to a second operation ƒ.sub.2 implemented by module 502B to generate a second intermediate result 508. In block 706, the second intermediate result 508 and secret 503 are applied to a third operation ƒ.sub.3 to generate the output 515. At least two of the first operation, the second operation, and the third operation is implemented by a plurality of interconnected logic elements. For example, if the first operations ƒ.sub.1 and ƒ.sub.2 include comprise the operation described in Equation (1), the lookup table T.sub.1 illustrated in FIGS. 2A and 2B (a white-box implementation of Equation (1) can instead be performed by the Boolean circuit illustrated in FIGS. 4A and 4B, as generated by performing step 5 of the of the operations illustrated in FIG. 3.

(51) In one embodiment, the interconnection of the plurality of logic elements being comprised of one of a non-algebraic interconnection of logic elements. The use of a non-algebraic interconnection of logic elements prevents or substantially inhibits the white-box attacks described above.

(52) Standard lookup tables used in white-box cryptography are “quasigroups” in the group theoretic sense. A quasigroup is an algebraic structure that consists of a set of elements along with an operation * that combines the two elements to form a third element that satisfies the axiom of closure and a “latin” property, such that for any two integers a, b in G, a*b is also an integer in G, thus satisfying the closure requirement. Also, for all integers a, b in G, there exist unique elements x and y also in G, where it holds that a*x=b and y*a=b.

(53) However, Boolean circuits can be devised that do not meet the requirements for a group, or even for an algebra. Non-algebraic Boolean circuits can be devised that comply with only one of the requirements of a group, namely, the closure requirement. One technique for generating non-algebraic interconnections can be established for example, by using a cyclic circuit as described below.

(54) In another embodiment, the an algebraic interconnection of logic elements is used, but the interconnection of logic elements is obfuscated. This can be accomplished by randomizing the interconnection of logic elements and/or obfuscating the boundaries between the at least one of the first operation, the second operation and the third operation, as further described below.

(55) As is plain from the Boolean circuit illustrated in FIGS. 4A and 4B, even simple functions (e.g. the exclusive OR operation of Equation (1) can result in a randomized Boolean circuit C.sub.1 having a large number of gates. Techniques for improving the security of a white-box implementation with such gates are also discussed below.

(56) Randomized Interconnected Logic Gates

(57) FIG. 7 is a diagram illustrating exemplary process steps that can be used to generate a randomized Boolean circuit comprising the plurality of interconnected logic gates. In block 702, a non-randomized circuit C.sub.1 is generated for computing at least one of the first operation, the second operation, and the third operation. In block 704, the randomized Boolean circuit is generated by performing at least one of (A) introduction of a variable into the non-randomized Boolean circuit C.sub.1, (B) permutation of a variable of the non-randomized Boolean circuit C.sub.1, (C) deletion of a logic gate of the non-randomized Boolean circuit C.sub.1, wherein the deleted logic gate is an input gate having all outgoing edges removed and assigned to another input gate of the non-randomized Boolean circuit C.sub.1, and (D) substitution of a logic gate of the non-randomized Boolean circuit C.sub.1 by a second Boolean circuit C.sub.2, as described above.

(58) “Cyclic” Encoding

(59) Cyclic circuit implementations can be defined that have having equivalent input-output relationships as non-cyclic (acyclic) implementations. Such acyclic implementations are non-algebraic (across operation boundaries), as they do not satisfy the requirements to qualify them as an algebra, thus making such white-box implementations using such structures more resistant to attack. Further, in some cases, cyclic circuit implementations can have as few as one-half the gates required for equivalent acyclic circuits.

(60) Thus, cyclic circuit implementations can also hide or completely remove function boundaries in Boolean circuit implementations, and deny hackers the ability to infer the functionality of white-box implementation. For example, referring to FIG. 5, if a hacker is able to identify which functional elements perform function ƒ.sub.1 to produce intermediate result 504, the job of determining the functions performed by ƒ.sub.1 becomes easier (e.g. by simply observing input-output behavior). However, if the point where the intermediate output of function ƒ.sub.1 is obfuscated, the hacker will find it difficult to infer such functionality from the input/output behavior. Therefore, from a security perspective, selective random cyclic substitutions act as a kind of “partitioning” that can hide or completely remove the function boundaries in Boolean circuit implementations.

(61) FIGS. 8A and 8B are diagrams illustrating a simple case of how selective random cyclic substitutions may be used to reduce the number of gates in the randomized Boolean circuit and also hide or remove function boundaries.

(62) FIG. 8A presents an exemplary acyclic Boolean circuit (left) and FIG. 8B presents the equivalent cyclic Boolean circuit (right) with one fewer gate, where the removed gate g.sub.7 is the output gate of the previous operation, hence concealing the output of ƒ.sub.1 “in” the cyclic circuit implementation of ƒ.sub.2. Under this hypothesis we say that the cyclic Boolean circuit implementation of ƒ.sub.1 and ƒ.sub.2 is nonseparable or “strongly connected.” Strongly connected circuits may be defined as described in Definition 3 below:

(63) Definition 3 (Strongly Connected Components):

(64) In a directed graph G, a strongly connected component is an induced subgraph S.Math.G, such that (1) There exists a directed path between every pair of nodes in S, and (2) for every node s∈S and every node n.Math.S, if there exists a path from s to n (from n to s) then there is no path from n to s (from s to n, respectively).

(65) Theorems 1 and 2 may be postulated.

(66) Theorem 1 (Menger's theorem [23]). Let u and v be distinct, non-adjacent vertices in a graph G. Then the maximum number of internally disjoint u-v paths in G equals the minimum number of vertices needed to separate u and v.

(67) Theorem 2 (Nonseparable [11]). Let G be a directed graph. Then G is nonseparable if and only if any two edges lie on a common cycle.

(68) Proof. Suppose G is separable such that G can be decomposed into two connected subgraphs S.sub.1 and S.sub.2. Then no one is contained in another and have exactly one vertex v in common. Let e.sub.1 be edges of S.sub.i, i=1, 2 incident with v.

(69) If one of e.sub.1, e.sub.2 is a loop, then there is no cycle containing both e.sub.1 and e.sub.2. This leads to a contradiction, therefore e.sub.i are not loops. Let v.sub.i be another end-vertex of e.sub.i, i=1, 2 other than v. Clearly there is no v.sub.1v.sub.2 path in G−v. Hence, there is no cycle in G that contains both e.sub.1 and e.sub.2.

(70) If G is a loop, then nothing is to be proved.

(71) If G is not a loop, then G has no loops. If we assume that G has at least two edges. Let e be an edge with end-vertices v.sub.1 and v.sub.2. Subdivide e into two edges by introducing a new vertex w on e to obtain a new graph G′. We claim that G′ is also nonseparable. By way of contradiction, suppose that is separable. Then G must be separated at the vertex w into two connected subgraphs G′.sub.1 and G′.sub.2. We may assume that vi belongs to G′.sub.i, i=1, 2. Then w is a cut vertex of G′ and subsequently the edge e is a cut edge of G. Thus G\e has two connected components G.sub.1 and G.sub.2 with v.sub.i∈V(G.sub.i). Since G has at least two edges, then either G.sub.1 has an edge at v.sub.1 or G.sub.2 has an edge at v.sub.2. If we suppose that G.sub.1 has an edge at v.sub.1, then G can be separated at v.sub.1 into G.sub.1 and G.sub.2 ∪e∪v.sub.1. This is a contradiction.

(72) Finally, let e.sub.1 and e.sub.2 be two edges of G. Subdivide e.sub.i by introducing a new vertex v.sub.i on e.sub.i to obtain a new graph G′.sub.i, i=1, 2. Then, G′.sub.i is nonseparable and the graph G′ is also nonseparable and has at least three vertices. Since Nonseparable graphs have no cut vertices, then by theorem 1, there are two internally disjoint v.sub.1v.sub.2-paths and therefore there is a cycle containing both edges e.sub.1 and e.sub.2.

(73) Secure Circuit Partitioning Construction

(74) Circuit partitioning divides a given circuit into a collection of smaller sub-circuits subject to specific constraints, such as fan-in size or depth, as described in “Large Scale Circuit Partitioning with Loose/Stable Net Removal and signal Flow Based Clustering,” by J. Cong, H. P. Li, Sung Kyu, Lim Sung Kyu Lim, T. Shibuya, and Dongmin Xu Dongmin Xu, Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference, ISSN 1092-3152.

(75) These methods are typically oriented around efficiency, whereas our primary interest is using circuit partitioning to conceal functional boundaries in the white-box implementation. The goal of the partitioning algorithm is to slice the graph of C into partitions that are orthogonal to the original function boundaries. These slices are then converted into Boolean gates (or equivalent look up tables (LUTs)) with a fan-in equal to the number of inputs in that slice, bound by the parameter k.

(76) Returning to the generalized embodiment of FIGS. 4A and 4B, one embodiment of this technique is evidenced by one in which the first operation 502A and the second operation 502B are implemented by the plurality of interconnected logic gates and the first operation 502A and the second operation 502B are partially implemented by a partition (S) of the interconnected logic gates, which may be constructed of a one or more higher order gates.

(77) FIG. 9 is a diagram presenting a circuit partitioning example illustrating a white-box encoded circuit computing ƒ.sub.1 ∘ƒ.sub.2 ∘ƒ.sub.3, with original function boundaries a.sub.1, a.sub.2, . . . , a.sub.8. The algorithm partitions the circuit into slices S.sub.1, . . . , S.sub.5 (only 5 are illustrated for the purposes of clarity) with new boundaries b.sub.1, b.sub.2, . . . , b.sub.11 that don't overlap the original function boundaries. Each slice is then converted into a Boolean gate (LUT).

(78) FIG. 10 is a diagram illustrating exemplary operations that can be performed to define the subset (S) of interconnected logic gates common to adjacent functions. In block 1002, a graph (e.g. topological interconnection) of the interconnected logic gates is sliced to define a subset (S) of the logic gates common to ƒ.sub.1 and ƒ.sub.2. For example, referring to FIG. 9, the illustrated slice defines the following subsets of the gates:

(79) S.sub.1: Gates g.sub.2, g.sub.3, g.sub.4, g.sub.7, g.sub.10 and g.sub.13, common to functions ƒ.sub.1 and ƒ.sub.2, and ƒ.sub.3;

(80) S.sub.2: Gates g.sub.2, g.sub.3, g.sub.5, and g.sub.8, common to functions ƒ.sub.1 and ƒ.sub.2;

(81) S.sub.3: Gates g.sub.3 and g.sub.6, common to functions ƒ.sub.1 and ƒ.sub.2;

(82) S.sub.4: Gates g.sub.11 and g.sub.14, common to functions ƒ.sub.2 and ƒ.sub.3; and

(83) S.sub.5: Gates g.sub.9, g.sub.12 and g.sub.16, common to functions ƒ.sub.1 and ƒ.sub.2.

(84) In block 1004, the set S.sub.1 is converted into a gate having a fan-in (number of inputs) equal to the number of inputs for the slice. In the example presented in FIG. 9, the following gates having the number of inputs can be substituted for the associated subset of gates. This process is performed for additional sets S as required.

(85) The foregoing has the effect of compressing the randomized circuit implementation into fewer operations, while also concealing the original function boundaries. Table I below presents a table illustrating Boolean gates generated from the partitioning presented in FIG. 9. Note that the number of gates has been substantially reduced and the new boundaries do not overlap the original function boundaries, increasing the cost of algebraic attacks against the implementation.

(86) TABLE-US-00001 TABLE I Boolean gates Generated from the Partitioning of FIG. 9. Original New Slice # Gates Fan-in #Gates Fan-in S.sub.1 6 2 1 7 S.sub.2 3 2 1 5 S.sub.3 2 2 1 3 S.sub.4 2 2 1 3 S.sub.5 3 2 1 4

(87) Hardware Environment

(88) FIG. 11 is a diagram illustrating an exemplary computer system 1100 that could be used to implement elements of this disclosure, including one or more of the modules 102A-102C implementing the original algorithm, a computer implementing the white box implementations of FIG. 1B, or a computer used in designing the randomized Boolean logic gates of FIG. 5. The computer 1102 comprises a general purpose hardware processor 1104A and/or a special purpose hardware processor 1104B (hereinafter alternatively collectively referred to as processor 1104) and a memory 1106, such as random access memory (RAM). The computer 1102 may be coupled to other devices, including input/output (I/O) devices such as a keyboard 1114, a mouse device 1116 and a printer 1128.

(89) In one embodiment, the computer 1102 operates by the general purpose processor 1104A performing instructions defined by the computer program 1110 under control of an operating system 1108. The computer program 1110 and/or the operating system 1108 may be stored in the memory 1106 and may interface with the user and/or other devices to accept input and commands and, based on such input and commands and the instructions defined by the computer program 1110 and operating system 1108 to provide output and results.

(90) Output/results may be presented on the display 1122 or provided to another device for presentation or further processing or action. In one embodiment, the display 1122 comprises a liquid crystal display (LCD) having a plurality of separately addressable pixels formed by liquid crystals. Each pixel of the display 1122 changes to an opaque or translucent state to form a part of the image on the display in response to the data or information generated by the processor 1104 from the application of the instructions of the computer program 1110 and/or operating system 1108 to the input and commands. Other display 1122 types also include picture elements that change state in order to create the image presented on the display 1122. The image may be provided through a graphical user interface (GUI) module 1118A. Although the GUI module 1118A is depicted as a separate module, the instructions performing the GUI functions can be resident or distributed in the operating system 1108, the computer program 1110, or implemented with special purpose memory and processors.

(91) Some or all of the operations performed by the computer 1102 according to the computer program 1110 instructions may be implemented in a special purpose processor 1104B. In this embodiment, some or all of the computer program 1110 instructions may be implemented via firmware instructions stored in a read only memory (ROM), a programmable read only memory (PROM) or flash memory within the special purpose processor 1104B or in memory 1106. The special purpose processor 1104B may also be hardwired through circuit design to perform some or all of the operations to implement the present invention. Further, the special purpose processor 1104B may be a hybrid processor, which includes dedicated circuitry for performing a subset of functions, and other circuits for performing more general functions such as responding to computer program instructions. In one embodiment, the special purpose processor is an application specific integrated circuit (ASIC).

(92) The computer 1102 may also implement a compiler 1112 which allows an application program 1110 written in a programming language such as COBOL, C++, FORTRAN, or other language to be translated into processor 1104 readable code. After completion, the application or computer program 1110 accesses and manipulates data accepted from I/O devices and stored in the memory 1106 of the computer 1102 using the relationships and logic that was generated using the compiler 1112.

(93) The computer 1102 also optionally comprises an external communication device such as a modem, satellite link, Ethernet card, or other device for accepting input from and providing output to other computers.

(94) In one embodiment, instructions implementing the operating system 1108, the computer program 1110, and/or the compiler 1112 are tangibly embodied in a computer-readable medium, e.g., data storage device 1120, which could include one or more fixed or removable data storage devices, such as a zip drive, floppy disc drive 1124, hard drive, CD-ROM drive, tape drive, or a flash drive. Further, the operating system 1108 and the computer program 1110 are comprised of computer program instructions which, when accessed, read and executed by the computer 1102, causes the computer 1102 to perform the steps necessary to implement and/or use the present invention or to load the program of instructions into a memory, thus creating a special purpose data structure causing the computer to operate as a specially programmed computer executing the method steps described herein. Computer program 1110 and/or operating instructions may also be tangibly embodied in memory 1106 and/or data communications devices 1130, thereby making a computer program product or article of manufacture according to the invention. As such, the terms “article of manufacture,” “program storage device” and “computer program product” or “computer readable storage device” as used herein are intended to encompass a computer program accessible from any computer readable device or media.

(95) Of course, those skilled in the art will recognize that any combination of the above components, or any number of different components, peripherals, and other devices, may be used with the computer 1102.

(96) Although the term “computer” is referred to herein, it is understood that the computer may include portable devices such as cellphones, portable MP3 players, video game consoles, notebook computers, pocket computers, or any other device with suitable processing, communication, and input/output capability.

CONCLUSION

(97) This concludes the description of the preferred embodiments of the present invention. The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.

(98) It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the apparatus and method of the invention. Since many embodiments of the invention can be made without departing from the scope of the invention, the invention resides in the claims hereinafter appended.