Peaking amplifier frequency tuning
09853612 · 2017-12-26
Assignee
Inventors
- Michael Chen (Raleigh, NC, US)
- Steven M. Clements (Raleigh, NC)
- Mohak Chhabra (Cary, NC, US)
- Steven E. Mikes (Apex, NC, US)
- Hayden C. Cranford, Jr. (Cary, NC)
Cpc classification
H03F3/68
ELECTRICITY
H03F1/34
ELECTRICITY
International classification
Abstract
A circuit including: input and output nodes and first and second feedback nodes; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a capacitor connecting the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier with an input connected to the output node and an output connected to the first feedback node; a tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for varying a transconductance of the tunable feedback circuit and operational frequency of the peaking amplifier circuit.
Claims
1. A peaking amplifier circuit, comprising: an input node, an output node, a first feedback node, and a second feedback node; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a coupling capacitor connected between the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier in a negative feedback loop with an input connected to the output node and an output connected to the first feedback node; a tunable feedback amplifier in a negative feedback loop with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for varying a transconductance of the tunable feedback amplifier to adjust an operational frequency of the peaking amplifier circuit.
2. The peaking amplifier circuit of claim 1, wherein the tuning circuit applies a tuning voltage to the tunable feedback amplifier.
3. The peaking amplifier circuit of claim 2, wherein the tuning circuit applies the tuning voltage to a gate of a tail transistor in the tunable feedback amplifier.
4. The peaking amplifier circuit of claim 1, further comprising a series arrangement of a capacitor and a load impedance connected from the first feedback node to a source voltage.
5. The peaking amplifier circuit of claim 1, further comprising a tunable feedback amplifier in a positive feedback loop with an input connected to the output node and an output connected to the second feedback node.
6. The peaking amplifier circuit of claim 1, wherein the tuning circuit applies a tuning voltage to the tunable feedback amplifier in the positive feedback loop.
7. The peaking amplifier circuit of claim 6, wherein the tuning circuit applies the tuning voltage to a gate of a tail transistor in the tunable feedback amplifier in the positive feedback loop.
8. The peaking amplifier circuit of claim 2, wherein the tunable feedback amplifier in the negative feedback loop includes a plurality of tunable feedback amplifier cells, and wherein the tuning circuit selectively activates or deactivates at least one of the tunable feedback amplifier cells.
9. The peaking amplifier circuit of claim 8, wherein the tuning circuit selectively activates or deactivates at least one of the tunable feedback amplifier cells by applying the tuning voltage to a gate of a tail transistor in at least one of the tunable feedback amplifier cells.
10. The peaking amplifier circuit of claim 1, further comprising an integrated circuit including the peaking amplifier circuit.
11. A peaking amplifier circuit, comprising: an input node, an output node, a first feedback node, and a second feedback node; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a coupling capacitor connected between the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier in a negative feedback loop with an input connected to the output node and an output connected to the first feedback node; a capacitor and a load impedance in series connected from the first feedback node to a source voltage; a first tunable feedback amplifier in a negative feedback loop with an input connected to the output node and an output connected to the second feedback node; a second tunable feedback amplifier in a positive feedback loop with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for applying a first tuning voltage to the first tunable feedback amplifier and for applying a second tuning voltage to the second tunable feedback amplifier.
12. The peaking amplifier circuit of claim 11, wherein the tuning circuit applies the first tuning voltage to a gate of a tail transistor in the first tunable feedback amplifier.
13. The peaking amplifier circuit of claim 11, wherein the tuning circuit applies the second tuning voltage to a gate of a tail transistor in the second tunable feedback amplifier.
14. The peaking amplifier circuit of claim 11, wherein the first tunable feedback amplifier includes a plurality of tunable feedback amplifier cells, and wherein the tuning circuit selectively activates or deactivates at least one of the tunable feedback amplifier cells.
15. The peaking amplifier circuit of claim 14, wherein the tuning circuit selectively activates or deactivates at least one of the tunable feedback amplifier cells by applying the tuning voltage to a gate of a tail transistor in at least one of the tunable feedback amplifier cells.
16. The peaking amplifier circuit of claim 11, further comprising an integrated circuit including the peaking amplifier circuit.
17. A peaking amplifier circuit, comprising: a first input amplifier having an input connected to an input node and an output connected to a first feedback node; a second input amplifier having an input connected to the input node and an output connected to a second feedback node; a coupling capacitor connected between the first feedback node and the second feedback node; an amplifier with an input connected to the first feedback node and an output connected to an output node; an untuned feedback amplifier with an input connected to the output node and an output connected to the first feedback node; a first tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; a second tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for selectively applying a first tuning voltage to the first tunable feedback amplifier and a second tuning voltage to the second tunable feedback amplifier.
18. The peaking amplifier circuit of claim 17, wherein the untuned feedback amplifier is in a negative feedback loop, and wherein the first tunable feedback amplifier is in a negative feedback loop.
19. The peaking amplifier circuit of claim 17, wherein the second tunable feedback amplifier is in a positive feedback loop.
20. The peaking amplifier circuit of claim 17, further comprising an integrated circuit including the peaking amplifier circuit.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18) It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
DETAILED DESCRIPTION
(19) In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative. It is understood that the various process steps discussed herein can be implemented in the same manner and/or with slight modifications.
(20) Referring to
(21) The input of the amplifier D is connected to the feedback node 12, and the output of amplifier D is connected to an output node V.sub.Out of the peaking amplifier 10. The input of the feedback amplifier FB is connected to the output node V.sub.Out of the peaking amplifier 10, and the output of the feedback amplifier FB is connected to the feedback node 12. The feedback amplifier FB shares the load resistor R.sub.A with input amplifier A.
(22) The basic function of the peaking amplifier 10 is outlined as follows: The input amplifier A provides a relatively low transconductance g.sub.mA from V.sub.In to V.sub.1 (at the feedback node 12) at all frequencies, while the amplifier D provides a much higher transconductance (e.g., >10 g.sub.mA) from V.sub.1 to V.sub.Out. The feedback amplifier FB attempts to bring down the magnitude of V.sub.Out through a negative feedback loop. The feedback transconductance g.sub.mFB of the feedback amplifier FB is approximately equal to −g.sub.mA.
(23) The amplifier B provides a large transconductance g.sub.mB (e.g., also >10 g.sub.mA), which is AC coupled into the feedback node 12 through the coupling capacitor C. At low frequencies, g.sub.mB is isolated from the output. However, as the input frequency increases, the impedance of the coupling capacitor C drops, allowing g.sub.mB to overpower the negative feedback of the feedback amplifier FB, increasing the overall gain of the peaking amplifier 10. The peaking frequency of the peaking amplifier 10 may be controlled, for example, by adjusting the inductive components of load impedances Z.sub.B and Z.sub.D.
(24) The overall transfer function of the peaking amplifier 10 is given by the following equation:
(25)
Where:
G.sub.A=g.sub.mA.Math.R.sub.A
G.sub.B=g.sub.mB.Math.Z.sub.B
G.sub.D=g.sub.mD.Math.Z.sub.D
G.sub.FB=g.sub.mFB.Math.R.sub.A
(26) To better understand the peaking amplifier frequency tuning disclosed herein, let us consider the peaking amplifier 10 as a cascaded system as shown in
(27)
where
α=G.sub.D
and
(28)
Then, it follows that:
(29)
From this transfer function, the frequency of the dominant pole can be determined to be:
(30)
(31) It has been observed, in accordance with the above equation, that the operating frequency can be increased, and thus the frequency rolloff pushed higher, by increasing the G.sub.FB term, which is the product of g.sub.mFB and R.sub.A. Similarly, the operating frequency can be decreased, and thus the frequency rolloff pushed lower, by decreasing the G.sub.FB term. While R.sub.A may in some cases be difficult to adjust electrically, g.sub.mFB can be electrically adjusted, as presented in detail below and generally indicated by arrow 14 in
(32) One technique, for tuning the feedback stage S2 of the peaking amplifier 10, depicted in
(33)
Thus,
Higher g.sub.mFB.fwdarw.Higher ω.sub.p.fwdarw.Higher ω.sub.peak
and
Lower g.sub.mFB.fwdarw.Lower ω.sub.p.fwdarw.Lower ω.sub.peak.
(34) In a particular embodiment, the tail transistor in the feedback amplifier FB has a threshold voltage V.sub.t=˜290 mV. In this case, the peak frequency of the peaking amplifier 10 can continue to be adjusted with V.sub.Tune below this value, gradually cutting out the feedback path. Above a V.sub.Tune of ˜400 mV, the drain voltage cannot keep the input transistor in saturation, and performance suffers accordingly. Thus, in this example, a suitable tuning range for V.sub.Tune is set to approximately 190 mV-390 mV. For practical purposes, this tuning may be accomplished, for example, using a tunable current mirror. If mirrored through an identical device, the input current will vary from approximately 10 μA-50 μA.
(35) A chart of the frequency response of an illustrative peaking amplifier 10 with fine tuning according to embodiments is presented in
(36) The use of V.sub.Tune allows for a “fine” adjustment of the transconductance g.sub.mFB of the feedback amplifier FB. This fine tuning may be performed, for example, by adjusting the bias current (e.g., through V.sub.Tune) of the feedback amplifier FB which, as described above, results in a monotonic change in the transconductance g.sub.mFB. By varying the transconductance g.sub.mFB of the feedback amplifier FB in this manner, the pole of the feedback path can be adjusted as described above.
(37) According to other embodiments, as depicted in
(38) The switching of a feedback amplifier cell FB.sub.Cell into or out of the feedback stage S2 of the peaking amplifier 20 may be actuated using a switch 16 at the input of the feedback amplifier cell FB.sub.Cell as shown in
(39) To avoid issues related to the use of a switch 16 at the input of a feedback amplifier cell FB.sub.Cell, switching may be accomplished at the gate of the tail transistor in the feedback amplifier cell FB.sub.Cell. This is the same node in the feedback amplifier FB at which V.sub.Tune is applied for fine tuning. For example, as shown in
(40) The concepts of fine and coarse tuning in a frequency tunable peaking amplifier 40 can be combined into a single implementation as shown in
(41) Still referring to
(42) A chart of the frequency response of an illustrative peaking amplifier 40 with fine and coarse tuning according to embodiments is presented in
(43) A control circuit may be used in any of the embodiments of the frequency tunable peaking amplifiers 10, 20, 30, 40, 50 (described below), 60 (described below), and 70 (described below) disclosed herein to control the transconductance of the feedback stage S2 and adjust the operational frequency of the peaking amplifier. Other components of the control circuit may be included to provide control schemes for adjusting the value of the transconductance of the feedback stage S2. For example, a dynamic control scheme may be implemented, wherein the transconductance of the feedback stage S2 is dynamically adjusted under changing operating conditions. In particular, a control circuit can be employed to receive as input certain data regarding operating conditions, e.g., data rates, channel loss, etc., and then dynamically output a control signal (e.g., tuning voltage) to dynamically adjust the value of the transconductance of the feedback stage S2 to adjust the operational frequency of the peaking amplifier.
(44) It can be seen from
(45)
As evident from Equation 1, an increase in g.sub.mFB results in a corresponding increase in G.sub.FB (recall that G.sub.FB=g.sub.mFB.Math.R.sub.A), which results in a decrease in the overall gain of the peaking amplifier. While this is, of course, beneficial to the high frequency response, the variation in the DC gain attenuation may not be suitable for some applications. To this extent, additional embodiments of a peaking amplifier which counteract such a variation in DC gain attenuation are presented below.
(46) A frequency tunable peaking amplifier 50 for counteracting variations in DC gain attenuation according to embodiments is depicted in
(47) The input of the amplifier D is connected to the feedback node 12, while the output of amplifier D is connected to an output node V.sub.Out of the peaking amplifier 50. Load impedances Z.sub.B and Z.sub.D are present at the outputs of the input amplifier B and the amplifier D, respectively.
(48) Unlike the peaking amplifier 10, the peaking amplifier 50 includes an untuned, base feedback amplifier FB.sub.Base, which is always on, and a tunable feedback amplifier FB.sub.Tune. The tunable feedback amplifier FB.sub.Tune may be tuned using any of the tuning techniques detailed above (e.g., through adjustment of V.sub.Tune and/or variation in the number of feedback amplifier cells). The inputs of the base feedback amplifier FB.sub.Base and the tunable feedback amplifier FB.sub.Tune are connected to the output node V.sub.Out of the peaking amplifier 50. The output of the base feedback amplifier FB.sub.Base is connected to the feedback node 12. The output of the tunable feedback amplifier FB.sub.Tune is capacitively coupled to the feedback node 12 by a feedback coupling capacitor C.sub.FB and is further connected to a load impedance Z.sub.FB.
(49) The inclusion of the untuned, base feedback amplifier FB.sub.Base, tunable feedback amplifier FB.sub.Tune, coupling capacitor C.sub.FB, and load impedance Z.sub.FB in the peaking amplifier 50 results in a reduction of the variation in DC gain attenuation. A chart of the frequency response of an illustrative peaking amplifier 50 is presented in
(50) In the peaking amplifier 50, the coupling capacitor C.sub.FB capacitively couples the tunable feedback amplifier FB.sub.Tune to the feedback node 12. In addition, the load impedance Z.sub.FB keeps the tunable feedback amplifier FB.sub.Tune properly biased at DC. This configuration counteracts the DC gain variation and isolates DC shift from the feedback node 12. The peaking amplifier 50 provides a practically constant feedback factor at DC, due to the incorporation of the base feedback amplifier FB.sub.Base, reducing variation in the DC gain attenuation over the V.sub.Tune sweep. The DC operation of the forward amplification path in the peaking amplifier 50 is completely isolated, allowing for an expanded tuning range.
(51) Although the peaking amplifier 50 provides several advantages (e.g., deceased DC gain variation), such advantages do not come without the cost of additional components (e.g., coupling capacitor C.sub.FB and load impedance Z.sub.FB), as well as a gain rolloff at higher frequencies. To this extent, as depicted in
(52) A frequency tunable peaking amplifier 60 for counteracting variations in DC gain attenuation according to embodiments is depicted in
(53) The input of the amplifier D is connected to the feedback node 12, and the output of amplifier D is connected to an output node V.sub.Out of the peaking amplifier 60. Load impedances Z.sub.B and Z.sub.D are present at the outputs of the input amplifier B and the amplifier D, respectively.
(54) The peaking amplifier 60 further includes an untuned, base feedback amplifier FB.sub.Base, which is always on, and a tunable feedback amplifier FB.sub.Tune. The tunable feedback amplifier FB.sub.Tune may be tuned using any of the tuning techniques detailed above (e.g., through adjustment of V.sub.Tune and/or variation in the number of feedback amplifier cells). The inputs of the base feedback amplifier FB.sub.Base and the tunable feedback amplifier FB.sub.Tune are connected to the output node V.sub.Out of the peaking amplifier 60. The output of the base feedback amplifier FB.sub.Base is connected to the feedback node 12. The output of the tunable feedback amplifier FB.sub.Tune is coupled to the output of the input amplifier B and is capacitively coupled to the output of the amplifier A by the coupling capacitor C.
(55) A chart of the frequency response of an illustrative peaking amplifier 60 is presented in
(56) Similar to the peaking amplifier 50, the peaking amplifier 60 provides a constant feedback factor at DC, due to the incorporation of the base feedback amplifier FB.sub.Base, reducing variation in the DC gain attenuation over the V.sub.Tune sweep. Unlike the peaking amplifier 50, however, fewer additional capacitors or loads are needed in the peaking amplifier 60. There is less peak loss at high frequencies; gain increases as the frequency increases. The peaking amplifier 60 has a slightly reduced tuning range compared to the peaking amplifier 50.
(57)
(58) The peaking amplifier 70 includes an input amplifier A, an input amplifier B, and an amplifier D. The input amplifiers A and B have inputs that are commonly connected to an input voltage V.sub.In. The output of the input amplifier A is connected to a feedback node 12. The output of the input amplifier B is connected to a feedback node 22 and is capacitively coupled to the output of the amplifier A by a coupling capacitor C.sub.1. The output of the input amplifier A is connected to a load impedance Z.sub.A. Further, the output of the input amplifier A is connected to a series arrangement of a feedback coupling capacitor C.sub.FB and a load impedance Z.sub.FB, which is connected to a source voltage.
(59) The input of the amplifier D is connected to the feedback node 12, while the output of amplifier D is connected to an output node V.sub.Out of the peaking amplifier 70. Load impedances Z.sub.B and Z.sub.D are present at the outputs of the input amplifier B and the amplifier D, respectively.
(60) Similar to the peaking amplifier 50 (
(61) Unlike the previously disclosed frequency tunable peaking amplifiers, the peaking amplifier 70 also includes a tunable feedback amplifier FB.sub.Pos, which is included in a positive feedback loop extending from V.sub.Out to the output of the tunable feedback amplifier FB.sub.Tune at feedback node 22. The tunable feedback amplifier FB.sub.Pos may be tuned using any of the tuning techniques detailed above (e.g., through adjustment of V.sub.Tune2 and/or variation in the number of feedback amplifier cells).
(62) The tunable feedback amplifier FB.sub.Tune in the peaking amplifier 70 is AC coupled to the feedback node 12 by the coupling capacitor C.sub.1. This configuration reduces the variation in DC gain attenuation for the peaking amplifier 70. This configuration also eliminates common mode shift at the output caused by the g.sub.m tuning. In order to maintain a moderate level of DC gain attenuation, the untuned, base feedback amplifier FB.sub.Base is connected to the output of the input amplifier A (at the feedback node 12) in a negative feedback configuration. By leaving the feedback coupling capacitor C.sub.FB and the load impedance Z.sub.FB in the peaking amplifier 70, the load degradation through the capacitor C.sub.FB counteracts any gain increase at the output of the input amplifier B. This requires a relatively large capacitor C.sub.FB.
(63)
(64) It can be seen that the tuning range of the peaking amplifier 70 (without the tunable feedback amplifier FB.sub.Pos) is slightly reduced compared to some of the above-described frequency tunable peaking amplifiers. This is due to the inclusion of the base feedback amplifier FB.sub.Base in the peaking amplifier 70, which limits the bottom end of the tuning range. To this extent, as shown in
(65)
(66) Numerous embodiments of peaking amplifiers 10, 20, 30, 40, 50, 60, and 70 are disclosed herein, each having particular operational characteristics. Advantageously, one shared characteristic is a multi-GHz tuning range rather than a single frequency as provided by known peaking amplifiers. Additional advantages of each embodiment are described in detail above.
(67) Further aspects of the present disclosure provide tunable peaking amplifiers which can be utilized in integrated circuit chips with various analog and digital integrated circuitries. For example, integrated circuit dies can be fabricated having peaking amplifiers and other semiconductor devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, resistors, capacitors, inductors, etc., forming analog and/or digital circuits. The peaking amplifiers can be formed upon or within a semiconductor substrate. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings provided above, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of described herein.
(68) The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.
(69) Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate, for example +/−10% of the stated value(s).
(70) Spatially relative terms, such as “inner,” “outer,” “beneath,” “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
(71) The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the disclosure as defined by the accompanying claims.
(72) The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.