Method of Vernier digital-to-analog conversion

Abstract

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

Claims

1. A method of Vernier digital-to-analog conversion, the method comprising: performing a conversion of a reference signal Y using a control code X=M+a.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and a.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein a≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code ofM±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

2. The method according to claim 1, wherein algebraic summing of the control code M and the resulting digital code N to a formula Q=M−N is an arithmetic summing thereof, and conversion of the analog signals Z.sub.1 and Z.sub.2 is performed by subtracting thereof, wherein the reference signal Y.sub.2 is generated in accordance with an expression: Y.sub.2=Y.sub.1(1−a.sup.−α).

3. The method according to claim 1, wherein algebraic summing the control code M and the resulting digital code N according to a formula Q=M−N is an arithmetic subtraction thereof, and conversion of the analog signals Z.sub.1 and Z.sub.2 is performed by summing thereof, wherein the reference signal Y.sub.2 is generated in accordance with an expression: Y.sub.2=Y.sub.1(1+a.sup.−α).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings:

(2) Fig. 1 shows a digital-to-analog converter (DAC) known from the prior art:

(3) FIG. 2 shows a parallel digital-to-analog converter and method using the DAC as shown in FIG. 1. known from the prior art: and

(4) FIG. 3 shows a Vernier digital-to-analog converter and method.

DETAILED DESCRIPTION

(5) FIG. 3 is a block diagram of one possible embodiment of the proposed method of building a Vernier digital-to-analog converter showing an arithmetic adder 6, to the corresponding inputs of which α of high-order bits and β of lower-order bits of the control code X arrive, wherein the lower-order a.sup.−αN bits were previously digitally multiplied a.sup.α times (left shift by a bits) using a digital multiplier 7.

(6) FIG. 3 also shows a reference signal Y.sub.1 source 8, a reference signal Y.sub.2 source 9, a DAC_10, an analog adder 11, and a DAC_12. An output bus of the arithmetic adder 6 is connected to a corresponding input control bus of the DAC_10, and the other input of the DAC_10 is connected to an output of the reference signal Y.sub.1 source 8. An output of the DAC_10 is connected to a corresponding input of the analog adder 11, and the other input of the adder 11 is connected to an output of the DAC_12. The a.sup.−αN low-order bits of the control code X are fed to a control input bus of the DAC_12, subjected to the digital multiplication a.sup.α times (left shift by α bits) using the digital multiplier 7. The other input of the DAC_12 is connected to the output of the reference signal Y.sub.2 source 9. An output analog signal Z.sub.0 is obtained at the output of the analog adder 11.

(7) In this embodiment, the proposed method of the Vernier digital-to-analog converter structure operates as follows.

(8) The input buses of the arithmetic adder 6 and of the digital multiplier 7 receive α high-order bits and β low-order bits of the control code X, respectively, being the control code M and the control code a.sup.−αN, respectively. The β lower-order bits are multiplied a.sup.α times in the digital multiplier 7 resulting in the control code N, which is fed to the second input bus of the digital arithmetic adder 6 and to the input bus of the DAC_12. The reference signal Y.sub.2=Y.sub.1(1±a.sup.−α) is also fed to the input of the DAC_12, wherein in the arithmetic adder 6, algebraic summation (arithmetic summing with account for the sign) of the α high-order bits and the β of lower-order bits of the number X obtained after a.sup.α times β multiplication is performed in accordance with the formula Q=M N, and the summation result comes to the input control bus of the DAC_10. The reference signal Y.sub.1 is also fed to the input of the DAC_10. A digital code Q in the DAC_10 is converted from the reference signal Y.sub.1 to the analog signal Z.sub.1, and the digital code N in the DAC_12 is converted from the reference signal Y.sub.2 to the analog signal Z.sub.2.

(9) The analog adder 11 sums the converted analog signals Z.sub.1 and Z.sub.2, coming to the corresponding inputs of the analog adder 11, resulting in the analog output signal Z.sub.0.

(10) As a numerical example, a conversion of a decimal number X.sub.(10).Math.(M+10.sup.−1N).sub.(10) to an abstract analog parameter Z is provided below.

(11) Since the number system is decimal, the two-digit numerical code X.sub.(10) is divided into two single-digit ones (M and N) and the reference signals Y.sub.1 and Y.sub.2 will take the form of: Y.sub.1=1.0; Y.sub.2=1.1×Y.sub.1.

EXAMPLES

(12) There are two characteristic options: for the case M.sub.1>N and for the case M.sub.2<N. Let M.sub.1=8 and M.sub.2=3, and N takes values from 0 to 9. Calculation and conversion steps are set forth in Table 1 and Table 2 provided below.

(13) TABLE-US-00001 TABLE 1 M.sub.1 N M.sub.1 − N Y.sub.1 × (M1 − N) Y.sub.2 × N Z.sub.0 8 0 8 8 0.0 8.0 8 1 7 7 1.1 8.1 8 2 6 6 2.2 8.2 8 3 5 5 3.3 8.3 8 4 4 4 4.4 8.4 8 5 3 3 5.5 8.5 8 6 2 2 6.6 8.6 8 7 1 1 7.7 8.7 8 8 0 0 8.8 8.8 8 9 −1 −1 9.9 8.9 Y.sub.2 = 1.1 × Y.sub.1

(14) TABLE-US-00002 TABLE 2 M.sub.2 N M.sub.2 − N Y.sub.1 × (M.sub.2 − N) Y.sub.2 × N Z.sub.0 3 0 3 3 0.0 3.0 3 1 2 2 1.1 3.1 3 2 1 1 2.2 3.2 3 3 0 0 3.3 3.3 3 4 −1 −1 4.4 3.4 3 5 −2 −2 5.5 3.5 3 6 −3 −3 6.6 3.6 3 7 −4 −4 7.7 3.7 3 8 −5 −5 8.8 3.8 3 9 −6 −6 9.9 3.9 Y.sub.2 = 1.1 × Y.sub.1

(15) The only elements that are critical to strict accuracy insurance requirements for nodes of the Vernier DAC (FIG. 3) are the output analog adder 11 and the reference signals Y.sub.1 source 8 and Y.sub.2 source 9, respectively. However, corresponding implementation problems are not insurmountable, moreover, they are conventional for (high) precision electronics.

(16) So, for example, with a twenty-bit input binary code (α=β=10) and Y.sub.1=10V, the required relative accuracy of the analog adder 11 and of the source 8 of a reference signal is δ.sub.a≤2.sup.−20≈10.sup.−6 (absolute accuracy—9.5 mV), which is quite feasible on modern element base.

(17) In case of Y.sub.2=0.9×Y.sub.1 and of the same numerical parameters, the following results are obtained:

(18) TABLE-US-00003 TABLE 3 M N M + N Y.sub.1 × (M + N) Y.sub.2 × N Z.sub.0 8 0 8 8 0.0 8.0 8 1 9 9 0.9 8.1 8 2 10 10 1.8 8.2 8 3 11 11 2.7 8.3 8 4 12 12 3.6 8.4 8 5 13 13 4.5 8.5 8 6 14 14 5.4 8.6 8 7 15 15 6.3 8.7 8 8 16 16 7.2 8.9 8 9 17 17 8.1 8.9 Y.sub.2 = 0.9 × Y.sub.1

(19) TABLE-US-00004 TABLE 4 M N M + N Y.sub.1 × (M + N) Y.sub.2 × N Z.sub.0 3 0 3 3 0.0 3.0 3 1 4 4 0.9 3.1 3 2 5 5 1.8 3.2 3 3 6 6 2.7 3.3 3 4 7 7 3.6 3.4 3 5 8 8 4.5 3.5 3 6 9 9 5.4 3.6 3 7 10 10 6.3 3.7 3 8 11 11 7.2 3.8 3 9 12 12 8.1 3.9 Y.sub.2 = 0.9 × Y.sub.1

(20) It should also be noted that in both of the above-mentioned cases, a digit capacity of the first DAC_10 should be greater by one than the digit capacity of the second DAC_12, in other words, with the equal digit capacity of the DAC_10 and the DAC_12 a length β of the control code N and of the code X.sub.02=N−1. As a result, when using the two DACs of equal digit capacity β (and the accuracy a.sup.−1), the resulting accuracy will not be better than δ≥(β−1).sup.−1, which, in general, is not so bad as it seems.

(21) Table 5 shows the results of selective checking of the first conversion algorithm for a four-digit decimal number.

(22) TABLE-US-00005 TABLE 5 Y.sub.2 = 1.01 × Y.sub.1 Q.sub.1 = Z.sub.1 = Z.sub.2 = Z.sub.0 = X.sub.1 X.sub.2 X.sub.3 X.sub.4 X.sub.1 X.sub.2 − X.sub.3X.sub.4 Y.sub.1 × X.sub.1X.sub.2 Y.sub.2 × X.sub.3X.sub.4 Z.sub.1 + Z.sub.2 8 0 0 0 80 80 0.00 80.00 8 1 0 2 79 79 2.02 81.02 8 2 0 4 78 78 4.04 82.04 8 3 0 1 82 82 1.01 83.01 8 4 0 3 81 81 3.03 84.03 8 5 0 6 79 79 6.06 85.06 8 6 0 8 78 78 8.08 86.08 8 7 0 5 82 82 5.05 87.05 8 8 0 7 81 81 7.07 88.07 8 9 0 9 80 80 9.09 89.09 8 3 4 7 36 36 47.47 83.47 8 3 1 6 67 67 16.16 83.16 8 3 2 6 57 57 26.26 83.26 8 3 3 6 47 47 36.36 83.36 8 3 4 6 37 37 46.46 83.46 8 3 5 6 27 27 56.56 83.56 8 3 6 6 17 17 66.66 83.66 8 3 7 6 7 7 76.76 83.76 8 3 8 6 −3 −3 86.86 83.86 8 3 9 6 −13 −13 96.96 83.96

(23) The last question is the unequal digit capacity of N and M for (N+M)=1 (mod 2), i.e., for X odd, namely, the case M=N−1. The following tables 6 and 7 show further results of the first and second conversions.

(24) TABLE-US-00006 TABLE 6 Q.sub.1 = X.sub.1 X.sub.2 X.sub.3 X.sub.1 − X.sub.2X.sub.3 Z.sub.1 = Y.sub.1 × Q.sub.1 Z.sub.2 = Y.sub.2 × Q.sub.2 Z.sub.0 = Z.sub.1 + Z.sub.2 8 0 0 8 8 0.00 8.00 8 0 1 7 7 1.01 8.01 8 1 2 −4 −4 12.12 8.12 8 1 3 −5 −5 13.13 8.13 8 2 4 −16 −16 24.24 8.24 8 2 5 −17 −17 25.25 8.25 8 3 6 −28 −28 36.36 8.36 8 3 7 −29 −29 37.37 8.37 8 4 8 −40 −40 48.48 8.48 8 4 9 −41 −41 49.49 8.49 etc

(25) TABLE-US-00007 TABLE 7 Q.sub.1 = Z.sub.2 = Y.sub.2 × Q.sub.2 X.sub.1 X.sub.2 X.sub.3 X.sub.1 + X.sub.2X.sub.3 Z.sub.1 = Y.sub.1 × Q.sub.1 (Q.sub.2 = X.sub.2X.sub.3) Z.sub.3 = Z.sub.1 − Z.sub.2 3 0 0 3 3 00.00 3.00 3 0 1 4 4 00.99 3.01 3 1 2 15 15 11.88 3.12 3 1 3 16 16 12.87 3.13 3 2 4 27 27 23.76 3.24 3 2 5 28 28 24.75 3.25 3 3 6 39 39 35.64 3.36 3 3 7 40 40 36.63 3.37 3 4 8 51 51 47.52 3.48 3 4 9 52 52 48.51 3.49

(26) The proposed conversion method with any ratio of the numbers N and M, concedes only one bit loss and provides an increasing of the digital-to-analog conversion accuracy by≈a.sup.α-1 times, because a errors are significantly reduced, which means that a parallel digital-to-analog conversion accuracy increases without tightening the requirements for the manufacturing technology of DAC elements.

(27) The attention shall be drawn again to the following: for any digital-to-analog conversion method (double or more integration, sigma-delta, conveyor, sequential approximation, Vernier, etc.), the accuracy requirements for analog nodes are determined only by the required conversion accuracy.

(28) The weight contribution of individual analog elements of the digital-to-analog converter implementing the proposed method to the budget of permissible errors of a whole device depends on a specific circuitry implementation. Certainly, a well-known rule is also applied: the stricter are the conversion accuracy requirements, the stricter (at least linearly) are the analog node requirements.

(29) The requirements for accuracy and stability of sources of reference voltages (currents) and analog algebraic adders of input/output voltages (currents) are invariant to the selected conversion method, and their contribution is small.

(30) The main contribution to the errors makes a DAC itself, (explicitly or implicitly) presenting in a structure of Vernier digital-to-analog conversion, due to errors of current/voltage switches and R(C) matrices.

(31) Using identical resistors allows significant accuracy improvement in comparison with a conventional weighting DAC because a set of precision elements with identical parameters is relatively easy to produce. A DAC of R-2R type allows to reduce, but not to remove, the restrictions on digit capacity. With a laser adjustment of film resistors arranged on same substrate of the hybrid IC, a DAC accuracy of 20-22 bits can be achieved.

(32) Therefore, in practice important is to abate the requirements for the DAC (by reducing of required number ψ of the control code X bits) along with maintaining final conversion accuracy.

(33) Exemplary elements realizing the proposed conversion method shown in the block diagram are as follows.

(34) The arithmetic adder 6 can be implemented on the integrated circuits of the arithmetic adder 555(SN7483) or on the integrated circuits of the arithmetic device 1533Π3.

(35) An integrated circuit of double DAC AD5763 can be used as the DAC 10 and 12.

(36) The reference signals sources 8 and 9 can be provided on integrated circuits LT6657 (precision voltage source) or LT3092 (precision current source).

(37) Integrated circuits of the shift registers—universal registers 15338 (SN74HC164) can be used for digital multiplying the N lower-order bits of the control code X by α times (left shift by a bits).