Interrupt handling method, computer system, and non-transitory storage medium that resumes waiting threads in response to interrupt signals from I/O devices

Abstract

The present invention provides an interrupt handling system for handling interrupts in a computer system is provided. The interrupt handling system captures and processes the interrupts in a user space of the computer system. The present invention also provides for an interrupt registration method that facilitates interrupt handling in the user space during porting of user applications from one platform to another.

Claims

1. An interrupt handling method for a computer system to execute an interrupt handling program on a second platform, the interrupt handling program being created on a first platform, the method comprising: storing an interrupt number and corresponding interrupt service routine in a memory of the computer system, wherein the interrupt number corresponds to an input/output device coupled with the computer system; determining a user space input/output device number on a basis of the interrupt number, wherein the user space input/output device number corresponds to the input/output device; determining a memory location of the input/output device on the basis of the determined user space input/output device number; initiating the input/output device for reading, on the basis of the determined memory location; creating a thread corresponding to the input/output device; and placing the thread in a wait state for receiving an interrupt signal from the input/output device, wherein the interrupt signal corresponds to an interrupt generated by the input/output device; receiving the interrupt signal from the input/output device; executing the interrupt service routine in a kernel space within the memory in response to receiving the interrupt signal; resuming the thread from wait state on the basis of the interrupt service routine; and executing a user-defined function corresponding to the interrupt signal, in a user space within the memory.

2. The interrupt handling method as claimed in claim 1, further comprising placing the thread in the wait state for receiving another interrupt signal from the input/output device subsequent to executing the user-defined function corresponding to the interrupt signal.

3. The interrupt handling method as claimed in claim 1, further comprising: incrementing an interrupt event counter subsequent to receiving the interrupt signal from the input/output device; and resetting the interrupt event counter subsequent to executing the user-defined function corresponding to the interrupt signal.

4. The interrupt handling method as claimed in claim 1, further comprising creating a separate thread for every interrupt.

5. The interrupt handling method as claimed in claim 1, wherein the step of receiving the interrupt signal from the input/output device includes receiving the interrupt signal corresponding to the input/output device through an interrupt controller.

6. The interrupt handling method as claimed in claim 1, wherein the thread is assigned highest priority, thereby reducing latency.

7. A computer system including a memory storing instructions and having a user space and a kernel space, and a computing device coupled with the memory, the computing device comprising a processor which executes the instructions which cause the computing device to: store an interrupt number and corresponding interrupt service routine in the memory, wherein the interrupt number corresponds to an input/output device coupled with the computer system; determine a user space input/output device number on a basis of the interrupt number, wherein the user space input/output device number corresponds to the input/output device; determine a memory location of the input/output device on the basis of the determined user space input/output device number; initiate the I/O device for reading, on the basis of the determined memory location; create a thread corresponding to the input/output device; place the thread in a wait state to receive an interrupt signal from the input/output device, wherein the interrupt signal corresponds to an interrupt generated by the input/output device; receive the interrupt signal from the input/output device; execute the interrupt service routine in the kernel space in response to receiving the interrupt signal; resume the thread from wait state on the basis of interrupt service routine; and execute a user-defined function corresponding to the interrupt signal, in the user space.

8. The computer system as claimed in claim 7, wherein the computing device is further configured to place the thread in the wait state for receiving another interrupt signal from the input/output device subsequent to executing the user-defined function corresponding to the interrupt signal.

9. The computer system as claimed in claim 7, wherein the computing device is further configured to: increment an interrupt event counter subsequent to receiving the interrupt signal from the input/output device, and reset the interrupt event counter subsequent to executing the user-defined function corresponding to the interrupt signal.

10. The computer system as claimed in claim 7, wherein the computing device is further configured to create a separate thread for every interrupt.

11. The computer system as claimed in claim 7, wherein the interrupt signal is received from the input/output device by way of an interrupt controller.

12. The computer system as claimed in claim 7, wherein the thread is assigned highest priority, thereby reducing latency.

13. A non-transitory storage medium storing a program for causing a computer system including a computing device to execute an interrupt handling program on a second platform, the interrupt handling program being created on a first platform, wherein the program causes the computing device to perform the operations of: storing an interrupt number and corresponding interrupt service routine in a memory coupled with the computing device, wherein the interrupt number corresponds to an input/output device coupled with the computer system; determining a user space input/output device number on a basis of the interrupt number, wherein the user space input/output device number corresponds to the input/output device; determining a memory location of the input/output device on the basis of the determined user space input/output device number; initiating the input/output device for reading, on the basis of the determined memory location; creating a thread corresponding to the input/output device; placing the thread in a wait state for receiving an interrupt signal from the input/output device, wherein the interrupt signal corresponds to an interrupt generated by the input/output device; receiving the interrupt signal from the input/output device; executing the interrupt service routine in a kernel space within the memory in response to receiving the interrupt signal; resuming the thread from wait state on the basis of the interrupt service routine; and executing a user-defined function corresponding to the interrupt signal, in a user space within the memory.

14. The storage medium as claimed in claim 13, wherein the program causes the computing device to further perform an operation of placing the thread in the wait state for receiving another interrupt signal from the input/output device subsequent to executing the user-defined function corresponding to the interrupt signal.

15. The storage medium as claimed in claim 13, wherein the program causes the computing device to further perform an operation of creating a separate thread for every interrupt.

16. The storage medium as claimed in claim 13, wherein the program causes the computing device to further perform operations of: incrementing an interrupt event counter subsequent to receiving the interrupt signal from the input/output device; and resetting the interrupt event counter subsequent to executing the user-defined function corresponding to the interrupt signal.

17. The storage medium as claimed in claim 13, wherein the operation of receiving the interrupt signal from the input/output device includes receiving the interrupt signal corresponding to the input/output device through an interrupt controller.

18. The storage medium as claimed in claim 13, wherein the thread is assigned highest priority, thereby reducing latency.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 illustrates a schematic block diagram of a computer implemented interrupt handling system according to an embodiment of the present invention.

(2) FIG. 2 is a flowchart illustrating a method of handling interrupts in a computer system according to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

(3) The detailed description is described with reference to the accompanying figures. Same numbers are used throughout the drawings to reference like features and modules.

(4) It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

(5) The various embodiments of the present invention provide a computer implemented system and a method of handling interrupts.

(6) In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details.

(7) One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems. However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.

(8) Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.

(9) References in the present disclosure to “one embodiment” or “an embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

(10) The present invention provides a computer system and a method of handling interrupts.

(11) Referring now to FIG. 1, a computer implemented interrupt handling system (100) is shown in accordance with an embodiment of the present invention. The computer implemented interrupt handling system (100) includes a computer system (102), a plurality of input/output (I/O) devices (104) including first and second I/O devices (104a and 104b) (also referred singularly as “I/O device (104)”), and an interrupt controller (106). The computer system (102) includes a processor (108) and a memory (110). The memory (110) includes a user space (112) and a kernel space (114).

(12) It will be apparent to a person of ordinary skill in the art that the computer system (102) is not limited to the processor (108) and the memory (110) and may include additional electronic components which are not depicted in FIG. 1 for simplicity.

(13) The I/O devices (104) include peripheral devices connected to the computer system (102). Examples of the I/O devices (104) include input devices such as a keyboard and output devices such as a display device. In an example, the first I/O device (104a) is directly connected to the computer system (102) and the second I/O system (104b) is connected to the computer system (102) by way of the interrupt controller (106). Therefore, it will be apparent to a person of ordinary skill in the art that the interrupt handling system (100) of the present invention is equally operative with various types of direct and indirect connection between the computer system (102) and the I/O devices (104). Further, the interrupt handling system (100) of the present invention is equally operative with or without the presence of the interrupt controller (106).

(14) Each I/O device (104) generates an interrupt which must be serviced by the computer system (102). Hence, each I/O device (104) generates corresponding interrupt signal and transmits the interrupt signal to the computer system (102). Each interrupt is identified using corresponding interrupt number.

(15) The computer system (102) converts a first program created on a first platform into a second program executable on a second platform. Examples of the first program created on the first platform include user applications created on platforms such as VxWorks. Examples of the second program executable on the second platform include user applications executable on operating systems such as Linux. In another example, the first and second programs are different types of user applications executable by the processor (108).

(16) The computer system (102) includes an emulation layer that converts the first program into the second program. The emulation layer includes an interrupt registration Application Programming Interface (API), operating system (OS) libraries, and an OS mechanism. The OS libraries provide conventional in-built functions for handling interrupts in the computer system (102).

(17) In an embodiment of the present invention, a novel interrupt registration API is provided. During initiation of the interrupt registration API, the interrupt numbers corresponding to the interrupt signals of the I/O devices (104) are stored in the memory (110). Further, interrupt service routine (ISR) handlers corresponding to the interrupt signals are also stored in the memory (110). In an exemplary embodiment, the memory (110) stores a look-up table that includes the interrupt numbers corresponding to the interrupt signals, and the ISR corresponding to the interrupt numbers.

(18) The processor (108) determines user space input/output (UIO) numbers corresponding to the interrupt numbers and stores the UIO numbers in the memory (110). In an exemplary embodiment, the processor (108) stores the UIO numbers in the look-up table stored in the memory (110). Thereafter, the processor (108) determines memory locations of the I/O devices (104) based on the UIO numbers. The processor (108) initiates the I/O devices (104) for reading based on the memory locations.

(19) The processor (108) creates a separate thread for every I/O device (104), i.e., every I/O device (104) has a dedicated thread for receiving interrupt signals generated by that I/O device (104). The processor (108) places the threads in wait state for receiving the interrupt signals from corresponding I/O devices (104).

(20) When the computer system (102) receives an interrupt signal from the I/O device (104), the processor (108) executes the ISR corresponding to the thread in the kernel space (114). The processor (108) also increments an event counter after receiving the interrupt signal from the I/O device (104). The thread corresponding to the interrupt signal is resumed from the wait state by the processor (108) during the execution of the ISR. After the thread is resumed from the wait state, the thread causes the processor (108) to execute a user-defined function corresponding to the interrupt signal which is stored and executed in the user space (112). When the execution of the user-defined function is completed, the processor (108) places the thread in wait state to receive any further interrupt signals from the I/O device (104). The processor (108) also resets the event counter after executing the user-defined function. The event counter is used to track missed events while debugging the computer system (102).

(21) In an embodiment, the computer system (102) of the present invention implements priority boosting mechanism that ensures immediate execution of the ISR function after receiving the interrupt signal from the I/O device (104).

(22) Generally, real-time computer systems implement a First-In-First-Out (FIFO) scheduler for executing multiple tasks. Each task is assigned a priority which ranges, for example, between 0-99; 0 being the least priority and 99 being the highest priority. Hence, the computer systems execute the tasks having the priority of 99 before the tasks having the priority of 0. The computer systems also allow the user to assign the priority between 0-99 to any user-defined task.

(23) The priority boosting mechanism of the computer system (102) of the present invention offers technical improvement over the priority scheme explained in the above paragraph by providing a priority of 100 to the thread corresponding to the interrupt signal. Since the thread corresponding to the interrupt signal is allotted the priority of 100, the ISR function is executed immediately and without any latency. Hence, the priority boosting mechanism greatly improves the efficiency of the computer system (102).

(24) Referring now to FIG. 2, a flowchart illustrating a method of handling interrupts is shown according to an embodiment of the present invention. The flowchart is explained below with reference to the computer implemented interrupt handling system (100) of FIG. 1.

(25) At step 202, the first program which is created on the first platform is provided at the computer system (102).

(26) At step 204, the first program is converted into the second program executable on the second platform.

(27) At step 206, the processor (108) stores the interrupt numbers and the ISR corresponding to the interrupts generated by the I/O devices (104) in the memory (110).

(28) At step 208, the processor (108) determines the UIO device numbers corresponding to the interrupt numbers.

(29) At step 210, the processor (108) determines the memory locations of the I/O devices (104) based on the UIO numbers.

(30) At step 212, the processor (108) initiates the I/O devices for reading.

(31) At step 214, the processor (108) creates the threads corresponding to the I/O devices (104).

(32) At step 216, the processor (108) restores the priorities of the threads corresponding to the I/O devices (104).

(33) At step 218, the processor (108) places the threads in wait state for receiving corresponding interrupt signals from the I/O devices (104).

(34) At step 220, the computer system (102) receives the interrupt signal from the I/O device (104).

(35) At step 222, the processor (108) executes the ISR corresponding to the received interrupt signal in the kernel space (114).

(36) At step 224, the processor (108) boosts the priority of the thread corresponding to the received interrupt signal.

(37) At step 226, the processor (108) resumes the thread from the wait state.

(38) At step 228, the processor (108) executes the user-defined function corresponding to the received interrupt signal in the user space (112).

(39) In operation, the computer implemented interrupt handling system (100) depicted in FIG. 1 and the method of handling the interrupts (202-228) depicted in FIG. 2 include converting the first program created on the first platform (for e.g. VxWorks) into the second program executable on the second platform (for e.g. Linux). Further, the novel interrupt registration API of the present invention stores the interrupt numbers corresponding to the interrupt signals of the I/O devices (104) in the memory (110). The processor (108) determines the UIO numbers corresponding to the interrupt numbers and stores the UIO numbers in the memory (110). Thereafter, the processor (108) determines the memory locations of the I/O devices (104) based on the UIO numbers and initiates the I/O devices (104) for reading. The processor (108) creates the threads for the I/O devices (104) and places the threads in wait state for receiving the interrupt signals from corresponding I/O devices (104).

(40) When the computer system (102) receives the interrupt signal from the I/O device (104), the processor (108) executes the ISR corresponding to the thread in the kernel space (114) and increments the event counter. Thereafter, the thread corresponding to the interrupt signal is resumed from the wait state by the processor (108) during the execution of the ISR. After the thread is resumed from the wait state, the thread causes the processor (108) to execute the user-defined function corresponding to the interrupt signal which is stored and executed in the user space (112) with boosted priority. Thereafter, the processor (108) places the thread in wait state to receive any further interrupt signals from the I/O device (104) and resets the event counter and restores the priority.

(41) Advantageously, the interrupt registration API of the present invention facilitates the execution of the user-defined functions in the user space instead of the kernel space. Therefore, even after the first program is converted into the second program, the interrupts are handled in the user space instead of the kernel space. This facilitates direct porting of user applications made on platforms such as VxWorks to platforms such as Linux, without requiring any change in the interrupt calls of the user applications.

(42) The interrupt registration API of the present invention facilitates the mapping of the peripheral devices into user space by way of memory mapping. This enables the interrupt registration API of the present invention to directly capture event data, such as occurrence of interrupts, into user space instead of kernel space. This is an immense technical improvement over the conventional interrupt handling systems which capture the event data in the kernel space and then transfer the data into the user space. Hence, the latency caused in the conventional interrupt handling systems due to transfer of the event data from the kernel space to the user space is avoided in the interrupt registration API of the present invention, thereby improving the efficiency of the computer system and providing enhanced interrupt handling in the user space. Since the event data is captured in the user space and the ISR functions are also stored and implemented in the user space, there is no need for users to re-define the user-defined functions even when the kernel is upgraded. This enables the user to upgrade the kernel without requiring changing the ISR functions.

(43) Further, the interrupt registration API of the present invention reduces the latency incurred in reception of the interrupt signal and execution of the ISR function, which improves the efficiency of the computer system. Reduced latency enables the computer system to perform real-time functions efficiently and with deterministic latency.

(44) In conventional systems for porting the user applications from one platform to another, the ISR function is split into two parts such that the event capturing is executed in the kernel space and the event processing is executed in the user space. Contrary to such conventional systems, the interrupt registration API of the present invention does not require the ISR to be split into two during the porting of the user application. Therefore, the interrupt registration API of the present invention allows easier and faster porting of user applications from one platform to another, which reduces the complexity of the process of porting and enhances the efficiency of the computing system.

(45) Moreover, the priority boosting mechanism implemented by the interrupt handling system of the present invention enables immediate execution of the ISR functions which further reduces the latency of the computer system.

(46) The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.

(47) It will be apparent to one of the ordinary skill in the art that many modifications, improvements and sub-combinations of the various embodiments, adaptations and variations can be made to the invention without departing from the scope thereof as claimed in the following claims.

REFERENCE SIGNS LIST

(48) 100 computer implemented interrupt handling system, 102 computer system, 104a first I/O device, 104b second I/O device, 106 interrupt controller, 108 processor, 110 memory, 112 user space, 114 kernel space