METHOD OF PRODUCING A FUNCTIONAL INLAY AND INLA PRODUCED BY THE METHOD

Abstract

The method of manufacturing a functional inlay, comprises at least the steps of: (1) providing a substrate (7) with a wire antenna embedded therein and with an aperture (6) wherein two wire antenna portions (4,5) are positioned over said aperture (6); (2) acquiring the positions and the dimensions of said wire antenna portions (4,5) and of said aperture (6); (3) determining If the acquired positions and dimensions meet predetermined tolerances; (4) if the acquired dimensions and positions meet said tolerances, then placing a chip (1) in fie aperture (6) so that said wire portions (4,5) are positioned over connections pads (2,3) of said chip (1) and then bonding said wire portions (4,5) to said connection pads (2,3).

Claims

1. A method of manufacturing a functional inlay, comprising at least the steps of: (1) providing a substrate with a wire antenna embedded therein and with an aperture wherein two wire antenna portions are positioned over said aperture; (2) acquiring the positions and the dimensions of said wire antenna portions and of said aperture; (3) determining if the acquired positions and dimensions meet predetermined tolerances; (4) if the acquired dimensions and positions meet said tolerances, then placing a chip in the aperture so that said wire portions are positioned over connections pads of said chip and then bonding said wire portions to said connection pads.

2. The method of claim 1, comprising a step of positioning said two wire antenna portions over said aperture before said acquiring step.

3. The method of claim 1 wherein if said acquired dimensions do not meet said tolerances, then no chip is placed in the aperture and no bonding step is carried out.

4. The method of claim 1 wherein if said acquired positions of said wire antenna portions do not meet said tolerances, then said wire antenna portions are repositioned.

5. The method of claim 4 wherein said repositioning step of wire antenna portions is carried out repeatedly until said tolerances are met.

6. The method of claim 1, comprising a levelling step of the substrate around the aperture before said acquiring step 2.

7. The method of claim 1, wherein the positions and the dimensions of the wire and of the aperture are acquired via optical means.

8. The method of claim 1, wherein beside the step of acquiring the positions and the dimensions of the wire antenna portions and of said aperture (6) there is an additional step of acquiring the position and the dimensions of the chip and of the chip connection pads.

9. The method of claim 1, wherein the position and the dimensions of the chip and of the chip connection pads are acquired via optical means.

10. The method of claim 1, wherein said tolerances comprise at least the interaxial distance between the two wire antenna portions.

11. The method of claim 1, wherein said tolerances comprise the distance between the nearest lateral edge of the aperture and one of the wire antenna portions which has to be larger than the distance between the lateral edge of the chip and its nearest connection pad.

12. The method as defined in claim 1, wherein said tolerances comprise the distance between the connection pads of the chip.

13. The method of claim 1, wherein the substrate comprises multiple wire antenna portions embedded therein relative to multiple apertures, and that the process steps are repeated for all of them so that at the end a chip is bonded to each antenna for which said tolerances are met.

14. A functional inlay obtained by a method according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The present invention will be better understood from the following detailed description and from the following drawings.

[0052] FIG. 1 shows a block diagram of a method according to the present invention;

[0053] FIG. 2 illustrates an example of a chip used in the present invention;

[0054] FIG. 3 illustrates the wires of the antenna over an opening of the substrate;

[0055] FIGS. 4A to 4C illustrate schematically different possible positions of the chip and wires in the opening of the substrate;

[0056] FIGS. 4D and 4E illustrate variants of replacing the wires of the antenna;

[0057] FIGS. 5A to 5C illustrate the means used to support the substrate;

DETAILED DESCRIPTION

[0058] For the general method of manufacturing an inlay and connecting a chip to the embedded antenna wire to which the present invention may be applied, reference is made to the embodiments of methods and devices disclosed in WO 2014/008937 incorporated by reference therein.

[0059] It has also to be noted that all elements (aperture, wires, chip) have a well-defined and quite symmetrical shape (this could be different for example if the pads of the chip are placed in a non-symmetrical manner on the chip). This helps decrease the number of positions and/or dimensions which have to be measured by the system which are at least;

the center of the chip (dimensions and positions of the pads are then deduced very precisely)
the interaxial distance of the two wire portions
the geometrical center of the parallelepiped formed by the two wire portions
the dimensions of the aperture
the geometrical center of the aperture

[0060] Additionally, to ensure that the camera focus on the right position (depth), an additional tool is used bringing the cavity/wires/sheet (material around the cavity) to a defined height fin the z focus axis of the camera). In the realized embodiment, this tool may simply be a small ring of material which is processed from below the sheet and is then positioned in order to support the layer at the defined height)

[0061] The chip holder tool as used in WO 2014/008937 will comprise a similar ring around the chip position, so that when the tool is in the “bonding” position, the cavity/wires/sheet material is positioned exactly at the same position as when measured by the camera. This ensures a perfect matching of the bonding process.

[0062] It should also be noted that the tray used to manipulate the sheet with the embedded antennas is formed by a transparent (plastic) plate, showing large apertures around each chip/cavity position (large enough to allow tools to approach from both sides of the sheet). This means that around each cavity, the sheet material is not supported, and shows generally a slight depression (due to its own weight and the antenna wires weight). The process steps described above are mainly here to correct this slight deformation of the sheet.

[0063] In a basic embodiment, positions which are determined to be out of the tolerance (wires and/or aperture) are going to be excluded of the bonding step.

[0064] An embodiment, of the method according to the present invention is illustrated in FIG. 1. The method comprises al least the following steps:

(1) providing a substrate with a wire antenna embedded therein and an aperture. Typically, this can be done as illustrated In FIGS. 1 to 3 of WO 2014/008937 and their related description, as a possible realization embodiment;
(2) leveling the substrate around the aperture for visual acquisition, for example via a camera or other equivalent optical means. This step may be realized, as described above, by the use of additional means;
(3) acquiring the positions and the dimensions of the wire and of the aperture. This step may be carried out with adapted optical means, for example a camera or other equivalent means;
(4) acquiring the position and dimensions of the chip. As for the precedent step, this step may be earned out with adapted optical means(for example a camera or other equivalent means;
(5) determining if the measured positions and dimensions match the predetermined tolerances. This step, as described above considers the sizes of the elements measured and their positions to decide whether the tolerances are met and whether the process of the invention may be carried out;
(6) if the measured dimensions and positions match the predetermined tolerances, then the process may be continued and the chip bonded to the wires, as illustrated in FIGS. 7 and 8 of WO 2014/008937 and explained in the corresponding description;
(7) alternatively, if the tolerances (dimensions and positions) are not met, the positions are corrected or the wires are repositioned and a new check is carried out again (step (5) above) and then the process is carried out (step (6) above). If the tolerances are not met once again, then a new correction is carried out with subsequent control. This step may in fact be carried out repeatedly until finally the tolerances are met and the chip is bonded to the wires. Alternatively, it may be carried out a limited number of times (once, twice etc) in order not to slow down the overall production process. In another variant, the correction may be carried out only if the tolerance are not met but for a small value, this meaning that a correction step will most probably allow the tolerance to be easily met. If the measured values are too far away from the defined tolerance than no correction step is carried out and the bonding operation is not carried out at all.

[0065] FIG. 2 illustrates a top view of a chip 1 with its connexion pads 2, 3. This chip typically corresponds to the chip 11 of WO 2014/008937 (see FIGS. 7 and 8 of this earner application). The center point of this chip is determined by the crossing of the two lines 11, 12.

[0066] FIG. 3 illustrates a top view of the ends 4, 6 of a wire antenna passing over the opening 6 of a substrate 7. This typically corresponds to FIG. 3 of WO 2014/008937. The two crossing lines 13, 14 allowing to determine the the geometrical center point of the parallelepiped formed by the two wire portions 4, 5.

[0067] FIG. 4A illustrates the positioning of a chip 1 with its pads 2, 3 over the antenna ends 4, 5 in the opening 6 of a substrate 7. This corresponds merely to the situation illustrated in FIGS. 7 to 10 of WO 2014/008937. The chip may be easily aligned with the antenna ends if both center points are aligned. The situation illustrated Is ideal with an essentially constant distance between the sides of the chip 2 and the sides of the opening 6.

[0068] FIG. 4B Illustrates another positioning step of a chip 1 with its pads 2, 3 over the wire ends 4, 5 but here the wire ends 4, 5 are not perfectly aligned in the opening (as in FIG. 4A) but are offset to the (left) side. In the case illustrated, one sees that the necessary tolerances are still met and that the chip 1 is still within the opening 6 so that the bonding may be carried out.

[0069] FIG. 4C illustrates another positioning step of a chip 1 with its pads 2, 3 over the wire ends 4, 5 but here the wire ends 4, 5 are further offset to the (left) side by comparison with FIG. 4B. In this case, one sees that because of the size of the chip, when the center points are aligned there is an overlap zone 8 between the chip 1 and the substrate 7 that renders the bonding not possible. In this case, we run in the situation of step (7) above, and a correction (here a repositioning of the wire ends 4, 5 with a shift to the right side) is necessary. This shift may be carried out with appropriate means of the machine to reach the positions illustrated in FIG. 4B or even better as illustrated in FIG. 4A.

[0070] FIG. 4D illustrates an embodiment of the process used to displace the wire ends 4, 5 of the antenna if they are not aligned with the pads 2, 3 of the chip 1. It is clear from the figure that the distance D between the wire ends 4 and 5 is much larger than the one between the pads 2 and 3 on the chip 1. This is typically a case wherein if the tolerance values are not met at first, and this can be changed by modifying the positioning of the wire ends.

[0071] FIG. 4E illustrates a possible embodiment wherein only wire end 4 is moved/formed so that the distance D′ between wires ends 4, 5 is in relation to the distance between pads 2, 3 of the chip 1 to allow a proper connection. Appropriate wire-positioning means are disclosed for example in WO2008/114091 which is incorporated by reference in the present application in its entirety. Note however that the preferred embodiment will be to displace/to form the both wires end 4 and 5: either symmetrically or even better by re-centering the wire ends around the center of the cavity (such that the geometrical center of the wire ends meet the geometrical center of the aperture) and with a distance D′ corresponding to the distance between the pads 2, 3 of the chip 1.

[0072] The choice of the number of wire ends being displaced may be done according to circumstances, for example taking account of the position of the chip 1. For example, as In FIG. 4D, the chip 1 is in the middle of the wire ends 4, 5 with the pads 2, 3 at substantially the same distance from the wire ends 4, 5. In this situation, a symmetric re-placing the wire ends is probably the most effective and quickest way to proceed.

[0073] Of course, these are only two illustrations of many different configurations that are possible and the important result sought is that the spacing of the wire ends is corrected to meet the tolerance, that the chip is positioned to align with the wires and that both fit with aperture position/dimensions.

[0074] FIG. 5A illustrates the position of the substrate when not supported: as shown, it forms a slight depression. To avoid this depression and present a straight surface to the camera 3 as optical means, a supporting tool 10 is used as illustrated in FIG. 5B. FIG. 5C illustrates the same situation as in FIG. 5B, but with a chip 1 being In position (as for example in the top view of FIG. 4A).

[0075] Of course, ail the methods and embodiments described herein are to be regarded as illustrative examples and should not be construed in a limiting manner. Modifications are possible within the scope of the present invention, for example by use of equivalent technical means and/or method steps. In addition, different embodiments described herein may be combined together according to circumstances.