Parallel filter structure, oscilloscope and method of processing a signal

Abstract

The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

Claims

1. A parallel filter structure for processing a signal, the parallel filter structure comprising: a processing circuit; a signal input configured to receive a time and value discrete input signal; a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal; and a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both are connected with the signal input such that the feed forward equalizer circuit and the decision feedback equalizer circuit both process the same time and value discrete input signal in parallel that was received via the signal input, and wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both provide output signals in parallel via separate output interfaces, wherein the output signals are forwarded to the processing circuit that processes the respective output signals.

2. The parallel filter structure according to claim 1, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit are communicatively connected with each other.

3. The parallel filter structure according to claim 1, wherein at least one feed forward equalizer parameter of the feed forward equalizer circuit is set depending on at least one decision feedback equalizer parameter of the decision feedback equalizer circuit.

4. The parallel filter structure according to claim 3, wherein the dependency is determined based on a minimum of a cost function.

5. The parallel filter structure according to claim 4, wherein the processing circuit is configured to minimize the cost function.

6. The parallel filter structure according to claim 4, wherein the cost function comprises the error squared between an output signal of the feed forward equalizer circuit and an output signal of the decision feedback equalizer circuit.

7. The parallel filter structure according to claim 1, wherein the parallel filter structure is implemented on a single chip.

8. The parallel filter structure according to claim 7, wherein the parallel filter structure is implemented on an application-specific integrated circuit (ASIC).

9. The parallel filter structure according to claim 7, wherein the feed forward equalizer circuit is implemented in a real time section of the chip.

10. The parallel filter structure according to claim 7, wherein the decision feedback equalizer circuit is implemented in a non-real time section of the chip.

11. The parallel filter structure according to claim 1, wherein an output signal of the feed forward equalizer circuit is fed to an interface for a trigger circuit.

12. The parallel filter structure according to claim 11, wherein the parallel filter structure further comprises the trigger circuit that is connected with the feed forward equalizer circuit.

13. The parallel filter structure according to claim 1, wherein an output signal of the decision feedback equalizer circuit is fed to an interface for an eye diagram circuit.

14. The parallel filter structure according to claim 13, wherein the parallel filter structure further comprises the eye diagram circuit that is connected with the decision feedback equalizer circuit.

15. An oscilloscope comprising the parallel filter structure according to claim 1.

16. The oscilloscope according to claim 15, wherein the oscilloscope further comprises a trigger circuit that is connected with an interface associated with the feed forward equalizer circuit that is separately formed with respect to the trigger circuit.

17. The oscilloscope according to claim 15, wherein the oscilloscope further comprises an eye diagram circuit that is connected with an interface associated with the decision feedback equalizer circuit that is separately formed with respect to the eye diagram circuit.

18. A method of processing a signal, wherein the method comprises the steps of: receiving a time and value discrete input signal via a signal input; filtering the time and value discrete input signal by a feed forward equalizer circuit of a parallel filter structure; and filtering the time and value discrete input signal by a decision feedback equalizer circuit of the parallel filter structure, which together with the feed forward equalizer circuit forms a parallel circuit of the parallel filter structure, wherein the parallel filter structure comprises a first output interface associated with the feed forward equalizer circuit such that an output signal of the feed forward equalizer circuit is fed to the first output interface, wherein the parallel filter structure is connectable with a separately formed chip on which a trigger circuit is provided via the first output interface, wherein the parallel filter structure comprises a second output interface associated with the decision feedback equalizer circuit such that an output signal of the decision feedback equalizer circuit is fed to the second output interface, wherein the parallel filter structure is connectable with a separately formed chip on which an eye diagram circuit is provide via the second output interface, and wherein the first output interface and the second output interface are separate output interfaces.

19. The method according to claim 18, wherein at least one feed forward equalizer parameter of the feed forward equalizer circuit is set depending on at least one decision feedback equalizer parameter of the decision feedback equalizer circuit.

20. A parallel filter structure for processing a signal, the parallel filter structure comprising: a processing circuit; a signal input configured to receive a time and value discrete input signal; a feed forward equalizer circuit directly connected via a first line with the signal input for receiving the time and value discrete input signal; and a decision feedback equalizer circuit directly connected via a second line with the signal input for receiving the time and value discrete input signal, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both are connected with the signal input such that the feed forward equalizer circuit and the decision feedback equalizer circuit both process the same time and value discrete input signal in parallel that was received via the signal input, and wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both provide output signals in parallel that are forwarded to the processing circuit that processes the respective output signals.

Description

DESCRIPTION OF THE DRAWINGS

(1) The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

(2) FIG. 1 schematically shows an oscilloscope according to an embodiment of the present disclosure, which comprises an embodiment of a parallel filter structure according to one or more aspects of the present disclosure;

(3) FIG. 2 schematically shows a flow-chart that illustrates a representative method of processing a signal according to an embodiment of the present disclosure;

(4) FIG. 3 schematically shows an overview of a feed forward equalizer (FFE) circuit according to one embodiment; and

(5) FIG. 4 schematically shows an overview of a decision feedback equalizer (DFE) circuit according to one embodiment.

DETAILED DESCRIPTION

(6) The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Similarly, any steps described herein may be interchangeable with other steps, or combinations of steps, in order to achieve the same or substantially similar result. Moreover, some of the method steps can be carried serially or in parallel, or in any order unless specifically expressed or understood in the context of other method steps.

(7) FIG. 1 depicts an oscilloscope 10 for processing a signal. In the embodiment of FIG. 1, the oscilloscope 10 comprises a housing 12 with a front end 14. At the front end 14 of the oscilloscope 10, an analog input 16 is provided that is configured to receive an analog input signal. The analog input 16 is connected with a sampling circuit 18 that processes the analog input signal in order to generate a digitized signal, namely a time and value discrete input signal.

(8) The time and value discrete signal provided by the sampling circuit 18 is forwarded to a parallel filter structure 20 that processes the respective time and value discrete signal. The parallel filter structure 20 has a signal input 22 via which the time and value discrete input signal is received. In addition, the parallel filter structure 20 has a parallel circuit 24 that comprises two different equalizer circuits, namely a feed forward equalizer circuit 26 as well as a decision feedback equalizer circuit 28. As shown in FIG. 2, both equalizer circuits 26, 28 are connected with the signal input 22 such that both circuits 26, 28 receive the time and value discrete input signal that is processed by both equalizer circuits 26, 28 in parallel.

(9) Returning to FIG. 1, the parallel filter structure 20 also comprises a processing circuit 30 that is interconnected between both equalizer circuits 26, 28, thereby establishing a communication connection between the equalizer circuits 26, 28. Accordingly, data/information of the respective equalizer circuits 26, 28 may be gathered, for example data/information of the decision feedback equalizer circuit 28, which may be used for setting at least one of the equalizer circuits 26, 28 appropriately.

(10) For instance, the processing circuit 30 is assigned to output interfaces of the respective equalizer circuits 26, 28 such that output signals of the equalizer circuits 26, 28 are forwarded to the processing circuit 30 that processes the respective output signals.

(11) Again, the processing circuit 30 receives at least the output signal of the decision feedback equalizer circuit 28 in order to obtain information associated with the decision feedback equalizer circuit 28, which is used for controlling the feed forward equalizer circuit 26.

(12) Generally, the respective equalizer circuits 26, 28 each have respective parameters, also called filter parameters or filter coefficients, that are set/parameterized in order to define the respective processing of the time and value discrete input signal by the respective equalizer circuits 26, 28.

(13) Example schematic overviews of the equalizer circuits 26, 28 are shown in FIGS. 3 and 4. The FFE circuit 26 shown in FIG. 3 is a finite impulse response (FIR) filter that is used to compensate pre- and post-oscillations of a channel impulse response:
y(t/T.sub.s)=h.sub.FFE.sup.T.Math.x(t/T.sub.s)

(14) Accordingly, the influence of an inter-symbol interference (ISI) on the symbol decision is reduced, thereby reducing the risk of false decision.

(15) The filter coefficients of the FFE circuit 26 are expressed by the vector
h.sub.FFE=[h.sub.0h.sub.1 . . . h.sub.L.sub.FFE.sub.−1].sup.T,

(16) with L.sub.FFE representing the length of the filter, namely the FFE circuit 26.

(17) Further, the time and value discrete input signal is expressed by the following vector:
x(t/T.sub.s)=[x(t/T.sub.s)x(t/T.sub.s−T.sub.a/T.sub.s) . . . x(t/T.sub.s−(L.sub.FFE−1).Math.T.sub.a/T.sub.s)].sup.T

(18) In the formulas, T.sub.S relates to the symbol rate, whereas T.sub.a relates to the sample rate.

(19) In FIG. 3, it is also shown that the symbol decision Q takes place based on the output signal of the FFE circuit 26, wherein the output signal may also be used for generating an eye diagram.

(20) The DFE circuit 28 shown in FIG. 4 is a combination of a finite impulse response (FIR) filter and an infinite impulse response (IIR) filter, thereby providing two filter portions, namely a FIR portion for compensating the pre- and post-oscillations of the channel impulse response as well as an IIR portion for only compensating post-oscillations of the channel impulse response. Hence, the signal processing of the DFE circuit 28 can be expressed as follows:
y(t/T.sub.s)=h.sub.FFE.sup.T.Math.x(t/T.sub.s)+h.sub.DFE.sup.T.Math.y.sub.q(t/T.sub.s−1).

(21) The FIR portion of the DFE circuit 28 can be expressed by the vector
h.sub.FFE=[h.sub.FFE,0h.sub.FFE,1 . . . h.sub.FFE,L.sub.FFE.sub.−1].sup.T

(22) and the IIR portion of the DFE circuit 28 can be expressed by the vector
h.sub.DFE=[h.sub.DFE,1h.sub.DFE,2 . . . h.sub.DFE,L.sub.DFE.sub.−1].sup.T.

(23) L.sub.FFE represents the length of the FIR filter portion, whereas L.sub.DFE represents the length of the IIR filter portion.

(24) The time and value discrete input signal is expressed by the following vector:
x(t/T.sub.s)=[x(t/T.sub.s)x(t/T.sub.s−T.sub.a/T.sub.s) . . . x(t/T.sub.s−(L.sub.FFE−1).Math.T.sub.a/T.sub.s)].sup.T

(25) The symbols decided can be expressed by the vector:
y.sub.q(t/T.sub.s−1)=Q{y(t/T.sub.s−1)}.

(26) In FIG. 4, it is shown that the symbol decision Q takes place based on the output signal of the DFE circuit 28, wherein the output signal may also be used for generating an eye diagram. The DFE circuit 28 has a feedback structure.

(27) Generally, the equalizer circuits 26, 28 may be trained by a method of, for example, least squares. In case of the DFE circuit 28, the filter length of the IIR filter portion is set to 0.

(28) The approach, which minimizes the mean square error between the equalized signal y(t/T.sub.S) and transmitted symbols y.sub.q(t/T.sub.S), assumes that the error e(t/T.sub.S) of the equalized signal y(t/T.sub.s) is so small that no symbol error decisions occur in the symbol decision Q. It minimizes the mean square error between equalized signal y(t/T.sub.S) and transmitted symbols y.sub.q(t/T.sub.S):
K=[X(t/T.sub.s).Math.h.sub.FFE+Y.sub.q(t/T.sub.s−1).Math.h.sub.DFE−y.sub.q(t/T.sub.s)].sup.T.Math.[X(t/T.sub.s).Math.h.sub.FFE+Y.sub.q(t/T.sub.s−1).Math.h.sub.DFE−y.sub.q(t/T.sub.s)]

(29) wherein the matrix of the time and value discrete input signal is expressed by:
X(t/T.sub.s)=[x.sup.T(t/T.sub.s+T.sub.D/T.sub.s)x.sup.T(t/T.sub.s+T.sub.D/T.sub.s−1) . . . x.sup.T(t/T.sub.s+T.sub.D/T.sub.s−N+1)].sup.T

(30) and wherein the matrix of the transmitted symbols is expressed by:
Y.sub.q(t/T.sub.s−1)=[y.sub.q.sup.T(t/T.sub.s−1)y.sub.q.sup.T(t/T.sub.s−2) . . . y.sub.q.sup.T(t/T.sub.s−N)].sup.T

(31) Moreover, N corresponds to the observation length of the observer. Moreover, the delay T.sub.D/T.sub.S was introduced so that the respective PPE circuit 26 can also compensate for pre-cursors of the channel impulse response. Then, the cost function to be minimized can be expressed as follows
[h.sub.FFE.sup.Th.sub.DFE.sup.T].sup.T=−½.Math.A.sup.−1.Math.b

(32) wherein the matrix A corresponds to:
A=[X(t/T.sub.s)Y.sub.q(t/T.sub.s−1)].sup.T.Math.[X(t/T.sub.s)Y.sub.q(t/T.sub.s−1)]

(33) and the vector b corresponds to:
b=−2.Math.[X(t/T.sub.s)Y.sub.q(t/T.sub.s−1)].sup.T.Math.y.sub.q(t/T.sub.s)

(34) As mentioned above, the feed forward equalizer circuit 26 and the decision feedback equalizer circuit 28 are communicatively connected with each other via the processing circuit 30. In some embodiments, the filter parameter/coefficient of the feed forward equalizer circuit 26 is set depending on at least one decision feedback equalizer parameter of the decision feedback equalizer circuit 28.

(35) The respective decision feedback equalizer parameter of the decision feedback equalizer circuit 28 may be derived from the output signal of the decision feedback equalizer circuit 28 that has been forwarded to the processing circuit 30. Alternatively, the processing circuit 30 gathers the respective filter parameters of the decision feedback equalizer circuit 28 directly.

(36) In some embodiments, the processing circuit 30 generates a cost function that is minimized in order to find the respective setting of the feed forward equalizer parameter. The cost function may relate to an error squared between the output signals of the respective equalizer circuits 26, 28. Hence, the respective cost function is minimized in order to identify the respective setting for the feed forward equalizer parameter.

(37) The respective cost function to be minimized can be expressed as follows:
K=[X.sub.äquFFE(t/T.sub.s).Math.h.sub.äquFFE−X(t/T.sub.s).Math.h.sub.FFE−Y.sub.q(t/T.sub.s−1).Math.h.sub.DFE)].sup.T.Math.[X.sub.äquFFE(t/T.sub.s).Math.h.sub.äquFFE−X(t/T.sub.s).Math.h.sub.FFE−Y.sub.q(t/T.sub.s−1).Math.h.sub.DFE)]

(38) The impulse response of the equivalent FFE circuit 26 is expressed by:
h.sub.äquiFFE=[h.sub.0h.sub.1 . . . h.sub.L.sub.äquFFE.sub.−1].sup.T

(39) The time and value discrete input signal of the equivalent FFE circuit 26 is expressed by:
X.sub.äquFFE(t/T.sub.s)=[x.sup.T(t/T.sub.s+T.sub.D,äquFFE/T.sub.s)x.sup.T(t/T.sub.s+T.sub.D,äquFFE/T.sub.s−1) . . . x.sup.T(t/T.sub.s+T.sub.D,äquFFE/T.sub.s−N+1)].sup.T

(40) The cost function K becomes minimized by
h.sub.äquFFE=½.Math.A.sup.−1.Math.b

(41) wherein the matrix A is
A=X.sub.äquFFE.sup.T(t/T.sub.s).Math.X.sub.äquFFE(t/T.sub.s)

(42) And wherein the vector b is:
b=−2.Math.X.sub.äquFFE.sup.T(t/T.sub.s).Math.[X(t/T.sub.s).Math.h.sub.FFE+Y.sub.q(t/T.sub.s−1).Math.h.sub.DFE)]

(43) As shown in FIG. 1, the parallel filter structure 20 is implemented on a single chip 32, for instance an application-specific integrated circuit (ASIC). The chip 32 may have a real time section 34 as well as a non-real time section 36 that are used for different purposes. The feed forward equalizer circuit 26 is implemented in the real time section 34, whereas the decision feedback equalizer circuit 28 is implemented in the non-real time section 36 of the chip 32.

(44) Further, the parallel filter structure 20 comprises at least one (output) interface 38 that is associated with the feed forward equalizer circuit 26 such that the output signal of the feed forward equalizer circuit 26 is fed to the interface 38 that may be associated with a trigger circuit 40.

(45) The trigger circuit 40 may be part of the parallel filter structure 20 such that the trigger circuit 40 is also implemented on the chip 32. Alternatively, the trigger circuit 40 is established as a separately formed circuit that is provided on a separately formed chip within the oscilloscope 10.

(46) Further, the parallel filter structure 20 may comprise another output interface 42 that is associated with the decision feedback equalizer circuit 28 such that the output signal of the decision feedback equalizer circuit 28 is fed to the output interface 42 that is associated with an eye diagram circuit 44. The eye diagram circuit 44 may be implemented on the chip 32 or on a separately formed chip that is connected with the chip 32 on which the parallel filter structure 20 is implemented.

(47) The parallel filter structure 20, for example the parallel circuit 24, ensures that the output signals of the different equalizer circuits 26, 28 are equivalent with each other since the filter parameters of the feed forward equalizer circuit 26 are set accordingly as described above. The equivalence is ensured by minimizing the cost function, namely the error squared between the output signals of the equalizer circuits 26, 28. Accordingly, both equalizer circuits 26, 28 have the same transfer function, resulting in similar or equivalent equalizing functions.

(48) Therefore, the oscilloscope 10 is enabled to provide a real-time processing wherein the equalization functions have the same characteristics in a triggering path and a displaying path of the oscilloscope 10.

(49) Certain embodiments disclosed herein utilize circuitry (e.g., one or more circuits) in order to implement protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph. It will be further appreciated that the terms “circuitry,” “circuit,” “one or more circuits,” etc., can be used synonymously herein.

(50) In an embodiment, circuitry includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof.

(51) In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof).

(52) In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein.

(53) In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation.

(54) In an embodiment, circuitry includes an implementation comprising one or more processors or portions thereof and accompanying software, firmware, hardware, and the like.

(55) Various embodiments are described above with reference to block diagrams and/or flowchart illustrations of apparatuses, methods, systems, and/or computer program instructions or program products. It should be understood that each block of any of the block diagrams and/or flowchart illustrations, respectively, of portions thereof, may be implemented in part by computer program instructions, e.g., as logical steps or operations executing on one or more computing devices. These computer program instructions may be loaded onto one or more computer or computing devices, such as special purpose computer(s) or computing device(s) or other programmable data processing apparatus(es) to produce a specifically-configured machine, such that the instructions which execute on one or more computer or computing devices or other programmable data processing apparatus implement the functions specified in the flowchart block or blocks and/or carry out the methods described herein.

(56) These computer program instructions may also be stored in one or more computer-readable memory (including volatile and non-volatile media). or portions thereof, that can direct one or more computers or computing devices or other programmable data processing apparatus(es) to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the functionality specified in the flowchart block or blocks.

(57) It will be appreciated that the term computer or computing device can include, for example, any computing device or processing structure, including but not limited to a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof.

(58) Accordingly, blocks of the block diagrams and/or flowchart illustrations support various combinations for performing the specified functions, combinations of operations for performing the specified functions and program instructions for performing the specified functions. Again, it should also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, or portions thereof, could be implemented by special purpose hardware-based computer systems or circuits, etc., that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

(59) Embodiments of the present disclosure may also take the form of an apparatus, system, computing device, computing entity, and/or the like executing instructions stored on computer-readable storage media to perform certain steps or operations. The computer-readable media include cooperating or interconnected computer-readable media, which exist exclusively on a processing or processor system or distributed among multiple interconnected processing or processor systems that may be local to, or remote from, the processing or processor system. However, embodiments of the present disclosure may also take the form of an entirely hardware embodiment performing certain steps or operations.

(60) In the foregoing description, specific details are set forth to provide a thorough understanding of representative embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the embodiments disclosed herein may be practiced without embodying all of the specific details. In some instances, well-known process steps have not been described in detail in order not to unnecessarily obscure various aspects of the present disclosure. Further, it will be appreciated that embodiments of the present disclosure may employ any combination of features described herein.

(61) The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about,” “approximately,” “near,” etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase “at least one of A and B” is equivalent to “A and/or B” or vice versa, namely “A” alone, “B” alone or “A and B.”. Similarly, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.

(62) Throughout this specification, terms of art may be used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise.

(63) The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.