Bidirectional AC-DC converter with multilevel power factor correction

Abstract

A multilevel stage of a bidirectional AC power converter, comprising: a set of switches in series, a set of capacitors in series, the set of capacitors being in parallel with the set of switches; a number of sets of diodes in series; a center tap along the set of switches in series; and a pair of taps, respectively after the first and before the last switch of the set of switches in series; wherein each node between respective capacitors is connected to a node between respective diodes. A converter first stage for a 3-level converter has 6 switches, two capacitors, and two diodes, with the junction between diodes connected to the junction between capacitors, and the diode legs between switches 2-3 and 4-5. The center tap is between switches 3-4, and the pair of taps between switches 1-2 and 5-6.

Claims

1. A multilevel stage of an AC power converter having at least three levels, comprising: a set of switches in series, comprising two switches per level; a set of capacitors in series, having one less capacitor than the number of levels, the set of capacitors being in parallel with the set of switches; a clamping network interconnecting nodes of the set of switches with nodes of the set of capacitors, to establish incremental voltages across the set of capacitors; a center tap along the set of switches in series; and a pair of taps, respectively after the first and before the last switch of the set of switches in series; wherein the set of switches are operable to transfer power between the center tap operating at a first AC frequency and the pair of taps operating at a second AC frequency.

2. The multilevel stage of an AC power converter according to claim 1, wherein: the clamping network comprises a number of sets of diodes in series corresponding to the number of levels minus two, defining a unidirectional current flow direction along the respective set of diodes, nodes between respective capacitors are connected to a single node between respective diodes of a respective set of diodes, each set of diodes connecting nodes between respective switches spaced by one less than the number of levels starting after the second switch and ending before the second to last switch, such that the number of switches and the number of diodes in parallel is the same, and the connection between the node between respective capacitors and the single node between respective diodes of a respective set of diodes is made such that the number of capacitors beneath the connection node is equal to the number of diodes beneath the connection node.

3. The multilevel stage of an AC power converter according to claim 1, wherein the center node is connected to a phase of a multiphase power source.

4. The multilevel stage of an AC power converter according to claim 1, wherein the center node is connected to a phase of a multiphase power sink.

5. The multilevel stage of an AC power converter according to claim 1, wherein the pair of taps are connected to a resonant synchronous rectifier.

6. The multilevel stage of an AC power converter according to claim 1, wherein the pair of taps are connected to a second multilevel power converter having at least three levels, comprising: a second set of switches in series, comprising twice the number of switches as levels; a second set of capacitors in series, having one less capacitor than the number of levels, the second set of capacitors being in parallel with the second set of switches; second clamping network interconnecting nodes of the second set of switches with nodes of the second set of capacitors, to establish incremental voltages across the second set of capacitors; a second center tap along the second set of switches in series; and a second pair of taps, respectively after the first and before the last switch of the second set of switches in series.

7. The multilevel stage of an AC power converter according to claim 1, further comprising a controller configured to control the first set of switches to interface an AC voltage having a first waveform at the center tap with a DC voltage across the set of capacitors, and to interface the DC voltage across the set of capacitors with an AC voltage having a second AC waveform at the pair of taps, the first waveform and the second waveform being different.

8. The multilevel stage of an AC power converter according to claim 1, further comprising: a transformer and a resonant tank circuit; a synchronous bridge rectifier comprising a set of switches in series; and a controller configured to: control the first set of switches and the set of switches to convert an AC current into a first DC voltage across the set of capacitors, control the first set of switches to generate a resonant AC waveform to transfer power through the transformer to the synchronous bridge rectifier, and control the synchronous bridge rectifier to produce a second DC voltage.

9. The multilevel stage of an AC power converter according to claim 1, configured to operate with a phase of an AC voltage signal between 50 and 500 VAC RMS applied to the center tap.

10. The multilevel stage of an AC power converter according to claim 1, further comprising a tank circuit comprising a capacitor and an inductor and having a resonant frequency between 2 kHz-1 MHz, which interfaces with the pair of taps.

11. The multilevel stage of an AC power converter according to claim 1, further comprising: a resonant tank circuit, connected to a node between two of the set of switches in series; a synchronous converter, configured to interface with a secondary power system; a coupling transformer, configured to couple power from the resonant tank circuit to the synchronous converter; and a controller, configured to control the switches and the synchronous converter, to transfer power from a multiphase AC system supplying power to the AC power converter to a load on the synchronous converter.

12. The multilevel stage of an AC power converter according to claim 11, wherein the multiphase AC system supplying power to the AC power converter operates at a frequency of 50 to 400 Hz and wherein the controller is configured to control the switches to generate a waveform having a frequency of greater than 10 kHz at the pair of taps.

13. The multilevel stage of an AC power converter according to claim 1, further comprising an automated controller, configured to: control the set of switches in a startup sequence to charge the set of capacitors, and after the capacitors are charged, to control the set of switches in an operating sequence different from the startup sequence; and to perform power factor correction.

14. The multilevel stage of an AC power converter according to claim 1, wherein power transferred through the pair of taps interfaces with at least one of a rechargeable battery, a motor, a generator, and a motor-generator.

15. An AC power converter having a number of levels N, wherein N is at least 3, comprising: a set of switches in series, comprising (N×2) switches, having a center tap and a pair of taps after the first and before the last switches; (N−1) capacitors in series, the (N−1) capacitors in series being in parallel with the set of switches in series; and a clamping network communicating with nodes between the set of switches, configured to establish monotonically increasing voltages at sequential nodes between the capacitors in series, wherein the switches, clamping network and capacitors are configured to generate, from a first AC waveform at the center tap and a controlled sequence of switching signals, a DC voltage across the capacitors in series, and a second AC waveform from the pair of taps.

16. The AC power converter according to claim 15, wherein the clamping network comprises (N−2) sets of diodes, wherein nodes between respective capacitors are connected to nodes between respective diodes, each set of diodes bridging a respective node between respective switches spaced by one less than the number of levels starting after the second switch and ending before the second to last switch.

17. The AC power converter according to claim 15, further comprising: a resonant tank circuit, connected between two of the set of switches in series; a synchronous converter, configured to interface with a secondary power system; a coupling transformer, configured to couple power from the resonant tank circuit for each respective phase of a multi-phase AC system to the synchronous converter; and a controller, configured to control the set of switches and the synchronous converter, to transfer power from the multiphase AC system to a load on the synchronous converter.

18. A method of power conversion, comprising: providing a multilevel stage of an AC power converter having at least three levels, comprising: a set of switches in series, comprising two switches per level, having a center tap and a pair of taps before the first and last switches; a set of capacitors in series, the set of capacitors in series being in parallel with the set of switches in series; a clamping network, interconnecting nodes between switches of the set of switches and nodes between capacitors of the set of capacitors, configured to establish different operating voltages at nodes between the set of capacitors; interfacing the center tap with a first AC system; interfacing the pair of taps with a second AC system, wherein an AC waveform of the first system is different from an AC waveform of the second AC system; and automatically controlling a sequence of switching signals for the set of switches to generate a DC voltage across the set of switches in series and the capacitors in series, and to transfer power between the first AC system and the second AC system.

19. The method according to claim 18, wherein the clamping network comprises sets of diodes which transfer a unidirectional current from a node between switches to a node between capacitors, each set of diodes connecting nodes between respective switches spaced by one less than the number of levels starting after the second switch and ending before the second to last switch, to establish a voltage gradient on the successive nodes of the set of capacitors.

20. The method according to claim 18, further comprising: providing a synchronous converter as the second AC system, the synchronous converter receiving power from the pair of taps and driving a load; and automatically controlling the synchronous converter, to transfer the power from the pair of taps through the synchronous converter to the load.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 shows a prior art two-level converter first stage;

(2) FIG. 2 shows a prior art three-phase converter design, with 12 active switches, and one capacitor.

(3) FIG. 3 shows a nine-switch power converter design.

(4) FIG. 4 shows a six switch power converter according to the present invention.

(5) FIG. 5 shows current paths through the six switch power converter according to FIG. 4 in 3 different phases of operation

(6) FIG. 6A shows the converter according to FIG. 4 in conjunction with a synchronous bridge resonant second stage, for each of 3 phases in a battery charging configuration.

(7) FIG. 6B shows the circuitry for each phase of the 3-phase circuit for charging a battery.

(8) FIG. 6C shows a schematic diagram of the circuit of FIG. 6B, with output filters.

(9) FIG. 6D shows a 3-phase AC-DC power converter having a two-switch resonant second stages.

(10) FIG. 6E shows a relatively symmetric (except accommodations for operating frequency) circuit having 6-switch converters in each of the first stage and the second stage, permitting bidirectional AC-AC conversion.

(11) FIGS. 7 and 8 show gate drive signal logic and waveforms for a first embodiment of the invention, with a sinusoidal reference waveform.

(12) FIGS. 9 and 10 show gate drive signal logic and waveforms for a second embodiment of the invention with a multimodal reference waveform.

(13) FIG. 11 shows the resulting pulses for switches for phase A.

(14) FIG. 12 shows, for transformer primary side phase A, the voltage across switch node points x-y, and the phase A resonant current.

(15) FIG. 13 shows, for transformer secondary side phase A, the voltage across switch node points x-y, and the phase A resonant current.

(16) FIG. 14 shows a prior art style converter with 8 switches per phase at both the first stage and the second stage.

(17) FIG. 15 shows a prior art style converter design including the 6-switch matrix according to FIG. 2.

(18) FIG. 16 shows an 8-switch, 4-level converter according to the present invention.

(19) FIG. 17 shows a 10-switch, 5-level converter according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(20) A prior art two stage AC-DC converter according to the present invention with 3-level PFC is shown in FIG. 1. In this converter, the PFC switch-network and resonant converter primary switch-network are separate from each other. The PFC network interfaces the DC link with one AC port (zO) which is connected to utility AC. The other switch-network interfaces DC link with second AC port (xO) which is connected to resonant network. If the PFC switch network is to be merged with the primary switch network of resonant converter, the resulting network should have two AC ports. One of the AC ports interfaces with the utility AC while the other feeds the resonant network of the resonant converter.

(21) If the PFC stage and the primary side switch network are merged into a single switch network, a reduced the number of required semiconductors is achieved. Further, the semiconductor switches are mostly soft switching, and an increased switching frequency operation with respect to hard switched PFC is employed. Since the two converter stages are not completely decoupled, and the DC link capacitor value can be smaller.

(22) This is accomplished by cascading two additional switches onto the 3-level arm, one on each side and the new network is shown in FIG. 4. This network is tapped between x and y, forming the new AC port, to feed the resonant stage (not shown in FIG. 4).

(23) The switches are driven according to the state Table 1:

(24) TABLE-US-00001 TABLE 1 Positive Half Cycle Negative Half Cycle 1-Do D.sub.o-D.sub.i D.sub.i 1-D.sub.o D.sub.o-D.sub.i D.sub.i S1 OFF ON ON S1 OFF ON ON S2 ON OFF ON S2 ON OFF OFF S3 ON ON ON S3 ON ON OFF S4 ON ON OFF S4 ON ON ON S5 ON OFF OFF S5 ON OFF ON S6 OFF ON ON S6 OFF ON ON Zero Period of Active Period of Zero Period of Active Period of Resonant AC port Resonant AC port Resonant AC port Resonant AC port Zero Period of Active Period of Zero Period of Active Period of utility AC port utility AC port utility AC port utility AC port

(25) D.sub.o represents the active duty-cycle of the AC voltage pulse waveform produced between nodes x and y which feeds the resonant stage. This duty cycle is constant in each switching cycle. D.sub.i represents the duty cycle of the AC voltage pulse produced between nodes z and O. This duty cycle is sinusoidally varying with respect to time according to the input utility voltage and actively shapes the grid currents.

(26) Each switching cycle can be divided into 3 stages as shown in Table 1. In the first stage, both AC outputs are zero and is achieved by opening switches S1 and S6 and shorting all the remaining switches. It is evident from this switching pattern that the potential of x and y are the same and z is connected to O.

(27) In the second stage, AC output for resonant stage port is active and that for utility port is zero. This is accomplished by keeping S2 and S5 open and shorting all the remaining switches. The potential between x and y is +Vdc and z is connected to O. In the final stage, both the AC outputs are active. The switching pattern depends on the utility AC voltage polarity. For positive half cycle, S4 and S5 are open and remaining switches are short. The potential between x and y is +Vdc and z is also connected to +Vdc. For negative half cycle, S2 and S3 are open and remaining switches are short. The potential between x and y is +Vdc and z is also connected to −Vdc. In each sub cycle, exactly two switches are open and all other switches are closed. All the switching stages are shown in FIG. 5.

(28) From FIG. 4, it is evident that the node x is between node +Vdc and z; node y is in between z and −Vdc. Hence, the active period of inner AC port can be equal or less than that of outer AC port, D.sub.i<D.sub.o. Ideally, for greater power transfer to the resonant stage, D.sub.o should be ½. This will restrict D.sub.i also to ½ and the DC link utilization is low. As a compromise between DC link utilization and power transfer to resonant stage, D.sub.o=0.6 is chosen. However, it should be understood that different contexts may lead to different optimal duty cycles.

(29) The complete schematic of the 3-ph AC-DC Multilevel-Bridge tapped Resonant converter is shown in FIGS. 6A and 6B. FIG. 6A shows a single phase, while FIG. 6B shows all three phases. FIG. 6C shows a schematic representation of FIG. 6B, with output filters.

(30) FIG. 6D shows a similar architecture to that in FIG. 6B, but with a half-bridge synchronous converter second stage. FIG. 6E shows a symmetric AC-AC bidirectional converter architecture, with six switches per phase for each phase of the input and output.

(31) The converter (in this case configured as a battery charger) consists of 3 limbs with the first stage of each limb assembled by using 6 semiconductors switches and 2 diodes.

(32) The resonant converter of each phase consists of a resonant network and four-switch full-bridge converter connected to the respective battery. Note that a single battery or three separate batteries may be employed.

(33) For any N-level PFC, the modified integrated network can be built using the same procedure discussed before. In an N-level converter, each limb has 2×N semiconductor switches and (N−1)×(N−2) diodes. The above switching pattern can be easily implemented using a modulating scheme described below.

(34) Two Phase Opposition Disposition carrier waves are compared with two modulating waves to generate the switching pulses which control the semiconductor switches of the converter. The switching logic is shown in FIG. 7, and the associated waveforms in FIG. 8.

(35) The first modulating signal, denoted as D.sub.o, is constant as discussed above and defines the duty cycle of the voltage pulse fed to the asymmetric resonant converter. The second modulating signal, denoted as d.sub.i, is an alternating sinusoidal signal at grid frequency. The carriers of each phase leg are again shifted by 120 degrees with respect to those of other two legs. This creates a similar phase shift between the input voltages of resonant networks of each phase, resulting in an interleaving effect of output currents, thus reducing the output filter size at the battery terminals. Since the converter is three phase, triplen harmonics can be added in each phase which will cancel out each other in line voltages to improve the DC link utilization. Hence, the modulating signal d.sub.i can be obtained from a space vector algorithm.

(36) In another embodiment, the switching logic is provided in FIG. 9 (for phase A), and the waveforms shown in FIG. 10. Note that, since each phase is separately controlled, phase-specific corrections may be employed as appropriate to the control of the switch matrix.

(37) FIG. 11 shows the resulting pulses for switches for phase A. It is particularly noted that the switches are driven such that the falling edge of a gate drive pulse precedes the rising edge of the subsequent gate drive pulse, so that the on-states are non-overlapping between adjacent switches.

(38) FIG. 12 shows, for transformer primary side phase A, the voltage across switch node points x-y, and the phase A resonant current.

(39) FIG. 13 shows, for transformer secondary side phase A, the voltage across switch node points x-y, and the phase A resonant current.

(40) The converter provides the following advantages over an eight-switch first stage single level power converter:

(41) The semiconductor switches are reduced in number.

(42) The rated voltage of the semiconductor switches is reduced. This will reduce the ON resistance of the switch positively impacting the efficiency.

(43) Since the number of levels in voltage is increased, the THD of currents is reduced.

(44) The volume of PFC inductors is reduced.

(45) It can be used in medium-level voltage applications.

(46) It has faster PFC response by virtue of higher switching frequency.

(47) The DC link voltage level in the proposed converter is higher than that of the traditional converter. This can be lowered by using advanced pulse width modulating strategies.

(48) The design is contrasted with a prior art design that uses eight switches per phase for the PFC first stage, and in this case, eight switches per phase for the synchronous second stage, as shown in FIG. 14, for an AC-to-AC bidirectional converter.

(49) An alternate with twelve switches for three phases is shown in FIG. 15, which shows a similar second resonant stage which charges a single battery stack. This design employs a single level PFC stage, with integrated phases, and thus incurs various disadvantages as discussed above.

(50) The present invention integrates the front-end boost PFC rectifier and the high frequency converter stage of the resonant converter into a single stage low frequency AC to high frequency AC front-end converter. This modified front end feeds the resonant tank and the rectifier stage forming the complete AC-DC converter.

(51) The input ports of the resonant tanks are connected in delta form. The interleaved three phase modulation results in a bipolar voltage input to the resonant tank, and hence the series capacitors in the resonant tank are relieved from blocking the DC voltage. This reduces the stress on these capacitors and increases the stability and the lifetime of the converter. Moreover, the interleaved modulation results in 120-degree phase between the inputs of each resonant tank and hence reduces the DC ripple and the filter size on the rectifier side.

(52) Moreover, various switches in present converter are soft switched allowing higher intermediate AC switching frequencies, and hence can use low volume magnetic components and capacitors, as compared to configurations that employ lower intermediate AC switching frequencies, which require physically larger magnetic components (inductors, transformers) and capacitors. Further, the configuration reduces the stress on the capacitors enabling the stability and long life for the converter.

(53) The present converter may integrate a front-end boost PFC rectifier and a high frequency converter stage of a typical resonant converter, into a single stage low frequency AC to high frequency AC front-end converter.

(54) It is noted that the architecture employs conventional three-phase power, and the design may be readily scaled to accommodate a larger number of phases in less conventional system architectures.

(55) As discussed above, while the present design provides three levels, with additional switches and correspondingly more complex control logic, a greater number of levels may be employed.

(56) FIG. 16 shows a 4-level configuration.

(57) FIG. 17 shows a 5-level architecture.

(58) Each phase has an input structure comprising six switches (MOSFETs) in series, between a positive and negative rail, the input of each phase being the three upper and three lower switches. Between the rails are a pair of capacitors in series, whose junction is the O node. A pair of diodes extend from node O to the junction of the second and third, and third and fourth switches, respectively, and are reverse biased with respect to the rails. The outputs are between the first and second, and fifth and sixth switches.

(59) The switches in series are driven to synchronously rectify the input AC frequency, and produce the output at the high AC frequency. The high frequency is passed through a tank circuit and transformer to a set of bridges run at the high AC frequency, which may be either three-phase interleaved full bridges or triple single phase parallel full bridges.

(60) A 12 kW prototype is built which interfaces a three-phase, 480V AC line to charge or discharge a battery with terminal voltage ranging from 390V-780V.

(61) 900V rated SiC MOSFETs are used for switches in AC side network whereas 1200V rated switches are used in the DC side switch network.

(62) The converter design can be easily modified for any other AC mains and battery voltage levels. Table 2 shows a bill of materials for the prototype.

(63) TABLE-US-00002 TABLE 2 Power Circuit Board Manufacturer Part Number Description B81123C1102M000 CAP FILM 1000 PF 20% 500VAC RAD M20-7820442 CONN RCPT 4POS 0.1 GOLD PCB T9GV2L14-12 RELAY GEN PURPOSE SPST 20 A 12 V 1792229 TERM BLOCK 2POS 30 DEG 7.5 MM PCB FDFS6N548 MOSFET N-CH 30 V 7 A 8-SOIC CR201-25AE ALUMINUM HEATSINK 25 MM BLK ANODI R76UN22204040J CAP FILM 0.022UF 5% 2KVDC RADIAL B32653A0473J000 CAP FILM 0.047UF 5% 1KVDC RADIAL RT8532-20-2M5 CMC 2.5 MH 20 A 3LN TH 282858-4 TERM BLK 4P SIDE ENTRY 10 MM PCB CR201-75AE ALUMINUM HEATSINK 75 MM BLK ANODI C3M0030090K ZFET 900 V, 30 MOHM, G3 SIC MOSFE B32653A2472K000 CAP FILM 4700 PF 10% 2KVDC RADIAL R75UR32204040J CAP FILM 0.22UF 5% 2KVDC RADIAL C3M0075120K MOSFET N-CH 1200 V 30 A TO247-4 UPH2G221MHD CAP ALUM 220UF 20% 400 V RADIAL ASB03512HB-F00 FAN AXIAL 35 × 15 MM 12VDC WIRE CM5441Z101B-10 CMC 75 A 2LN 100 OHM TH TMDSDOCK28379D EXPERIMENTER TMS320F28379D EVAL TXM 075-112 AC/DC CONVERTER 12 V 72 W GCM32DC72A475KE02L CAP CER 4.7UF 100 V X7S 1210 ACM4520V-142-2P-T00 CMC 1 A 2LN 1.4 KOHM SMD AEC-Q200 R75UR32204040J CAP FILM 0.22UF 5% 2KVDC RADIAL C4D20120A DIODE SCHOTTKY 1.2 KV 20 A TO220-2

(64) The first stage of the converter provides multilevel operation, see FIG. 4, which employs two switches per level, and saves two switches per phase as compared to the prior art embodiment of FIG. 1, while obtaining the benefits of multiphase operation, including soft switching on most switches, and reduced stress. As shown in FIG. 10, the reference Ref.sub.A, Ref.sub.B, Ref.sub.C waveforms have a transition that is offset from the peak of the sawtooth, in 6 phases, an ascending phase, followed by two high states, a descending phase, and two low states. These are offset for each phase. The switch signals are timed to avoid overlapping on states between adjacent switches S1 and S2, and S4 and S5. For the positive cycle switching pulses, S3 is on, and for negative cycle switching pulses, S4 is on.

(65) The switches are mostly soft switched, leading to reduced electromagnetic interference with respect to the traditional design in which the first stage switches are hard switched at the low frequency.

(66) While the invention has been described with respect to illustrative embodiments thereof, it will be understood that various changes may be made to the embodiments without departing from the scope of the invention. Accordingly, the described embodiments are to be considered merely exemplary and the invention is not to be limited thereby.