DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME

Abstract

A display device includes: a first substrate and a second substrate including a plurality of pixel areas and opposing each other; a liquid crystal layer between the first substrate and the second substrate; a first pixel electrode on the first substrate; a first insulating layer on the first pixel electrode; and a second pixel electrode on the first insulating layer and in a different pixel area from a pixel area in which the first pixel electrode is disposed.

Claims

1. A display device comprising: a first substrate and a second substrate comprising a plurality of pixel areas and opposing each other; a liquid crystal layer between the first substrate and the second substrate; a first pixel electrode on the first substrate; a first insulating layer on the first pixel electrode; and a second pixel electrode on the first insulating layer and in a different pixel area from a pixel area in which the first pixel electrode is disposed.

2. The display device as claimed in claim 1, wherein the first pixel electrode and the second pixel electrode have substantially a same shape.

3. The display device as claimed in claim 1, further comprising a gate line extending in a first direction and a data line extending in a second direction which intersects the first direction, wherein a distance between the first pixel electrode and the second pixel electrode is less than a width of the data line in the first direction.

4. The display device as claimed in claim 3, wherein at least a portion of the first pixel electrode and at least a portion of the second pixel electrode overlap the data line.

5. The display device as claimed in claim 3, wherein a distance between the first pixel electrode and the second pixel electrode is in a range of about 0.3 μm to about 1.0 μm.

6. The display device as claimed in claim 1, further comprising a common electrode on the first substrate, the common electrode insulated from the first pixel electrode.

7. The display device as claimed in claim 1, further comprising a common electrode on the second substrate.

8. The display device as claimed in claim 1, further comprising: a second insulating layer on the second pixel electrode; and a third pixel electrode on the second insulating layer, the third pixel electrode disposed in a different pixel area from pixel areas in which the first pixel electrode and the second pixel electrode are disposed.

9. The display device as claimed in claim 3, further comprising a first black matrix extending along the gate line.

10. The display device as claimed in claim 9, further comprising a second black matrix extending along the data line.

11. The display device as claimed in claim 10, wherein the second black matrix has a smaller width than a width of the data line.

12. A method of manufacturing a display device, the method comprising: preparing a first substrate comprising a plurality of pixel areas; forming a film structure on the first substrate, the film structure comprising a plurality of thin film transistors; defining a first contact hole in the film structure, the first contact hole exposing a portion of a first thin film transistor of the thin film transistors; forming a first pixel electrode connected to the first thin film transistor through the first contact hole; coating a first insulating layer on the first substrate on which the first pixel electrode is formed; defining a second contact hole in the film structure and the first insulating layer, the second contact hole exposing a portion of a second thin film transistor of the thin film transistors; and forming a second pixel electrode connected to the second thin film transistor through the second contact hole, wherein the first pixel electrode is formed in a different pixel area from a pixel area in which the second pixel electrode is formed.

13. A method of manufacturing a display device, the method comprising: preparing a first substrate comprising a plurality of pixel areas; forming a film structure on the first substrate, the film structure comprising a plurality of thin film transistors; forming a first pixel electrode on the film structure; coating a first insulating layer on the first substrate on which the first pixel electrode is formed; defining a first contact hole and a second contact hole in the film structure and the first insulating layer, the first contact hole exposing a portion of a first thin film transistor of the thin film transistors and the second contact hole exposing a portion of a second thin film transistor of the thin film transistors; forming a bridge electrode connecting the first thin film transistor and the first pixel electrode through the first contact hole; and forming a second pixel electrode connected to the second thin film transistor through the second contact hole, wherein the first pixel electrode is formed in a different pixel area from a pixel area in which the second pixel electrode is formed.

14. The method as claimed in claim 13, wherein the forming of the bridge electrode and the forming of the second pixel electrode are substantially simultaneously performed.

15. A display device comprising: a first substrate and a second substrate comprising a plurality of pixel areas and opposing each other; a liquid crystal layer between the first substrate and the second substrate; and a first pixel electrode and a second pixel electrode on the first substrate, wherein the first pixel electrode comprises a different material from a material forming the second pixel electrode.

16. The display device as claimed in claim 15, wherein the first pixel electrode and the second pixel electrode are disposed on substantially a same layer.

17. The display device as claimed in claim 15, wherein the first pixel electrode has a different etching ratio from an etching ratio of the second pixel electrode.

18. The display device as claimed in claim 15, wherein the first pixel electrode comprises one selected from the group consisting of: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), and amorphous indium tin oxide (a-ITO).

19. The display device as claimed in claim 15, further comprising a gate line extending in a first direction and a data line extending in a second direction which intersects the first direction, wherein a distance between the first pixel electrode and the second pixel electrode is less than a width of the data line in the first direction.

20. The display device as claimed in claim 19, wherein at least a portion of the first pixel electrode and at least a portion of the second pixel electrode overlap the data line.

21. The display device as claimed in claim 19, wherein a distance between the first pixel electrode and the second pixel electrode is in a range of about 0.3 μm to about 1.0 μm.

22. A method of manufacturing a display device, the method comprising: preparing a first substrate comprising a plurality of pixel areas; forming a film structure on the first substrate, the film structure comprising a plurality of thin film transistors; coating a first pixel electrode-forming material on the film structure; patterning the first pixel electrode-forming material using a first mask to form a first pixel electrode; coating a second pixel electrode-forming material on the first substrate on which the first pixel electrode is formed; and patterning the second pixel electrode-forming material using a second mask to form a second pixel electrode, wherein the first pixel electrode-forming material comprises a different material from a material forming the second pixel electrode-forming material.

23. The method as claimed in claim 22, wherein the first pixel electrode and the second pixel electrode are formed on substantially a same layer.

24. The method as claimed in claim 22, wherein the first pixel electrode has a different etching ratio from an etching ratio of the second pixel electrode.

25. The method as claimed in claim 22, wherein the first pixel electrode comprises one selected from the group consisting of: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), and amorphous indium tin oxide (a-ITO).

26. The method as claimed in claim 22, wherein a distance between the first pixel electrode and the second pixel electrode is in a range of about 0.3 μm to about 1.0 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features and aspects of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0037] FIG. 1 is a schematic plan view illustrating an exemplary embodiment of a display device;

[0038] FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1;

[0039] FIGS. 3 and 4 are cross-sectional views illustrating alternative exemplary embodiments of a display device;

[0040] FIGS. 5, 6A, 6B, 6C, 6D, 6E, and 6F are views illustrating an exemplary embodiment of a method of manufacturing a display device;

[0041] FIGS. 7A, 7B, 7C, 7D, and 7E are views illustrating an alternative exemplary embodiment of a method of manufacturing a display device;

[0042] FIG. 8 is a schematic plan view illustrating another alternative exemplary embodiment of a display device;

[0043] FIG. 9 is a cross-sectional view taken along line of FIG. 8; and

[0044] FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H are views illustrating another alternative exemplary embodiment of a method of manufacturing a display device.

DETAILED DESCRIPTION

[0045] Features of the inventive concept and methods for achieving them will be made clear from exemplary embodiments described below in detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The inventive concept is merely defined by the scope of the claims. Therefore, well-known constituent elements, operations and techniques are not described in detail in the exemplary embodiments in order to prevent the inventive concept from being obscurely interpreted. Like reference numerals refer to like elements throughout the specification.

[0046] In the drawings, thicknesses of a plurality of layers and areas are illustrated in an enlarged manner for clarity and ease of description thereof. When a layer, area, or plate is referred to as being “on” another layer, area, or plate, it may be directly on the other layer, area, or plate, or intervening layers, areas, or plates may be present therebetween. Conversely, when a layer, area, or plate is referred to as being “directly on” another layer, area, or plate, intervening layers, areas, or plates may be absent therebetween. Further, when a layer, area, or plate is referred to as being “below” another layer, area, or plate, it may be directly below the other layer, area, or plate, or intervening layers, areas, or plates may be present therebetween. Conversely, when a layer, area, or plate is referred to as being “directly below” another layer, area, or plate, intervening layers, areas, or plates may be absent therebetween.

[0047] The spatially relative terms “below”, “beneath”, “less”, “above”, “upper”, and the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device shown in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in the other direction, and thus the spatially relative terms may be interpreted differently depending on the orientations.

[0048] Throughout the specification, when an element is referred to as being “connected” to another element, the element is “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0049] It will be understood that, although the terms “first,” “second,” “third,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, “a first element” discussed below could be termed “a second element” or “a third element,” and “a second element” and “a third element” can be termed likewise without departing from the teachings herein.

[0050] “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this application pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the present specification.

[0052] Some of the parts which are not associated with the description may not be provided in order to specifically describe embodiments, and like reference numerals refer to like elements throughout the specification.

[0053] FIG. 1 is a schematic plan view illustrating an exemplary embodiment of a display device, and FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1. FIG. 1 illustrates three pixels PX.sub.n, PX.sub.n+1, and PX.sub.n+2 that are arranged in a row along a first direction D1, for ease of description.

[0054] Referring to FIGS. 1 and 2, an exemplary embodiment of a display device includes a plurality of pixels PX.sub.n, PX.sub.n+1, and PX.sub.n+2. An exemplary embodiment of a display device includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 between the display substrate 100 and the opposing substrate 200.

[0055] In addition, an exemplary embodiment of a display device may further include a backlight unit (not illustrated) which provides light toward the display substrate 100. However, the scope of the embodiments is not limited to a liquid crystal display (LCD) device, and an exemplary embodiment may be applied to an organic light emitting diode (OLED) device, for example.

[0056] The display substrate 100 may include a first substrate 110, a gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, a gate insulating layer 120, semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, a data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, an insulating interlayer 130, a passivation layer 140, first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2, first, second, and third thin film transistors (TFTs) T.sub.n, T.sub.n+1, and T.sub.n+2, or the like. Gate wiring GE.sub.n, GE.sub.n+1, and GE.sub.n+2 are sometimes called gate electrodes GE.sub.n, GE.sub.n+1, and GE.sub.n+2, respectively. Data wiring SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 are sometimes called source electrodes SE.sub.n, SE.sub.n+1, SE.sub.n+2 and drain electrodes DE.sub.n, DE.sub.n+1, and DE.sub.n+2, respectively.

[0057] The first thin film transistor (TFT) T.sub.n may include the first gate electrode GE.sub.n, the first semiconductor layer SM.sub.n, the first source electrode SE.sub.n, and the first drain electrode DE.sub.n. The second TFT T.sub.n+1 may include the second gate electrode GE.sub.n+1, the second semiconductor layer SM.sub.n+1, the second source electrode SE.sub.n+1, and the second drain electrode DE.sub.n+1. The third TFT T.sub.n+2 may include the third gate electrode GE.sub.n+2, the third semiconductor layer SM.sub.n+2, the third source electrode SE.sub.n+2, and the third drain electrode DE.sub.n+2.

[0058] The first substrate 110 may be an insulating substrate, e.g., a plastic substrate, which has light transmitting characteristics and flexibility. However, exemplary embodiments are not limited thereto, and the first substrate 110 may include a hard substrate such as a glass substrate.

[0059] The gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 is disposed on the first substrate 110.

[0060] The gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 includes the gate line GL.sub.n extending in the first direction D1 and the first, second, and third gate electrodes GE.sub.n, GE.sub.n+1, and GE.sub.n+2 branching off from the gate line GL.sub.n.

[0061] The gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 may include or be formed of aluminum (Al) or alloys thereof, silver (Ag) or alloys thereof, copper (Cu) or alloys thereof, molybdenum (Mo) or alloys thereof, chromium (Cr), tantalum (Ta), titanium (Ti), and/or the like.

[0062] In addition, the gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 may have a multilayer structure including two or more conductive layers (not illustrated) having different physical properties. For example, a conductive layer of the multilayer structure may include or be formed of metal, e.g., an aluminum (Al)-based metal, a silver (Ag)-based metal, and a copper (Cu)-based metal, which has low resistivity to reduce signal delay or voltage drop, and another conductive layer of the multilayer structure may include a material, e.g., a molybdenum-based metal, chromium, titanium, and tantalum, which is found to impart excellent contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO).

[0063] Examples of the multilayer structure may include a chromium lower layer and an aluminum upper layer, an aluminum lower layer and a molybdenum upper layer, a titanium lower layer and a copper upper layer. However, exemplary embodiments are not limited thereto, and the gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 may include various kinds of metals and conductors. The gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 may be simultaneously provided in substantially a same process.

[0064] The gate insulating layer 120 is disposed on the first substrate 110 on which the gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2 is disposed. The gate insulating layer 120 may include silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), or the like. In addition, the gate insulating layer 120 may further include aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide.

[0065] The semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2 are disposed on the gate insulating layer 120. The semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2 may include or be formed of amorphous silicon or an oxide semiconductor including at least one (or any combination) selected from the group consisting of: gallium (Ga), indium (In), tin (Sn), and zinc (Zn). Although not illustrated, an ohmic contact layer may be disposed on the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2.

[0066] In FIG. 2, each of the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2 is depicted as substantially overlapping the first, second, and third gate electrodes GE.sub.n, GE.sub.n+1, and GE.sub.n+2. However, exemplary embodiments are not limited thereto, and the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2 may substantially overlap the data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 to be described hereinbelow.

[0067] The data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 is disposed on the first substrate 110 on which the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2 are disposed.

[0068] The data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 includes: data lines DL.sub.n, DL.sub.n+1, DL.sub.n+2, and DL.sub.n+3 extending in a second direction D2 which intersects the first direction D1; the first, second, and third source electrodes SE.sub.n, SE.sub.n+1, and SE.sub.n+2 branching off from the data lines DL.sub.n, DL.sub.n+1, and DL.sub.n+2 to overlap the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2; and the first, second, and third drain electrodes DE.sub.n, DE.sub.n+1, DE.sub.n+2 spaced apart from the first, second, and third source electrodes SE.sub.n, SE.sub.n+1, and SE.sub.n+2 to overlap the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2. The data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 may include substantially a same material as that included in the gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, GE.sub.n+2. The data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 may be simultaneously provided in substantially a same process.

[0069] The insulating interlayer 130 is disposed on the first substrate 110 on which the data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2 is disposed. The insulating interlayer 130 may have a monolayer structure or a multilayer structure including, for example, silicon oxide, silicon nitride, a photosensitive organic material, or a low dielectric constant insulating material such as a-Si:C:O or a-Si:O:F.

[0070] The passivation layer 140 is disposed on the insulating interlayer 130. The passivation layer 140 may have a monolayer structure or a multilayer structure including, for example, silicon oxide, silicon nitride, a photosensitive organic material, or a silicon-based low dielectric constant insulating material.

[0071] However, exemplary embodiments are not limited thereto, and in the case of a color filter on array (COA) structure in which a color filter is disposed on the first substrate 110, a color filter may be provided in lieu of the passivation layer 140, or a color filter may be disposed between the insulating interlayer 130 and the passivation layer 140.

[0072] The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 are disposed in different pixel areas, respectively, on the passivation layer 140. The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 are disposed adjacent to one another with respect to respective ones of the data lines DL.sub.n, DL.sub.n+1 and DL.sub.n+2. In an exemplary embodiment, the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may have substantially a same shape, but exemplary embodiments are not limited thereto. In an alternative exemplary embodiment, the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may have different shapes from one another.

[0073] Each of the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may have a length in the first direction D1 in a range of about 3.0 μm to about 5.0 μm, and may have a length in the second direction D2 in a range of about 10.0 μm to about 12.0 μm.

[0074] For example, the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 may be disposed in an odd-numbered column, and the second pixel electrode PE.sub.n+1 may be disposed in an even-numbered column; however, exemplary embodiments are not limited thereto.

[0075] Each of the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 may pass through the insulating interlayer 130 and the passivation layer 140 to be connected to the first drain electrode DE.sub.n and the third drain electrode DE.sub.n+2.

[0076] A first insulating layer 150 may be disposed over an entire surface of the first substrate 110 on which the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 are formed. The firs insulating layer 150 may include silicon oxide (SiO.sub.x) or silicon nitride (SiN.sub.x).

[0077] The second pixel electrode PE.sub.n+1 is disposed on the first insulating layer 150. The second pixel electrode PE.sub.n+1 passes through the insulating interlayer 130, the passivation layer 140, and the first insulating layer 150 to be connected to the second drain electrode DE.sub.n+1.

[0078] The first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1, adjacently disposed with respect to the data line DL.sub.n+1, are disposed in different layers, respectively, due to the first insulating layer 150 such that the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may have a significantly small distance from each other regardless of a resolution limit of an exposure.

[0079] For example, a distance W.sub.PE from a plane between the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may be in a range of about 0.3 μm to about 1.0 μM.

[0080] In general, the data lines DL.sub.n, DL.sub.n+1, DL.sub.n+2, and DL.sub.n+3 have a width W.sub.DL in a range of about 0.8 μm to about 1.2 μm, and thus the distance W.sub.PE between the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 is less than the width W.sub.DL of the data lines DL.sub.n, DL.sub.n+2, and DL.sub.n+3.

[0081] Accordingly, at least a portion of the first pixel electrode PE.sub.n and at least a portion of the second pixel electrode PE.sub.n+1 overlap the data line DL.sub.n+1 from a plane, and at least a portion of the second pixel electrode PE.sub.n+1 and at least a portion of the third pixel electrode PE.sub.n+2 may overlap the data line DL.sub.n+2 from a plane.

[0082] The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may include or be formed of a transparent conductive material. For example, the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may include at least one (or any combination) selected from the group consisting of: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), and amorphous indium tin oxide (a-ITO).

[0083] A lower alignment layer (not illustrated) may be disposed on the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2. The lower alignment layer may be a homeotropic alignment layer or a photoalignment layer including a photopolymerizable material.

[0084] The opposing substrate 200 may include a second substrate 210, black matrixes 220a and 220b, color filters 230R, 230G, and 230B, a common electrode CE, or the like.

[0085] The second substrate 210 may be an insulating substrate, e.g., a plastic substrate, having light transmitting characteristics and flexibility. However, exemplary embodiments are not limited thereto, and the second substrate 210 may include a hard substrate such as a glass substrate.

[0086] The black matrixes 220a and 220b may be disposed on the second substrate 210.

[0087] The black matrixes 220a and 220b may include the first black matrix 220a extending in the first direction D1 along the gate line GL.sub.n and the second black matrix 220b extending in the second direction D2 along the data lines DL.sub.n, DL.sub.n+1, DL.sub.n+2, and DL.sub.n+3. The second black matrix 220b may have a smaller width than a width of the data lines DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, and may be omitted.

[0088] In addition, in the case of a black matrix on array (BOA) structure in which a light blocking member is disposed on the first substrate 110, the black matrixes 220a and 220b may be disposed on the first substrate 110.

[0089] The black matrixes 220a and 220b may include or be formed of a photosensitive composition. Examples of the photosensitive composition may include: a binder resin, a polymerizable monomer, a polymerizable oligomer, a pigment, a dispersant, and a photoinitiator. The pigment may use a black pigment, a black resin, or the like.

[0090] The color filters 230R, 230G, and 230B are disposed on the black matrixes 220a and 220b.

[0091] The color filters 230R, 230G, and 230B may be one selected from: a red color filter, a green color filter, a blue color filter, a cyan color filter, a magenta color filter, a yellow color filter, and a white color filter. Three primary colors of red, green, and blue or cyan, magenta, and yellow may define a basic pixel group for forming a color.

[0092] The common electrode CE is disposed on the second substrate 210 on which the color filters 230R, 230G, and 230B are disposed. However, exemplary embodiments are not limited thereto, and the common electrode CE may be disposed on the first substrate 110 (refer to FIG. 3).

[0093] The common electrode CE may be a whole planar electrode including a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO). In an alternative exemplary embodiment, the common electrode CE may have an uneven portion or at least one slit to define a plurality of domains.

[0094] An upper alignment layer (not illustrated) may be disposed on the common electrode CE. The upper alignment layer (not illustrated) may be a homeotropic alignment layer or a photoalignment layer including a photopolymerizable material.

[0095] FIG. 3 is a cross-sectional view illustrating an alternative exemplary embodiment of a display device. Descriptions with regard to configurations of an exemplary embodiment of a display device will not be repeated and thus be omitted in descriptions with regard to configurations of an alternative exemplary embodiment of a display device.

[0096] Referring to FIGS. 1 and 3, a gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, a gate insulating layer 120, semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, a data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, and an insulating interlayer 130 are sequentially disposed on a first substrate 110. A first passivation layer 140a, a common electrode CE, and a second passivation layer 140b are sequentially disposed on the insulating interlayer 130.

[0097] The first passivation layer 140a and the second passivation layer 140b may have a monolayer structure or a multilayer structure including, for example, silicon oxide, silicon nitride, a photosensitive organic material, a silicon-based low dielectric constant insulating material, or the like.

[0098] The common electrode CE and the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, PE.sub.n+2 form a fringe field, having the second passivation layer 140b thereamong, thereby adjusting an alignment direction of a liquid crystal layer 300. The common electrode CE may be disposed over an entire surface of the first substrate 110 except an area in which TFTs T.sub.n, T.sub.n+1, and T.sub.n+2 are formed.

[0099] The first and third pixel electrodes PE.sub.n and PE.sub.n+2, the first insulating layer 150, and the second pixel electrode PE.sub.n+1 are sequentially disposed on the second passivation layer 140b. A lower alignment layer (not illustrated) may be disposed on the first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, PE.sub.n+2. The lower alignment layer may be a homeotropic alignment layer.

[0100] An opposing substrate 200 may include a second substrate 210, black matrixes 220a and 220b, and color filters 230R, 230G, and 230B, for example. The black matrixes 220a and 220b and the color filters 230R, 230G, and 230B are sequentially disposed on the second substrate 210, and an upper alignment layer (not illustrated) may be disposed on the color filters 230R, 230G, and 230B. The upper alignment layer may be a homeotropic alignment layer.

[0101] FIG. 4 is a cross-sectional view illustrating another alternative exemplary embodiment of a display device. Descriptions with regard to configurations of an exemplary embodiment of a display device will not be repeated and thus be omitted in descriptions with regard to configurations of another alternative exemplary embodiment of a display device.

[0102] Referring to FIGS. 1 and 4, a gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, a gate insulating layer 120, semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, a data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, an insulating interlayer 130, and a passivation layer 140 are sequentially disposed on a first substrate 110.

[0103] First, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 are disposed in different pixel areas, respectively, on the passivation layer 140. The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may be disposed adjacent to one another with respect to respective ones of data lines DL.sub.n+1 and DL.sub.n+2.

[0104] For example, the first pixel electrode PE.sub.n may be disposed in a first column, the second pixel electrode PE.sub.n+1 may be disposed in a second column, and the third pixel electrode PE.sub.n+2 may be disposed in a third column; however, exemplary embodiments are not limited thereto.

[0105] The first pixel electrode PE.sub.n may pass through the insulating interlayer 130 and the passivation layer 140 to be connected to a first drain electrode DE.sub.n, and a first insulating layer 150 may be disposed over an entire surface of the first substrate 110 on which the first pixel electrode PE.sub.n is formed.

[0106] In addition, the second pixel electrode PE.sub.n+1 may pass through the insulating interlayer 130, the passivation layer 140, and the first insulating layer 150 to be connected to a second drain electrode DE.sub.n+1, and a second insulating layer 160 may be disposed over the entire surface of the first substrate 110 on which the second pixel electrode PE.sub.n+1 is formed.

[0107] In addition, the third pixel electrode PE.sub.n+2 may pass through the insulating interlayer 130, the passivation layer 140, the first insulating layer 150, and the second insulating layer 160 to be connected to a third drain electrode DE.sub.n+2.

[0108] The first insulating layer 150 and the second insulating layer 160 may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0109] An opposing substrate 220 may include a second substrate 210, black matrixes 220a and 220b, color filters 230R, 230G, and 230B, and a common electrode CE, for example.

[0110] FIGS. 5, 6A, 6B, 6C, 6D, 6E, and 6F are views illustrating an exemplary embodiment of a method of manufacturing a display device. FIGS. 6A, 6B, 6C, 6D, 6E, and 6F are cross-sectional views taken along line II-IP of FIG. 5.

[0111] Referring to FIGS. 5 and 6A, a film structure FS including a plurality of TFTs T.sub.n and T.sub.n+1 is formed on a first substrate 110 which includes transparent glass or plastic.

[0112] For example, a gate wiring including first and second gate electrodes GE.sub.n and GE.sub.n+1 is formed on the first substrate 110. A gate insulating layer 120 is disposed over an entire surface of the first substrate 110 on which the gate wiring is formed.

[0113] Semiconductor layers SM.sub.n and SM.sub.n+1 overlapping at least a portion of the first and second gate electrodes GE.sub.n and GE.sub.n+1 are formed on the gate insulating layer 120. Subsequently, a data wiring including a data line DL.sub.n+1, first and second source electrodes SE.sub.n and SE.sub.n+1, and first and second drain electrodes DE.sub.n and DE.sub.n+1 is formed on the first substrate 110 on which the semiconductor layers SM.sub.n and SM.sub.n+1 are formed.

[0114] An insulating interlayer 130 is formed over the entire surface of the first substrate 110 on which the data wiring SE.sub.n, SE.sub.n+1, DE.sub.n, and DE.sub.n+1 is formed, and subsequently, a passivation layer 140 is formed on the insulating interlayer 130.

[0115] Referring to FIGS. 5 and 6B, a first contact hole H1 which passes through the insulating interlayer 130 and the passivation layer 140 to extend to and expose a portion of the first drain electrode DE.sub.n is defined. The first contact hole H1 may be defined in a pixel area to be formed with a first pixel electrode PE.sub.n to be described hereinbelow.

[0116] Referring to FIGS. 5 and 6C, the first pixel electrode PE.sub.n connected to the first drain electrode DE.sub.n through the first contact hole H1 is formed. At least a portion of the first pixel electrode PE.sub.n may be formed to overlap the data line DL.sub.n+1.

[0117] Referring to FIGS. 5 and 6D, a first insulating layer 150 is formed over the entire surface of the first substrate 110 on which the first pixel electrode PE.sub.n is formed.

[0118] Referring to FIGS. 5 and 6E, a second contact hole H2 which passes through the insulating interlayer 130, the passivation layer 140, and the first insulating layer 150 to extend to and expose a portion of the second drain electrode DE.sub.n+1 is defined. The second contact hole H2 may be defined in a pixel area to be formed with a second pixel electrode PE.sub.n+1 to be described hereinbelow.

[0119] Referring to FIGS. 5 and 6F, the second pixel electrode PE.sub.n+1 connected to the second drain electrode DE.sub.n+1 through the second contact hole H2 is formed. At least a portion of the second pixel electrode PE.sub.n+1 may be formed to overlap the data line DL.sub.n+1. The first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may be formed respectively in different pixel areas adjacent to one another.

[0120] FIGS. 7A, 7B, 7C, 7D, and 7E are views illustrating an alternative exemplary embodiment of a method of manufacturing a display device. Descriptions with regard to configurations of an exemplary embodiment of a display device will not be repeated and thus be omitted in descriptions with regard to configurations of an alternative exemplary embodiment of a display device.

[0121] Referring to FIG. 7A, a film structure FS including a plurality of TFTs T.sub.n and T.sub.n+1 is formed on a first substrate 110.

[0122] Referring to FIG. 7B, a first pixel electrode PE.sub.n is formed on a passivation layer 140. At least a portion of the first pixel electrode PE.sub.n may be formed to overlap a data line DL.sub.n+1.

[0123] Referring to FIG. 7C, a first insulating layer 150 is formed over an entire surface of the first substrate 110 on which the first pixel electrode PE.sub.n is formed.

[0124] Referring to FIG. 7D, a first contact hole H1 which passes through an insulating interlayer 130, the passivation layer 140, the first pixel electrode PE.sub.n, and the first insulating layer 150 to extend to and expose a portion of a first drain electrode DE.sub.n and a second contact hole H2 which passes through the insulating interlayer 130, the passivation layer 140, and the first insulating layer 150 to extend to and expose a portion of a second drain electrode DE.sub.n+1 are defined.

[0125] The first contact hole H1 may be defined in a pixel area to be formed with the first pixel electrode PE.sub.n and the second contact hole H2 may be defined in a pixel area to be formed with a second pixel electrode PE.sub.n+1.

[0126] Referring to FIG. 7E, a bridge electrode BE connecting the first drain electrode DE.sub.n and the first pixel electrode PE.sub.n through the first contact hole H1 is formed. The second pixel electrode PE.sub.n+1 connected to the second drain electrode DE.sub.n+1 through the second contact hole H2 is formed. At least a portion of the second pixel electrode PE.sub.n+1 may be formed to overlap the data line DL.sub.n+1. The first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may be respectively formed in different pixel areas adjacent to one another.

[0127] The bridge electrode BE and the second pixel electrode PE.sub.n+1 may include substantially a same material and may be simultaneously provided in substantially a same process.

[0128] FIG. 8 is a schematic plan view illustrating another alternative exemplary embodiment of a display device, and FIG. 9 is a cross-sectional view taken along line of FIG. 8. Descriptions with regard to configurations of an exemplary embodiment of a display device will not be repeated and thus be omitted in descriptions with regard to configurations of another alternative exemplary embodiment of a display device. FIG. 8 illustrates three pixels PX.sub.n, PX.sub.n+1, and PX.sub.n+2 that are arranged in a row along a first direction D1, for ease of description.

[0129] Referring to FIGS. 8 and 9, another alternative exemplary embodiment of a display device includes the plurality of pixels PX.sub.n, PX.sub.n+1, and PX.sub.n+2. Another alternative exemplary embodiment of a display device includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 between the display substrate 100 and the opposing substrate 200.

[0130] The display substrate 100 may include a first substrate 110, a gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, a gate insulating layer 120, semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, a data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, an insulating interlayer 130, a passivation layer 140, first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2, first, second, and third TFTs T.sub.n, T.sub.n+1, and T.sub.n+2, or the like.

[0131] The first TFT T.sub.n may include a first gate electrode GE.sub.n, a first semiconductor layer SM.sub.n, a first source electrode SE.sub.n, and a first drain electrode DE.sub.n. The second TFT T.sub.n+1 may include a second gate electrode GE.sub.n+1, a second semiconductor layer SM.sub.n+1, a second source electrode SE.sub.n+1, and a second drain electrode DE.sub.n+1. The third TFT T.sub.n+2 may include a third gate electrode GE.sub.n+2, a third semiconductor layer SM.sub.n+2, a third source electrode SE.sub.n+2, and a third drain electrode DE.sub.n+2.

[0132] The gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, the gate insulating layer 120, the semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, the data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, the insulating interlayer 130, and the passivation layer 140 are sequentially disposed on the first substrate 110.

[0133] The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, PE.sub.n+2 are disposed in different pixel areas, respectively, on the passivation layer 140. The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 are disposed on substantially a same layer. The first, second, and third pixel electrodes PE.sub.n, PE.sub.n+1, and PE.sub.n+2 may be disposed adjacent to one another with respect to respective ones of data lines DL.sub.n+1 and DL.sub.n+2.

[0134] For example, the first pixel electrode PE.sub.n may be disposed in a first column, the second pixel electrode PE.sub.n+1 may be disposed in a second column, and the third pixel electrode PE.sub.n+2 may be disposed in a third column; however, exemplary embodiments are not limited thereto.

[0135] Each of the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1, adjacent to one another, may include different materials, respectively. For example, the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may respectively include materials each having different etching ratios.

[0136] Similarly, the second pixel electrode PE.sub.n+1 and the third pixel electrode PE.sub.n+2, adjacent to one another, may include different materials. For example, the second pixel electrode PE.sub.n+1 and the third pixel electrode PE.sub.n+2 may respectively include materials each having different etching ratios.

[0137] It is assumed that in an exemplary embodiment of a display device, the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 include substantially a same material, and the second pixel electrode PE.sub.n+1 includes a different material from a material included in the first pixel electrode PE.sub.n or the third pixel electrode PE.sub.n+2; however, exemplary embodiments are not limited thereto.

[0138] Each of the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may include at least one (or any combination) selected from the group consisting of: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), and amorphous indium tin oxide (a-ITO). For example, in a case where the first pixel electrode PE.sub.n is indium tin oxide (ITO), the second pixel electrode PE.sub.n+1 may be amorphous indium tin oxide (a-ITO).

[0139] The first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1, which are adjacent to one another with respect to the data line DL.sub.n+1, may respectively include materials each having different etching ratios and thus may have a significantly small distance from each other regardless of a resolution limit of an exposure.

[0140] For example, a distance W.sub.PE from a plane between the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may be in a range of about 0.3 μm to about 1.0 μm.

[0141] In general, the data line DL.sub.n+1 has a width W.sub.DL in a range of about 0.8 μm to about 1.2 μm, and thus the distance W.sub.PE between the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 is less than the width W.sub.DL of the data line DL.sub.n+1. Accordingly, at least a portion of the first pixel electrode PE.sub.n and at least a portion of the second pixel electrode PE.sub.n+1 may overlap the data line DL.sub.n+1 from a plane.

[0142] FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H are views illustrating another alternative exemplary embodiment of a method of manufacturing a display device. Descriptions with regard to configurations of an exemplary embodiment of a method of manufacturing a display device will not be repeated and thus be omitted in descriptions with regard to configurations of another alternative exemplary embodiment of a method of manufacturing a display device.

[0143] Referring to FIGS. 8 and 10A, a film structure FS including a plurality of TFTs T.sub.n, T.sub.n+1, and T.sub.n+2 is formed on a first substrate 110.

[0144] For example, a gate wiring GL.sub.n, GE.sub.n, GE.sub.n+1, and GE.sub.n+2, a gate insulating layer 120, semiconductor layers SM.sub.n, SM.sub.n+1, and SM.sub.n+2, a data wiring DL.sub.n, DL.sub.n+1, DL.sub.n+2, DL.sub.n+3, SE.sub.n, SE.sub.n+1, SE.sub.n+2, DE.sub.n, DE.sub.n+1, and DE.sub.n+2, an insulating interlayer 130, and a passivation layer 140 may be sequentially formed on the first substrate 110.

[0145] Subsequently, a first contact hole H1 which passes through the insulating interlayer 130 and the passivation layer 140 to extend to and expose a portion of a first drain electrode DE.sub.n is defined. The first contact hole H1 may be defined in a pixel area to be formed with a first pixel electrode PE.sub.n.

[0146] Subsequently, a first pixel electrode-forming material PE1 is formed on the passivation layer 140. The first pixel electrode-forming material PE1 passes through the first contact hole H1 to be connected to the first drain electrode DE.sub.n. The first pixel electrode-forming material PE1 may include at least one (or any combination) selected from the group consisting of: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), and amorphous indium tin oxide (a-ITO).

[0147] Referring to FIGS. 8 and 10B, a first photosensitive composition PR1 is coated over the first pixel electrode-forming material PE1. The first photosensitive composition PR1 may be a photosensitive resin composition of a positive type or a negative type. Hereinbelow, it is assumed that the first photosensitive composition PR1 is a positive type photosensitive composition in which an exposed portion is developed and an unexposed portion remains.

[0148] The first photosensitive composition PR1 may include a binder resin, a polymerizable monomer, a polymerizable oligomer, a pigment, a dispersant, and a photoinitiator, for example. The pigment may use a black pigment or a black resin.

[0149] A first exposure mask 501 is disposed above the first photosensitive composition PR1 to be spaced apart from the first photosensitive composition PR1, and a light L is irradiated to the first photosensitive composition PR1 through the first exposure mask 501 to perform light exposure.

[0150] The first exposure mask 501 includes a transmissive portion 510 and a light blocking portion 520. The transmissive portion 510 is disposed above an area except an area to be formed with the first pixel electrode PE.sub.n and a third pixel electrode PE.sub.n+2, and the light blocking portion 520 is disposed above the area to be formed with the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2.

[0151] Referring to FIGS. 8 and 10C, an unexposed portion of the first photosensitive composition PR1 is developed, using a developing solution, and cured such that a first etching prevention layer PR1′ is formed. That is, a portion of the first photosensitive composition PR1 below the transmissive portion 510 of the first exposure mask 501 is removed.

[0152] Referring to FIG. 10D, the first pixel electrode-forming material PE1 is patterned using a first etchant. A portion of the first pixel electrode-forming material PE1 on an area absent the first photosensitive composition PR1 is removed such that the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 are formed.

[0153] Referring to FIGS. 8 and 10E, a second pixel electrode-forming material PE2 is formed on the passivation layer 140 on which the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 are formed.

[0154] The second pixel electrode-forming material PE2 includes a different material from a material included in the first pixel electrode-forming material PE1. For example, the second pixel electrode-forming material PE2 may include a material having a different etching ratio from an etching ratio of a material included in the first pixel electrode-forming material PE1.

[0155] Referring to FIGS. 8 and 10F, a second photosensitive composition PR2 is coated on the second pixel electrode-forming material PE2. The second photosensitive composition PR2 may be a photosensitive resin composition of a positive type or a negative type. Hereinbelow, it is assumed that the second photosensitive composition PR2 is a positive type photosensitive composition in which an exposed portion is developed and an unexposed portion remains.

[0156] A second exposure mask 502 is disposed above the second photosensitive composition PR2 to be spaced apart from the second photosensitive composition PR2, and a light L is irradiated to the second photosensitive composition PR2 through the second exposure mask 502 to perform light exposure.

[0157] The second exposure mask 502 includes a transmissive portion 510 and a light blocking portion 520. The transmissive portion 510 is disposed above an area except an area to be formed with a second pixel electrode PE.sub.n+1, and the light blocking portion 520 is disposed above the area to be formed with the second pixel electrode PE.sub.n+1.

[0158] Referring to FIGS. 8 and 10G, an unexposed portion of the second photosensitive composition PR2 is developed, using a developing solution, and cured such that a second etching prevention layer PR2′ is formed. That is, a portion of the second photosensitive composition PR2 below the transmissive portion 510 of the second exposure mask 502 is removed.

[0159] In such an exemplary embodiment, the second etching prevention layer PR2′ is formed to be spaced apart from the first pixel electrode PE.sub.n and the third pixel electrode PE.sub.n+2 at a distance in a range of about 0.3 μm to about 1.0 μm from a plane.

[0160] Referring to FIGS. 8 and 10H, the second pixel electrode-forming material PE2 is patterned using a second etchant. A portion of the second pixel electrode-forming material PE2 on an area absent the second photosensitive composition PR2 is removed such that the second pixel electrode PE.sub.n+1 is formed. The second etchant may have a different etching ratio than that of the first etchant. The first etchant and the second etchant may be a combined material of hydrochloric acid, acetic acid, deionized water, and a surfactant.

[0161] As such, in another alternative exemplary embodiment of a display device, the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1, adjacent to one another, respectively include materials each having different etching ratios such that the first pixel electrode PE.sub.n and the second pixel electrode PE.sub.n+1 may have a significantly small distance from each other regardless of a resolution limit of an exposure.

[0162] As set forth hereinabove, in one or more exemplary embodiments of a display device, a distance among pixel electrodes may be less than or equal to a resolution limit of an exposure and thus display devices having an ultra-high resolution of about 2000 pixel per inch (ppi) or higher may be realized.

[0163] From the foregoing, it will be appreciated that various embodiments in accordance with the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present teachings. Accordingly, the various embodiments disclosed herein are not intended to be limiting of the true scope and spirit of the present teachings. Various features of the above described and other embodiments can be mixed and matched in any manner, to produce further embodiments consistent with the inventive concept.