APPARATUS AND METHODS FOR PARALLEL TESTING OF DEVICES

Abstract

Apparatus and methods for reducing device testing times, such as missile testing times, are disclosed. The apparatus and methods may execute tests or portions of tests in a parallel manner. The apparatus and methods ensure that tests or portions of tests executing in parallel do not interfere with one another. The apparatus and methods may assess the current state of the test environment to confirm whether it is acceptable to advance one or more tests. If the testing environment is not acceptable for a test to continue executing, the apparatus and methods do not allow the test to advance. The testing environment may be monitored by measuring one or more vital signs, where the vital signs may indicate whether it is safe for a particular test to advance. As such, the apparatus and methods provide an efficient way to test devices such as missiles.

Claims

1. A test system comprising: a test missile; an electronic device operably coupled to the test missile and comprising: first stage concurrent determination test logic configured to: determine that a plurality of first stage tests to be executed on the test missile do not require a missile target or high pressure gas for testing of the test missile; concurrently execute the plurality of first stage tests on the test missile by determining when data will be made available for each of the plurality of first stage tests and executing a portion of the plurality of first stage tests that may be completed before the data is made available for each of the plurality of first stage tests; and provide an indication of whether the plurality of first stage tests completed successfully; second stage concurrent determination test logic configured to: determine that a plurality of second stage tests to be executed on the test missile require a first type missile target and high pressure gas for testing of the test missile; concurrently execute the plurality of second stage tests on the test missile by determining when data will be made available for each of the plurality of second stage tests and executing a portion of the plurality of second stage tests that may be completed before the data is made available for each of the plurality of second stage tests; and provide an indication of whether the plurality of second stage tests completed successfully; and third stage concurrent determination test logic configured to: determine that a plurality of third stage tests to be executed on the test missile require a second type missile target for testing of the test missile; concurrently execute the plurality of third stage tests on the test missile by determining when data will be made available for each of the plurality of third stage tests and executing a portion of the plurality of third stage tests that may be completed before the data is made available for each of the plurality of third stage tests; and provide an indication of whether the plurality of third stage tests completed successfully.

2. The test system of claim 1 wherein the electronic device comprises gyro spin test logic for executing a gyro spin test, wherein the plurality of first stage tests comprise the gyro spin test, wherein the gyro spin test logic is operable to: provide the test missile with a first test signal; determine a gyro spin frequency of a gyro of the test missile based on a first received signal from the test missile after a first minimum threshold amount of time; determine a gyro spin time of the gyro of the test missile based on the first received signal from the test missile; and determine whether the determined gyro spin frequency is within a gyro spin frequency range and whether the determined gyro spin time falls within a gyro spin time range, wherein: if the determined gyro spin frequency is within the gyro spin frequency range and the determined gyro spin time is within the gyro spin time range, the gyro spin test logic provides an indication that the gyro spin test completed successfully; and if the determined gyro spin frequency is not within the gyro spin frequency range or the determined gyro spin time is not within the gyro spin time range, the gyro spin test logic provides an indication that the gyro spin test has failed.

3. The test system of claim 2 wherein the electronic device comprises gyro spin frequency test logic for executing a gyro spin frequency test, wherein the plurality of first stage tests comprise the gyro spin frequency test, wherein the gyro spin frequency test logic is operable to: determine a gyro spin frequency of the gyro of the test missile based on a second received signal from the test missile after a second minimum threshold amount of time; and determine whether the determined gyro spin frequency is within a gyro spin frequency range, wherein: if the determined gyro spin frequency is within the gyro spin frequency range, the gyro spin frequency test logic provides an indication that the gyro spin frequency test completed successfully; and if the determined gyro spin frequency is not within the gyro spin frequency range, the gyro spin frequency test logic provides an indication that the gyro spin frequency test has failed.

4. The test system of claim 3 wherein the electronic device comprises gyro spin direction test logic for executing a gyro spin direction test, wherein the plurality of first stage tests comprise the gyro spin direction test, wherein the gyro spin direction test logic is operable to determine a gyro spin direction of the gyro of the test missile.

5. The test system of claim 1 wherein the electronic device comprises digital word sensing test logic for executing a digital word sensing test, wherein the plurality of first stage tests comprise the digital word sensing test, wherein the digital word sensing test logic is operable to: determine whether a digital word in signal occurred based on a first received signal from the test missile after a minimum threshold amount of time; determine whether a digital word out signal occurred based on a second received signal from the test missile after the minimum threshold amount of time; wherein: if the digital word in signal occurred and the digital word out signal occurred, the digital word sensing test logic provides an indication that the digital word sensing test completed successfully; and otherwise the digital word sensing test logic provides an indication that the digital word sensing test has failed.

6. The test system of claim 1 wherein the electronic device comprises chirp test logic for executing a chirp test, wherein the plurality of first stage tests comprise the chirp test, wherein the chirp test logic is operable to: periodically determine an audio out signal level based on a received audio out signal from the test missile over a period of time; and determine a number of times that the measured audio out signal level exceeds an audio out signal level threshold, wherein: if the determined number of times that the measured audio out signal level exceeds the audio out signal level threshold is greater than a maximum threshold, the audio out signal level test logic provides an indication that the audio out signal level test failed; and otherwise the audio out signal level test logic provides an indication that the audio out signal level test completed successfully.

7. The test system of claim 1 wherein the electronic device comprises operating current test logic for executing an operating current test, wherein the plurality of first stage tests comprise the operating current test, wherein the operating current test logic is operable to: determine an operating current based on a received signal from the test missile; determine whether the operating current is within an operating current range; and determine a number of how many of the plurality of first stage tests are completed, wherein: if the operating current is not within the operating current range or a determined number of the plurality of first stage tests are not completed, the operating current test logic provides an indication that the operating current test has failed; and if the operating current is within the operating current range and the determined number of the plurality of first stage tests are completed, the operating current test logic provides an indication that the operating current test completed successfully.

8. The test system of claim 1 wherein the electronic device comprises gas flow rate test logic for executing a gas flow rate test, wherein the plurality of second stage tests comprise the gas flow rate test, wherein the gas flow rate test logic is operable to: determine a gas flow rate based on one or more received signals from the test missile after a minimum threshold amount of time; and determine whether the gas flow rate is within a gas flow rate range, wherein: if the gas flow rate is within the gas flow rate range, the gas flow rate test logic provides an indication that the gas flow rate test completed successfully; and otherwise the gas flow rate test logic provides an indication that the gas flow rate test has failed.

9. The test system of claim 1 wherein the electronic device comprises functional cool down test logic for executing a functional cool down test, wherein the plurality of second stage tests comprise the functional cool down test, wherein the functional cool down test logic is operable to determine whether the test missile acquires tracking of the first type missile target before a maximum threshold amount of time has expired based on a first received signal from the test missile, wherein: if the test missile acquires tracking of the first type missile target before the maximum threshold amount of time expires, the functional cool down test logic provides an indication that the functional cool down test completed successfully; and otherwise the functional cool down test logic provides an indication that the functional cool down test has failed.

10. The test system of claim 9 wherein the electronic device comprises tracking sensitivity test logic for executing a tracking sensitivity test, wherein the plurality of second stage tests comprise the tracking sensitivity test, wherein the tracking sensitivity test logic is operable to determine whether the test missile maintains acquisition of the first type missile target for a minimum threshold amount of time based on a second received signal from the test missile, wherein: if the test missile maintains acquisition of the first type missile target for the minimum threshold amount of time, the tracking sensitivity test logic provides an indication that the tracking sensitivity test completed successfully; and otherwise the tracking sensitivity test logic provides an indication that the tracking sensitivity test has failed.

11. The test system of claim 1 wherein the electronic device comprises positive quiescent current test logic for executing a positive quiescent current test, wherein the plurality of third stage tests comprise the positive quiescent current test, wherein the positive quiescent current test logic is operable to determine a positive quiescent current level of the test missile while the test missile is tracking the second missile type target based on a received signal from the test missile, wherein: if the positive quiescent current level is within a positive quiescent current range, the positive quiescent current test logic provides an indication that the positive quiescent current test completed successfully; and otherwise the positive quiescent current test logic provides an indication that the positive quiescent current test has failed.

12. The test system of claim 1 wherein the electronic device comprises negative quiescent current test logic for executing a negative quiescent current test, wherein the plurality of third stage tests comprise the negative quiescent current test, wherein the negative quiescent current test logic is operable to determine a negative quiescent current level of the test missile while the test missile is tracking the second missile type target based on a received signal from the test missile, wherein: if the negative quiescent current level is within a negative quiescent current range, the negative quiescent current test logic provides an indication that the negative quiescent current test completed successfully; and otherwise the negative quiescent current test logic provides an indication that the negative quiescent current test has failed.

13. The test system of claim 1 wherein the electronic device comprises clockwise tracking capability test logic for executing a clockwise tracking capability test, wherein the plurality of third stage tests comprise the clockwise tracking capability test, wherein the clockwise tracking capability test logic is operable to determine whether the test missile maintains acquisition of the second type missile target for a minimum threshold amount of time based on a received signal from the test missile, wherein: if the test missile maintains acquisition of the second type missile target for the minimum threshold amount of time, the clockwise tracking capability test logic provides an indication that the clockwise tracking capability test completed successfully; and otherwise the clockwise tracking capability test logic provides an indication that the clockwise tracking capability test has failed.

14. The test system of claim 1 wherein the electronic device comprises caging capability test logic for executing a caging capability test, wherein the plurality of third stage tests comprise the caging capability test, wherein the caging capability test logic is operable to: provide an indication to the test missile to cease tracking the second missile target type and return to an off-axis position; determine, based on one or more received signals from the test missile, whether the test missile loses acquisition of the second missile target type and returns to an off-axis position, wherein: if the test missile loses acquisition of the second missile target type and returns to an off-axis position, the caging capability test logic provides an indication that the caging capability test completed successfully; and otherwise the caging capability test logic provides an indication that the caging capability test has failed.

15. A method in an electronic device comprising: determining that a plurality of first stage tests to be executed on a test missile do not require a missile target or high pressure gas for testing of the test missile; concurrently executing the plurality of first stage tests on the test missile by determining when data will be made available for each of the plurality of first stage tests and executing a portion of the plurality of first stage tests that may be completed before the data is made available for each of the plurality of first stage tests; determining that a plurality of second stage tests to be executed on the test missile require a first type missile target and high pressure gas for testing of the test missile; concurrently executing the plurality of second stage tests on the test missile by determining when data will be made available for each of the plurality of second stage tests and executing a portion of the plurality of second stage tests that may be completed before the data is made available for each of the plurality of second stage tests; determining that a plurality of third stage tests to be executed on the test missile require a second type missile target for testing of the test missile; and concurrently executing the plurality of third stage tests on the test missile by determining when data will be made available for each of the plurality of third stage tests and executing a portion of the plurality of third stage tests that may be completed before the data is made available for each of the plurality of third stage tests; and providing an indication of whether the plurality of first stage tests, plurality of second stage tests, and plurality of third stage tests completed successfully.

16. The method of claim 15 wherein concurrently executing the plurality of first stage tests on the test missile comprises: providing the test missile with a first test signal; determining a gyro spin frequency of a gyro of the test missile based on a first received signal from the test missile after a first minimum threshold amount of time; determining a gyro spin time of the gyro of the test missile based on the first received signal from the test missile; and determining whether the determined gyro spin frequency is within a gyro spin frequency range and whether the determined gyro spin time falls within a gyro spin time range, wherein: if the determined gyro spin frequency is within the gyro spin frequency range and the determined gyro spin time is within the gyro spin time range, providing an indication that a gyro spin test completed successfully; and if the determined gyro spin frequency is not within the gyro spin frequency range or the determined gyro spin time is not within the gyro spin time range providing an indication that the gyro spin test has failed.

17. The method of claim 16 wherein concurrently executing the plurality of first stage tests on the test missile comprises: determining a gyro spin frequency of the gyro of the test missile based on a second received signal from the test missile after a second minimum threshold amount of time; and determining whether the determined gyro spin frequency is within a gyro spin frequency range, wherein: if the determined gyro spin frequency is within the gyro spin frequency range, providing an indication that a gyro spin frequency test completed successfully; and if the determined gyro spin frequency is not within the gyro spin frequency range, providing an indication that the gyro spin frequency test has failed.

18. The method of claim 17 wherein concurrently executing the plurality of first stage tests on the test missile comprises determining a gyro spin direction of the gyro of the test missile.

19. The method of claim 15 wherein concurrently executing the plurality of first stage tests on the test missile comprises: determining whether a digital word in signal occurred based on a first received signal from the test missile after a minimum threshold amount of time; determining whether a digital word out signal occurred based on a second received signal from the test missile after the minimum threshold amount of time; wherein: if the digital word in signal occurred and the digital word out signal occurred, providing an indication that the digital word sensing test completed successfully; and otherwise providing an indication that the digital word sensing test has failed.

20. The method of claim 15 wherein concurrently executing the plurality of first stage tests on the test missile comprises: periodically determining an audio out signal level based on a received audio out signal from the test missile over a period of time; and determining a number of times that the measured audio out signal level exceeds an audio out signal level threshold, wherein: if the number of times that the measured audio out signal level exceeds the audio out signal level threshold is greater than a maximum threshold, providing an indication that an audio out signal level test completed successfully; and otherwise providing an indication that the audio out signal level test has failed.

21. The method of claim 15 wherein concurrently executing the plurality of first stage tests on the test missile comprises: determining an operating current based on a received signal from the test missile after a minimum threshold amount of time; determining whether the operating current is within an operating current range; and determining a number of how many of the plurality of first stage tests are completed, wherein: if the operating current is not within the operating current range or a determined number of the plurality of fist stage tests are not completed, providing an indication that an operating current test has failed; and if the operating current is within the operating current range and the determined number of the plurality of first stage tests are completed, providing an indication that the operating current test completed successfully.

22. The method of claim 15 wherein concurrently executing the plurality of second stage tests on the test missile comprises: determining a gas flow rate based on a received signal from the test missile after a minimum threshold amount of time; and determining whether the gas flow rate is within a gas flow rate range, wherein: if the gas flow rate is within the gas flow rate range, providing an indication that a gas flow rate test completed successfully; and otherwise providing an indication that the gas flow rate test has failed.

23. The method of claim 15 wherein concurrently executing the plurality of second stage tests on the test missile comprises determining whether the test missile acquires tracking of the first type missile target before a maximum threshold amount of time based on a first received signal from the test missile, wherein: if the test missile acquires tracking of the first type missile target before the maximum threshold amount of time, providing an indication that a functional cool down test completed successfully; and otherwise providing an indication that the functional cool down test has failed.

24. The method of claim 23 wherein concurrently executing the plurality of second stage tests on the test missile comprises determining whether the test missile maintains acquisition of the first type missile target for a minimum threshold amount of time based on a second received signal from the test missile, wherein: if the test missile maintains acquisition of the first type missile target for the minimum threshold amount of time, providing an indication that a tracking sensitivity test completed successfully; and otherwise providing an indication that the tracking sensitivity test has failed.

25. The method of claim 15 wherein concurrently executing the plurality of third stage tests on the test missile comprises determining a positive quiescent current level of the test missile while the test missile is tracking the second missile type target based on a received signal from the test missile, wherein: if the positive quiescent current level is within a positive quiescent current range, providing an indication that a positive quiescent current test completed successfully; and otherwise providing an indication that the positive quiescent current test has failed.

26. The method of claim 15 wherein concurrently executing the plurality of third stage tests on the test missile comprises determining a negative quiescent current level of the test missile while the test missile is tracking the second missile type target based on a received signal from the test missile, wherein: if the negative quiescent current level is within a negative quiescent current range, providing an indication that the negative quiescent current test completed successfully; and otherwise providing an indication that the negative quiescent current test has failed.

27. The method of claim 15 wherein concurrently executing the plurality of third stage tests on the test missile comprises determining whether the test missile maintains acquisition of the second type missile target for a minimum threshold amount of time based on a received signal from the test missile, wherein: if the test missile maintains acquisition of the second type missile target for the minimum threshold amount of time, providing an indication that a clockwise tracking capability test completed successfully; and otherwise providing an indication that the clockwise tracking capability test has failed.

28. The method of claim 15 wherein concurrently executing the plurality of third stage tests on the test missile comprises: providing an indication to the test missile to cease tracking the second missile target type and return to an off-axis position; and determining, based on one or more received signals from the test missile, whether the test missile loses acquisition of the second missile target type and returns to an off-axis position, wherein: if the test missile loses acquisition of the second missile target type and returns to an off-axis position, providing an indication that the caging capability test completed successfully; and otherwise providing an indication that the caging capability test has failed.

29. A test system comprising: a device under test; an electronic device operably coupled to the device under test and comprising: first stage concurrent determination test logic configured to: determine that a plurality of first stage tests to be executed on the device under test require a first test environment; concurrently execute the plurality of first stage tests on the device under test by determining when data will be made available for each of the plurality of first stage tests and executing a portion of the plurality of first stage tests that may be completed before the data is made available for each of the plurality of first stage tests; and provide an indication of whether the plurality of first stage tests completed successfully; second stage concurrent determination test logic configured to: determine that a plurality of second stage tests to be executed on the device under test require a second test environment; concurrently execute the plurality of second stage tests on the device under test by determining when data will be made available for each of the plurality of second stage tests and executing a portion of the plurality of second stage tests that may be completed before the data is made available for each of the plurality of second stage tests; and provide an indication of whether the plurality of second stage tests completed successfully; and third stage concurrent determination test logic configured to: determine that a plurality of third stage tests to be executed on the device under test require a third test environment; concurrently execute the plurality of third stage tests on the device under test by determining when data will be made available for each of the plurality of third stage tests and executing a portion of the plurality of third stage tests that may be completed before the data is made available for each of the plurality of third stage tests; and provide an indication of whether the plurality of third stage tests completed successfully.

30. The test system of claim 29 wherein the device under test is a missile, wherein the first test environment does not require a missile target or high pressure gas for the testing of the test missile, wherein the second test environment does require a first type missile target and high pressure gas for the testing of the test missile, and the third test environment requires a second type missile target for the testing of the test missile.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The detailed description of the drawings particularly refers to the accompanying figures in which:

[0031] FIG. 1 is an example functional block diagram of an electronic device with concurrent test determination logic that includes first, second, and third stage concurrent test determination logic according to one example of the present disclosure;

[0032] FIG. 2 is another functional block diagram with a more detailed view of the example test device testing logic 122, and its operability with test control logic 110 and first stage concurrent test determination logic, of FIG. 1 in accordance with one example of the present disclosure;

[0033] FIG. 3 is another functional block diagram with a more detailed view of the example test device testing logic 122, and its operability with test control logic 110 and second stage concurrent test determination logic, of FIG. 1 in accordance with one example of the present disclosure;

[0034] FIG. 4 is another functional block diagram with a more detailed view of the example test device testing logic 122, and its operability with test control logic 110 and third stage concurrent test determination logic, of FIG. 1 in accordance with one example of the present disclosure;

[0035] FIG. 5 is an example diagram indicating various test that may be performed concurrently by, for example, the electronic device of FIG. 1 in accordance with one example of the present disclosure;

[0036] FIG. 6 is a flowchart of an example method for concurrently executing a plurality of first, second, and third stage tests as may be performed by, for example, the electronic device of FIG. 1 in accordance with one example of the present disclosure; and

[0037] FIG. 7 is an example functional block diagram of a device testing system that includes an electronic device, a display device, a user input device, a test device, and first, second, and third stage concurrent test determination logic code residing in memory in accordance with one example of the present disclosure.

DETAILED DESCRIPTION OF THE DRAWINGS

[0038] The embodiments of the invention described herein are not intended to be exhaustive or to limit the invention to precise forms disclosed. Rather, the embodiments selected for description have been chosen to enable one skilled in the art to practice the invention.

[0039] FIG. 1 shows an example block diagram of an example electronic device with concurrent test determination logic (“electronic device”) 102 that includes first stage concurrent test determination logic 104, second stage concurrent test determination logic 106, and third stage concurrent test determination logic 108. Although three stages of concurrent test determination logic are shown, it is to be appreciated that electronic device 102 may include less, or more, stages of concurrent test determination logic. Electronic device 102 also includes test control logic 110, test device interface 112, and test device testing logic 122. In some examples, electronic device 102 may be a personal computer, laptop, tablet, work station, or any other suitable electronic device. In some embodiments, some or all of the functionality of first stage concurrent test determination logic 104, second stage concurrent test determination logic 106, third stage concurrent test determination logic 108, test control logic 110, and test device testing logic 122 may be performed by one or more processors executing suitable instructions, such as processor 114 indicated in the figure. The processor may be any suitable processor, such as a central processing unit (CPU), digital signal processor (DIP), microprocessor, or any other suitable processor(s).

[0040] As indicated in the figure, electronic device 102 may be operably coupled to test device 116, where test device 116 is a device under test, such as a missile. Test device interface 112 of electronic device 102 may be configured to provide test signals 118 to test device 116. Test initiation signals 118 may include, for example, test preparation signals to prepare a test to be executed on test device 116. Test initiation signals 118 may also include signals to begin test execution on test device 116. Test device interface 112 may also be configured to receive test status signals 120. Test status signals 120 may include signals that provide information as to the current status of a test. Test status signals 120 may also indicate whether a particular test has completed, and whether the test was successful, or failed. Test initiation signals 118 and test status signals 120 may include, for example, analog signals, digital signals, control signals, or any other suitable signal.

[0041] As shown in the figure, test control logic 110 is operably coupled to test device interface 112. As such, test control logic 110 may be configured to provide (e.g., signal) information to test device interface 112 so as to cause test device interface 112 to provide one or more signals to test device 116 via test initiation signals 118. Similarly, test control logic 110 may be configured to receive (e.g., read) information from test device interface 112, such as information related to signals received by test device interface 112 from test device 116 via test status signals 120. Test control logic 110 is also operably coupled to test device testing logic 122. Test device testing logic 122, as described further below with respect to FIGS. 2-4, includes test logic to execute one or more tests on test device 116. Test control logic 110 is also operably coupled to first stage concurrent test determination logic 104, second stage concurrent test determination logic 106, and third stage concurrent test determination logic 108.

[0042] First stage concurrent test determination logic 104 is operable to determine that one or more first stage tests to be executed on test device 116, which may be executed by test device testing logic 122, do not require a missile target or high pressure gas for testing of the test device 116. For example, each test may have an associated setting, such as in memory (e.g., in a database, in a look up table), indicating whether that test requires a missile target or high pressure gas during its execution. First stage concurrent test determination logic 104 is operable to read the test settings and determine which test may be executed concurrently as first stage tests. First stage concurrent test determination logic 104 is also operable to concurrently execute (or cause to execute) the first stage tests on test device 116. For example, first stage concurrent test determination logic 104 may provide data, such as in a message, to test control logic 110, to cause test device interface 112 to provide test initiation signals 118 to test device 116 to prepare for execution, and execute, first stage tests to be executed on test device 116.

[0043] First stage concurrent test determination logic 104 is also operable to receive an indication of whether one or more first stage tests completed successfully. For example, first stage concurrent test determination logic 104 may receive data, such as in a message, from test control logic 110, indicating whether one or more first stage tests completed successfully. In one example, to determine whether a first stage test completed successfully, first stage concurrent test determination logic 104 provides data to test control logic 110 to cause test device interface 112 to receive test status signals 120 from test device 116. Test control logic 110 may then read data received via test status signals 120 and provide the data to first stage concurrent test determination logic 104 via, for example, a message. First stage concurrent test determination logic 104 is also operable to provide an indication of whether the first stage tests completed successfully, such as by providing for display the indication.

[0044] Second stage concurrent test determination logic 106 is operable to determine that one or more second stage tests to be executed on test missile 116, which may be executed by test device testing logic 122, require a first type (e.g., particular) missile target and high pressure gas for testing of the test device 116. For example, each test may have a setting, such as in memory, indicating whether that test requires a first type missile target and high pressure gas during its execution. Second stage concurrent test determination logic 106 is operable to read the test settings and determine which test may be executed concurrently as second stage tests. Second stage concurrent test determination logic 106 is also operable to concurrently execute (or cause to execute) the second stage tests on test device 116, similar to that described above with respect to first stage concurrent test determination logic 104.

[0045] Second stage concurrent test determination logic 106 is also operable to receive an indication of whether one or more second stage tests completed successfully, similar to that described above with respect to first stage concurrent test determination logic 104. Second stage concurrent test determination logic 106 is also operable to provide an indication of whether the second stage tests completed successfully, such as by providing for display the indication.

[0046] Third stage concurrent test determination logic 108 is operable to determine that one or more third stage tests to be executed on test missile 116, which may be executed by test device testing logic 122, require a second type missile target for testing of the test device 116. For example, each test may have a setting, such as in memory, indicating whether that test requires a second type missile target during its execution. Third stage concurrent test determination logic 108 is operable to read the test settings and determine which test may be executed concurrently as third stage tests. Third stage concurrent test determination logic 108 is also operable to concurrently execute (or cause to execute) the third stage tests on test device 116, similar to that described above with respect to first stage concurrent test determination logic 104 and second stage concurrent test determination logic 106.

[0047] Third stage concurrent test determination logic 108 is also operable to receive an indication of whether one or more second stage tests completed successfully, similar to that described above with respect to first stage concurrent test determination logic 104 and second stage concurrent test determination logic 106. Third stage concurrent test determination logic 108 is also operable to provide an indication of whether the third stage tests completed successfully, such as by providing for display the indication.

[0048] In one example, electronic device 102 is operable to enable first stage concurrent test determination logic 104 to execute first stage tests. Once the first stage tests are completed, electronic device 102 enables second stage concurrent test determination logic 106 to execute second stage tests. Once the second stage tests are completed, electronic device 102 enables third stage concurrent test determination logic 108 to execute third stage tests.

[0049] FIG. 2 shows a functional block diagram with a more detailed view of the test device testing logic 122, and its operability with test control logic 110 and first stage concurrent test determination logic 104, of FIG. 1. As indicated in the figure, test device testing logic 122 includes a plurality of test logic (202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, and 226) for executing (e.g., conducting) a plurality of tests, such as the various tests described above. For example, gyro spin test logic 202 is operable to execute a gyro spin test, while gyro spin frequency test logic 204 is operable to execute a gyro spin frequency test. Similarly, gyro spin direction test logic 206 is operable to execute a gyro spin direction test. Digital word sensing test logic 208 is operable to execute a digital word sensing test. Chirp test logic 210 is operable to execute a chirp test. Operating current test logic 212 is operable to execute an operating current test. Gas flow rate test logic 214 is operable to execute a gas flow rate test, while functional cool down test logic 216 is operable to execute a functional cool down test. Tracking sensitivity test logic 218 is operable to execute a tracking sensitivity test. Positive quiescent current test logic 220 is operable to execute a positive quiescent current test, while negative quiescent current test logic 222 is operable to execute a negative quiescent current test. Clockwise tracking capability test logic 224 is operable to execute a clockwise tracking capability test, and caging capability test logic 226 is operable to execute a caging capability test.

[0050] As described above with respect to FIG. 1, first stage concurrent test determination logic 104 is operable to determine that one or more first stage tests to be executed on test device 116, which may be executed by test device testing logic 122, do not require a missile target or high pressure gas for testing of the test device 116. For example, first stage concurrent test determination logic 104 may be operable to select which tests supported by test device testing logic 122 do not require a missile target or high pressure gas for testing of the test device 116. Test control logic 110 is operable to allow the selected tests to execute concurrently as first stage tests. For example, test control logic 110 may enable the selected tests, while disabling the others, to execute as first stage tests. In one example, test control logic 110 includes register settings whereby first stage concurrent test determination logic 104 is operable to enable or disable one or more of the a plurality of test logic (202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, and 226) supported by test device testing logic 122.

[0051] FIG. 3 shows a functional block diagram with a more detailed view of the test device testing logic 122, and its operability with test control logic 110 and second stage concurrent test determination logic 106, of FIG. 1. As described above with respect to FIG. 1, second stage concurrent test determination logic 106 is operable to determine that one or more second stage tests to be executed on test device 116, which may be executed by test device testing logic 122, require a first type missile target and high pressure gas for testing of the test device 116. Similar to that described above with respect to first stage concurrent test determination logic 104 in FIG. 2, second stage concurrent test determination logic 106 may be operable to select which tests supported by test device testing logic 122 require a first type missile target and high pressure gas for testing of the test device 116. Test control logic 110 is operable to allow the selected tests to execute concurrently as second stage tests.

[0052] FIG. 4 shows a functional block diagram with a more detailed view of the test device testing logic 122, and its operability with test control logic 110 and third stage concurrent test determination logic 108, of FIG. 1. As described above with respect to FIG. 1, third stage concurrent test determination logic 106 is operable to determine that one or more third stage tests to be executed on test device 116, which may be executed by test device testing logic 122, require a second type missile target for testing of the test device 116. Similar to that described above with respect to first stage concurrent test determination logic 104 in FIG. 2, third stage concurrent test determination logic 108 may be operable to select which tests supported by test device testing logic 122 require a second type missile target for testing of the test device 116. Test control logic 110 is operable to allow the selected tests to execute concurrently as third stage tests.

[0053] FIG. 5 is a diagram indicating example tests that may be performed concurrently on a test device by, for example, the electronic device 102 of FIG. 1. For example, first stage tests 502 may be executed concurrently, which may include a gyro spin test, a gyro spin frequency test, a digital word sensing test, a chirp test, an operating current test, and a gyro spin direction test. Second stage tests 504 may also be executed concurrently, which may include a gas flow rate test, a functional cool down test, and a tracking sensitivity test. Likewise, third stage tests 506 may be executed concurrently, which may include a positive quiescent current test, a negative quiescent current test, a clockwise tracking capability test, and a caging capability test. In one example, first stage tests 502 are executed and, once complete, second stage tests 504 are executed. Once the second stage tests 504 are complete, third stage tests 504 are executed. Once the third stage tests are complete, any other tests may then be executed.

[0054] FIG. 6 illustrates an exemplary method 600 that may be realized, for example, by electronic device 102. For example, all or parts of method 600 may be performed by a software algorithm, such as one executed by electronic device 102. In various embodiments of the present disclosure, the steps or processes involved in method 600, and any other methods described herein, should not be limited to the sequence described in the present disclosure. One of ordinary skill in the art could readily understand the plurality of different options for organizing or executing the steps of the methods described herein in order to achieve substantially the same results or outcomes disclosed herein. Accordingly, the present disclosure contemplates that one of ordinary skill in the art may implement or execute one or more steps of the methods described herein in a plurality of different ways. Thus, the present disclosure should not be limited to the particular order disclosed in the methods described herein.

[0055] Method 600 begins at step 602, where a determination is made that a plurality of first stage tests to be executed on a test missile do not require a missile target or high pressure gas for testing of the test missile. At step 604, the plurality of first stage tests are concurrently executed on the test missile. At step 606, a determination is made that a plurality of second stage tests to be executed on the test missile require a first type missile target and high pressure gas for testing of the test missile. At step 608, the plurality of second stage tests are concurrently executed on the test missile. Proceeding to step 610, a determination is made that a plurality of third stage tests to be executed on the test missile require a second type missile target for testing of the test missile. At step 612, the plurality of third stage tests are concurrently executed on the test missile. At step 614 an indication of whether the plurality of first stage tests, plurality of second stage tests, and plurality of third stage tests were completed successfully is provided.

[0056] FIG. 7 is a functional block diagram illustrating an example device testing system 700 employing an electronic devices with processor 114 and test device 116. Device testing system 700 also includes display device 702, user Input/Output device 706, and memory device 704. Each of these devices is operatively coupled to expansion bus XXX. Display device 702 may be any suitable display device, such as a monitor, a liquid crystal display (LCD), a touch screen, or any other suitable display. User Input/Output device 706 may be any suitable input/output device such as a keyboard, a stylus, a touch screen, or any other suitable input/output device.

[0057] In some examples, executable suitable instructions may be stored on a computer readable storage medium, where the executable instructions are executable by one or more processors to cause the one or more processors to perform the actions described herein. Referring back to FIG. 7, memory device 704 may store executable instructions, including first stage concurrent test determination logic code 708, second stage concurrent test determination logic code 710, and third stage concurrent test determination logic 712, each of which may be executed by processor 114. For example, first stage concurrent test determination logic code 708 may include, for example, executable instructions corresponding to (e.g., compiled from) the “TestPhaseI” code module included in the code listing attached as an appendix. The appendix is incorporated by reference herein. Similarly, second stage concurrent test determination logic code 710 may include, for example, executable instructions corresponding to the “TestPhaseII” code module included in the code listing, and third stage concurrent test determination logic 712 may include executable instructions corresponding to the “TestPhaseII” code module included in the code listing.

[0058] As indicated in the figure, electronic device 102 is operatively coupled to memory device 704 via expansion bus 714 such that processor 114 may obtain first stage concurrent test determination logic code 708 from memory device 704 for execution. Similarly, processor 114 may obtain second stage concurrent test determination logic code 710 and third stage concurrent test determination logic code 712 from memory device 704 for execution. Memory device 704 may be any suitable memory, such as random access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, EPSOM, EPSOM, etc.), a disk storage device, or any other suitable memory that may store executable instructions.

[0059] Some or all of the functionality described above may be implemented in hardware or a combination of hardware and hardware executing suitable instructions. Suitable hardware may include one or more processors, BASICS, state machines, FPGAs, or other suitable hardware. Some or all of the functionality described above may also be implemented in any other suitable manner such as, but not limited to, a software implementation including, for example, a driver implementation, a firmware implementation, a hardware implementation, or any suitable combination of the example implementations described above. In some examples, the executable suitable instructions may be stored on a computer readable storage medium, where the executable instructions are executable by one or more processors to cause the one or more processors to perform the actions described herein. Computer readable storage medium may include, for example, flash memory, any non-transitory computer readable medium such as but not limited to RAM or ROM, a cloud storage mechanism, or any other suitable storage mechanism.

[0060] In the foregoing specification, specific embodiments of the present disclosure have been described. However, one of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative, rather than a restrictive, sense, and all such modifications are intended to be included within the scope of disclosure. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as critical, required, or essential features or elements of any or all the claims. The disclosure is defined solely by the appended claims including any amendments made during the pendently of this application and all equivalents of those claims as issued. Although the invention has been described in detail with reference to certain embodiments, variations and modifications exist within the spirit and scope of the disclosures as described and defined in the following claims.