INSULATED DC/DC CONVERTER, AND POWER ADAPTOR AND ELECTRONIC DEVICE USING THE SAME

Abstract

An insulated DC/DC converter includes: a transformer; a switching transistor; a rectifier circuit; a photocoupler; a feedback circuit configured to drive a light emitting element of the photocoupler such that an output voltage of the DC/DC converter approaches a target voltage; a primary side controller having a feedback terminal which is connected to a light receiving element of the photocoupler and receives a feedback signal from the photocoupler, a zero current detection terminal which receives a zero current detection signal corresponding to a voltage generated at one end of an auxiliary winding of the transformer, and a pulse modulator of a quasi-resonant mode configured to generate a pulse signal depending on the feedback signal and the zero current detection signal; and a starting control circuit which, in start-up of the DC/DC converter, electrically affects the zero current detection terminal such that an OFF time of the switching transistor lengthens.

Claims

1. An insulated DC/DC converter, comprising: a transformer having a primary winding, a secondary winding, and an auxiliary winding; a switching transistor installed between the primary winding of the transformer and a ground line; a rectifier circuit connected to the secondary winding of the transformer; a photocoupler including a light emitting element and a light receiving element; a feedback circuit configured to drive the light emitting element of the photocoupler such that an output voltage of the DC/DC converter approaches a target voltage; a primary side controller having a feedback terminal which is connected to the light receiving element of the photocoupler and receives a feedback signal from the photocoupler, a zero current detection terminal which receives a zero current detection signal corresponding to a voltage generated at one end of the auxiliary winding, and a pulse modulator of a quasi-resonant mode configured to generate a pulse signal depending on the feedback signal and the zero current detection signal; and a starting control circuit which, in start-up of the DC/DC converter, electrically affects the zero current detection terminal such that an OFF time of the switching transistor lengthens.

2. The DC/DC converter of claim 1, wherein the pulse modulator is configured to (i) shift the pulse signal to an OFF level depending on the feedback signal, and (ii) forcibly shift the pulse signal to an ON level when a state in which the zero current detection signal does not reach a predetermined first threshold voltage continues for a first predetermined time, and wherein the starting control circuit is configured to, in the start-up of the DC/DC converter, superimpose an auxiliary signal on the zero current detection terminal such that a voltage of the zero current detection terminal exceeds the first threshold voltage each time the switching transistor is turned off.

3. The DC/DC converter of claim 2, wherein the primary side controller further comprises: a comparator configured to assert a bottom detection signal when the zero current detection signal exceeds the first threshold voltage and then becomes lower than a second threshold voltage that is lower than the first threshold voltage; and a blanking circuit configured to mask the bottom detection signal for a predetermined mask time after the switching transistor is turned off, and wherein the starting control circuit is configured to superimpose the auxiliary signal on the zero current detection terminal such that a voltage of the zero current detection terminal becomes higher than the first threshold voltage after a lapse of the mask time from turning-off of the switching transistor.

4. The DC/DC converter of claim 2, wherein the starting control circuit is configured to generate the auxiliary signal using a voltage generated at one end of the auxiliary winding.

5. The DC/DC converter of claim 1, wherein the starting control circuit is configured to superimpose a high frequency component of a voltage generated at one end of the auxiliary winding on the zero current detection terminal.

6. The DC/DC converter of claim 1, wherein the starting control circuit comprises a first capacitor installed between one end of the auxiliary winding and the zero current detection terminal.

7. The DC/DC converter of claim 6, wherein the starting control circuit comprises a first resistor installed in series with the first capacitor between the one end of the auxiliary winding and the zero current detection terminal.

8. The DC/DC converter of claim 1, wherein the starting control circuit comprises a high pass filter.

9. The DC/DC converter of claim 1, wherein the pulse modulator is configured to (ii) shift the pulse signal to an ON level when the zero current detection signal reaches a predetermined first threshold voltage and then a state in which the zero current detection signal becomes lower than a predetermined second threshold voltage occurs a predetermined number of times, and wherein the starting control circuit is configured to control an electrical state of the zero current detection terminal such that, in the start-up of the DC/DC converter, a base line of a voltage of the zero current detection terminal exceeds the second threshold voltage.

10. The DC/DC converter of claim 9, wherein the starting control circuit is configured to, in the start-up of the DC/DC converter, shift the voltage of the zero current detection terminal to a high potential side.

11. The DC/DC converter of claim 9, further comprising: a power supply circuit including a diode whose anode is connected to the one end of the auxiliary winding and a second capacitor connected to a cathode of the diode, and configured to generate a power supply voltage of the primary side controller, wherein the starting control circuit is configured to control the base line of the voltage of the zero current detection terminal using the power supply voltage.

12. The DC/DC converter of claim 11, wherein the starting control circuit further comprises a second resistor installed between one end of the second capacitor and the zero current detection terminal.

13. The DC/DC converter of claim 1, further comprising a sense resistor installed in series with the switching transistor, wherein the primary side controller further comprises a current detection terminal which receives a current detection signal corresponding to a voltage drop of the sense resistor, and wherein the pulse modulator is a peak current mode modulator configured to (i) shift the pulse signal to an OFF level when the current detection signal reaches the feedback signal.

14. The DC/DC converter of claim 1, wherein the rectifier circuit comprises: a synchronous rectifying transistor; and a synchronous rectification controller configured to drive the synchronous rectifying transistor.

15. An insulated DC/DC converter, comprising: a transformer having a primary winding, a secondary winding, and an auxiliary winding; a switching transistor installed between the primary winding of the transformer and a ground line; a sense resistor installed in series with the switching transistor; a rectifier circuit connected to the secondary winding of the transformer; a photocoupler including a light emitting element and a light receiving element; a feedback circuit configured to drive the light emitting element of the photocoupler such that an output voltage of the DC/DC converter approaches a target voltage; a primary side controller having a feedback terminal which is connected to the light receiving element of the photocoupler and receives a feedback signal from the photocoupler, a current detection terminal which receives a current detection signal corresponding to a voltage drop of the sense resistor, a zero current detection terminal which receives a zero current detection signal corresponding to a voltage generated at one end of the auxiliary winding, and a peak current mode pulse modulator of a quasi-resonant mode configured to generate a pulse signal depending on the feedback signal, the current detection signal, and the zero current detection signal; a first voltage dividing resistor installed between the one end of the auxiliary winding and the current detection terminal; a second voltage dividing resistor installed between the current detection terminal and the ground line; and a first resistor and a first capacitor installed in series and on a path parallel with the first voltage dividing resistor, between the one end of the auxiliary winding and the current detection terminal.

16. The DC/DC converter of claim 15, further comprising: a power supply circuit including a diode whose anode is connected to the one end of the auxiliary winding and a second capacitor connected to a cathode of the diode, and configured to generate a power supply voltage of the primary side controller; and a second resistor installed between one end of the second capacitor and the zero current detection terminal.

17. An electronic device, comprising: a load; a diode rectifier circuit configured to full-wave rectify a commercial AC voltage; a smoothing capacitor configured to smooth an output voltage of the diode rectifier circuit to generate an DC input voltage; and the DC/DC converter of claim 1, configured to step down the DC input voltage to supply the stepped down voltage to the load.

18. A power adaptor, comprising: a diode rectifier circuit configured to full-wave rectify a commercial AC voltage; a smoothing capacitor configured to smooth an output voltage of the diode rectifier circuit to generate a DC input voltage; and the DC/DC converter of claim 1, configured to step down the DC input voltage to supply the stepped down voltage to the load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG. 1 is a circuit diagram of an AC/DC converter having a synchronous rectification type flyback converter.

[0046] FIG. 2 is an operational waveform diagram when the DC/DC converter of FIG. 1 starts up.

[0047] FIG. 3 is a circuit block diagram of a DC/DC converter according to a first embodiment of the present disclosure.

[0048] FIG. 4 is an operational waveform diagram when the DC/DC converter of FIG. 3 starts up.

[0049] FIG. 5 is a circuit block diagram of a primary side controller according to an example of the present disclosure

[0050] FIG. 6 is a circuit diagram illustrating a first configuration example of a starting control circuit for controlling start-up of the primary side controller of FIG. 5.

[0051] FIG. 7 is a diagram illustrating an operation of the starting control circuit of FIG. 6.

[0052] FIG. 8A is an operational waveform diagram of a conventional DC/DC converter and FIG. 8B is an operational waveform diagram of the DC/DC converter of FIG. 6.

[0053] FIG. 9 is a circuit diagram illustrating a second configuration example of the starting control circuit for controlling start-up of the primary side controller of FIG. 5.

[0054] FIG. 10 is an operational waveform diagram of the DC/DC converter of FIG. 9.

[0055] FIG. 11 is a diagram illustrating an AC adapter having an AC/DC converter.

[0056] FIGS. 12A and 12B are diagrams illustrating an electronic device having an AC/DC converter.

DETAILED DESCRIPTION

[0057] Embodiments of the present disclosure will be now described in detail with reference to the drawings. Like or equivalent components, members, and processes illustrated in each drawing are given like reference numerals and a repeated description thereof will be properly omitted. Further, the embodiments are presented by way of example only, and are not intended to limit the present disclosure, and any feature or combination thereof described in the embodiments may not necessarily be essential to the present disclosure.

[0058] In the present disclosure, “a state where a member A is connected to a member B” includes a case where the member A and the member B are physically directly connected or even a case where the member A and the member B are indirectly connected through any other member that does not affect an electrical connection state between the members A and B or does not inhibit any function.

[0059] Similarly, “a state where a member C is installed between a member A and a member B” includes a case where the member A and the member C or the member B and the member C are indirectly connected through any other member that does not affect an electrical connection state between the members A and C or the members B and C or does not inhibit any function, in addition to a case where the member A and the member C or the member B and the member C are directly connected.

[0060] FIG. 3 is a circuit block diagram of a DC/DC converter 200 according to a first embodiment of the present disclosure. The DC/DC converter 200 further includes a starting control circuit 240, in addition to the flyback converter 200r of FIG. 1.

[0061] The primary side controller 300 will be described in detail. The FB terminal of the primary side controller 300 is connected to the light receiving element of the photocoupler 204 to receive the feedback signal V.sub.FB from the photocoupler 204. A zero current detection signal V.sub.ZT corresponding to a voltage V.sub.D generated at one end of the auxiliary winding W3 is input to the ZT terminal of the primary side controller 300. Specifically, the voltage V.sub.D at one end of the auxiliary winding W3 is divided by a first voltage dividing resistor R.sub.ZT1 and a second voltage dividing resistor R.sub.ZT2 and input to the ZT terminal. A capacitor C.sub.ZT is connected to the ZT terminal.

[0062] The primary side controller 300 includes a pulse modulator (not shown) for generating a pulse signal S.sub.PFM. The pulse modulator operates in a quasi-resonant manner where (i) the pulse signal S.sub.PFM shifts to an OFF level depending on the feedback signal V.sub.FB and (ii) the pulse signal S.sub.PFM shifts to an ON level under a condition of zero cross of a current of the secondary winding W2 detected depending on the zero current detection signal V.sub.ZT.

[0063] In the present disclosure, a specific configuration of the pulse generator operating in the quasi-resonant manner is not particularly limited. Under some conditions, when the zero current detection signal V.sub.ZT of the ZT terminal does not meet the zero current, the switching transistor M1 may stop its switching. To solve this problem, in many cases, the primary side controller 300 forcibly turns on the switching transistor M1 to shift the pulse signal S.sub.PFM to an ON level, although the zero current detection terminal V.sub.ZT does not cross zero, when a predetermined condition is met.

[0064] For example, the switching transistor M1 is forcibly turned on after a lapse of a predetermined first time τ.sub.1 from an immediate previous turn-off of the switching transistor M1. As explained above with reference to FIG. 2, when an OFF time of the switching transistor M1 is fixed to the first time τ.sub.1 in the low voltage state, a surge is caused by operations in the continuous current mode.

[0065] In order to suppress the surge in the low voltage state, the DC/DC converter 200 includes the starting control circuit 240.

[0066] When the DC/DC converter 200 starts up, the starting control circuit 240 electrically affects the ZT terminal such that the OFF time of the switching transistor M1 becomes longer than that occurring when the starting control circuit 240 is not installed (i.e., τ.sub.1).

[0067] The above is the configuration of the DC/DC converter 200. Next, an operation of the DC/DC converter 200 will be described. FIG. 4 is an operational waveform diagram when the DC/DC converter 200 of FIG. 3 starts up. An OFF time T.sub.OFF of the switching transistor M1 becomes longer than the first time τ.sub.1, by the starting control circuit 240. Thus, the DC/DC converter 200 can operate in a discontinuous current mode (or a critical mode). As a result, since the residual energy of the transformer T1 approaches zero at a timing when the switching transistor M1 is turned on, it is possible to suppress the surge generated in the secondary winding W2 due to the turning on of the switching transistor M1.

[0068] The above is the operation of the DC/DC converter 200. According to the DC/DC converter 200, it is possible to delay a timing at which the pulse signal S.sub.OFF shifts to an ON level. Thus, it is possible to reduce the amount of current flowing through the transformer T1, and to suppress surge noise generated in the secondary side rectifier circuit.

[0069] The present disclosure is intended to cover various devices and circuits that are recognized by the block diagram or the circuit diagram of FIG. 3 or derived from the above description, but is not limited to the specific configuration. Hereinafter, a more specific configuration example or an example will be described in order to help understand and clarify the essence of the present disclosure and a circuit operation thereof, rather than to narrow the scope of the present disclosure.

[0070] The control of the electrical state of the ZT terminal by the starting control circuit 240 may be determined based on an internal configuration or a modulation scheme of the primary side controller 300 and is not particularly limited. In the following specific example, a configuration of a typical primary side controller 300 and a configuration and an operation of the starting control circuit 240 corresponding thereto will be described.

Example

[0071] FIG. 5 is a circuit block diagram of the primary side controller 300 according to an example of the present disclosure. Further, in FIG. 5, only blocks related to the present disclosure are illustrated and other blocks are properly omitted.

[0072] The primary side controller 300 includes a pulse modulator 302 and a driver 304. The pulse modulator 302 generates a pulse signal S.sub.PFM in a peak current mode of a quasi-resonant mode. When the zero current detection signal V.sub.ZT reaches a predetermined first threshold voltage V.sub.TH1 (e.g., 0.2V) and then a state (bottom detection) in which the zero current detection signal V.sub.ZT becomes lower than a predetermined second threshold voltage V.sub.TH2 (e.g., 0.1V) occurs a predetermined number of times, the pulse modulator 302 shifts the pulse signal S.sub.PFM to an ON level. The predetermined number of times may be one or more times. Further, when the current detection signal V.sub.CS reaches the feedback signal V.sub.FB, the pulse modulator 302 shifts the pulse signal S.sub.PFM to an OFF level.

[0073] The primary side controller 300 includes a set signal generating part 310, a reset signal generating part 330, and a flipflop 350. The set signal generating part 310 generates a set signal S.sub.SET that instructs the switching transistor M1 to be turned on based on a state of the ZT terminal (zero current detection signal V.sub.ZT).

[0074] The reset signal generating part 330 generates a reset signal S.sub.RESET that instructs the switching transistor M1 to be turned off based on electrical states (V.sub.CS and V.sub.FB) of the CS terminal and the FB terminal.

[0075] The flipflop 350 may be, for example, an SR flipflop, and shifts the pulse signal S.sub.PFM as its output to an ON level (e.g., high level) in response to assertion of the set signal S.sub.SET, and shifts the pulse signal S.sub.PFM to an OFF level (low level) in response to assertion of the reset signal S.sub.RESET.

[0076] When the set signal generating part 310 detects that the current I.sub.S of the secondary winding W2 (i.e., the residual energy of the transformer T1) is zero depending on the zero current detection signal V.sub.ZT during general operations, the set signal generating part 310 asserts the set signal S.sub.SET.

[0077] The set signal generating part 310 includes a ZT comparator 312, a ZT blanking circuit 314, a one shot circuit 320, a timer circuit 322, and an OR gate 326.

[0078] The ZT comparator 312 is a hysteresis comparator, and compares the zero current detection signal V.sub.ZT with a threshold voltage to output a bottom detection signal S.sub.BOTTOM indicating a comparison result. The threshold voltage switches two values of the first threshold voltage V.sub.TH1 (e.g., 0.2V) and the second threshold voltage V.sub.TH2 (e.g., 0.1V) depending on a level of the bottom detection signal S.sub.BOTTOM.

[0079] When the current I.sub.S of the secondary winding W2 becomes zero (zero current), the zero current detection signal V.sub.ZT greatly oscillates. At this time, the zero current detection signal V.sub.ZT temporarily exceeds the first threshold voltage V.sub.TH1 and then becomes lower than the second threshold voltage V.sub.TH2, so that the bottom detection signal S.sub.BOTTOM changes in a pulse form (asserted).

[0080] Immediately after the switching transistor M1 is turned off, there is a possibility that noise is superimposed on the zero current detection signal V.sub.ZT to erroneously detect the zero cross. The ZT blanking circuit 314 is installed to remove the noise. The blanking timer 316 generates a mask signal S.sub.MSK which has a low level for a predetermined mask time from the turning off of the switching transistor M1 and then has a high level. The AND gate 318 outputs a logical product of the bottom detection signal S.sub.BOTTOM and the mask signal S.sub.MSK.

[0081] The one shot circuit 320 generates a set signal S.sub.SET1 in response to an edge of the bottom detection signal S.sub.BOTTOM which has passed through the ZT blanking circuit 314. The set signal S.sub.SET1 is input to the flipflop 350 via the OR gate 326.

[0082] Further, a counter for counting the bottom detection signal S.sub.BOTTOM may be installed when as a condition for turning on the switching transistor a bottom detection is made multiple times.

[0083] The pulse modulator 302 has a function of preventing the switching of the switching transistor M1 from being stopped in a situation where the zero cross of the current I.sub.S of the secondary winding W2 cannot be detected by the ZT comparator 312. Specifically, when a state in which the zero current detection signal V.sub.ZT does not reach the first threshold voltage V.sub.TH1 continues for a predetermined first time τ.sub.1 after the switching transistor M1 is turned off, the set signal generating part 310 asserts the set signal S.sub.SET to forcibly shift the pulse signal S.sub.PFM to an ON level.

[0084] For this function, the timer circuit 322 is installed. The timer circuit 322 includes two timers. A first timer measures a time during which the bottom detection signal S.sub.BOTTOM has not been generated after the switching transistor M1 is turned off. When the measured time reaches the first time τ.sub.1 (e.g., 15 μs) (timeout), the first timer asserts a set signal S.sub.SET2.

[0085] Further, if the zero current detection signal V.sub.ZT of the ZT terminal exceeds the first threshold voltage V.sub.TH1 and then remains higher than the second threshold voltage V.sub.TH2, the bottom detection signal S.sub.BOTTOM is not asserted, which stops switching of the switching transistor M1. In order to prevent this, the timer circuit 322 includes a second timer. When the bottom detection signal S.sub.BOTTOM shifts to a high level and remains at the high level for a second time τ.sub.2 (e.g., 5 μs), the second timer asserts a set signal S.sub.SET3. Thus, the pulse signal S.sub.PFM forcibly shifts to an ON level.

[0086] The reset signal generating part 330 will be described. The reset signal generating part 330 includes a voltage dividing circuit 332, a leading edge blanking circuit 334, and a comparator 336.

[0087] Immediately after the switching transistor M1 is turned on, noise is superimposed on the current detection signal V.sub.CS. The leading edge blanking circuit 334 is installed to remove the noise. The leading edge blanking circuit 334 masks the current detection signal V.sub.CS for a predetermined mask time from the turning on of the switching transistor M1.

[0088] The voltage dividing circuit 332 divides a voltage of the FB terminal to generate a feedback signal V.sub.FB′. The comparator 336 compares a current detection signal V.sub.CS′ which has passed through the leading edge blanking circuit 334 with the feedback signal V.sub.FB′. When the current detection signal V.sub.CS′ reaches the feedback signal V.sub.FB′, the comparator 336 asserts the reset signal S.sub.RESET.

[0089] The above is the configuration example of the primary side controller 300. Next, the starting control circuit 240 suitable for the primary side controller 300 of FIG. 5 will be described.

[0090] FIG. 6 is a circuit diagram illustrating a first configuration example 240a of the starting control circuit 240 of controlling starting of the primary side controller 300 of FIG. 5.

[0091] When the DC/DC converter 200 starts up, the starting control circuit 240a superimposes an auxiliary signal S.sub.AUX on the ZT terminal such that the voltage of the ZT terminal exceeds the first threshold voltage V.sub.TH1 each time the switching transistor M1 is turned off. The auxiliary signal S.sub.AUX may be a voltage signal or a current signal. This makes it possible to prevent the switching transistor M1 from being forcibly turned on after the lapse of the first time τ.sub.1 (15 μs) from the turning off of the switching transistor M1, and to prolong an OFF time.

[0092] More specifically, the starting control circuit 240a generates the auxiliary signal S.sub.AUX such that the zero current detection signal V.sub.ZT becomes higher than the first threshold voltage V.sub.TH1 after the lapse of the mask time T.sub.MSK from turning off of the switching transistor M1. This makes it possible to prevent a change in the bottom detection signal S.sub.BOTTOM caused by the auxiliary signal S.sub.AUX from being masked by the ZT blanking circuit 314. There is a requirement that auxiliary signal S.sub.AUX cannot interfere with the zero current detection and is thus preferably attenuated before the zero current (I.sub.S=0)

[0093] The starting control circuit 240a generates the auxiliary signal S.sub.AUX using a voltage VD generated at one end of the auxiliary winding W3. Specifically, the starting control circuit 240a may generate the auxiliary signal S.sub.AUX using a steep waveform generated in the voltage VD at one end of the auxiliary winding W3, i.e., a high frequency component of the voltage VD, due to the turning off of the switching transistor M1. For example, the starting control circuit 240a may include a high pass filter.

[0094] Here, since a spike-like waveform generated in the voltage V.sub.D is generated only for a very short time, if it is superimposed on the ZT terminal as it is, it may be often masked by the ZT blanking circuit 314. In this case, the starting control circuit 240a properly waveform-shapes the high frequency component of the voltage VD to generate the auxiliary signal S.sub.AUX.

[0095] The starting control circuit 240a includes a first capacitor C21 installed between one end of the auxiliary winding W3 and the ZT terminal. The high frequency component of the voltage V.sub.D may be extracted by the first capacitor C21. In addition, a first resistor R21 is installed in series with the first capacitor C21. The first resistor R21 provides a degree of freedom of adjusting a voltage variation of the ZT terminal provided by the auxiliary signal S.sub.AUX. The first resistor R21 and the first capacitor C21 may be recognized as a high pass filter.

[0096] FIG. 7 is a diagram illustrating an operation of the starting control circuit 240a of FIG. 6. A voltage obtained by multiplying the input voltage V.sub.IN by a winding ratio n.sub.A/n.sub.P is generated between both ends of the auxiliary winding W3 during an ON time T.sub.ON of the switching transistor M1, and thus, the voltage V.sub.D at one end of the auxiliary winding W3 becomes −V.sub.IN×n.sub.A/n.sub.P. n.sub.A is the number of turns of the auxiliary winding W3 and n.sub.P is the number of turns of the primary winding W1. While the switching transistor M1 is turned off and the current I.sub.S flows through the secondary winding W2, the voltage VD becomes a positive voltage that is proportional to the output voltage V.sub.OUT. Thus, the voltage VD steeply changes from negative to positive in response to the turning off of the switching transistor M1. By extracting this steep change by the high pass filter or the like, it is possible to generate the auxiliary signal S.sub.AUX.

[0097] Next, an operation of the DC/DC converter 200 of FIG. 6 will be described.

[0098] In order to further clarify effects obtained by the DC/DC converter 200 of FIG. 6, first, an operation of the conventional DC/DC converter will be described. FIG. 8A is an operational waveform diagram of the conventional DC/DC converter. While a current flows through the secondary winding W2, the zero current detection signal V.sub.ZT appears as a voltage obtained by multiplying the output voltage V.sub.OUT by the winding ratio n.sub.P/n.sub.S. n.sub.P is the number of turns of the primary winding W1 and n.sub.S is the number of turns of the secondary winding W2. Immediately after starting-up, since the output voltage your is low, the zero current detection signal V.sub.ZT becomes lower than the first threshold voltage V.sub.TH1. In the conventional DC/DC converter, a valid bottom detection signal S.sub.BOTTOM immediately after starting-up is not generated, and after a predetermined first time τ.sub.1 has lapsed since the switching transistor M1 is turned off, the set signal S.sub.SET2 is asserted and the pulse signal S.sub.PFM forcibly shifts to an ON level.

[0099] In this case, since the switching transistor M1 is turned on before the current I.sub.S flowing through the secondary winding W2 drops to zero, the continuous current mode is entered. When the switching transistor M1 is turned on in a state where energy remains in the transformer, a large surge noise occurs between a drain and a source of the synchronous rectifying transistor M2.

[0100] It is not desirable that a negative overvoltage is input to the ZT terminal due to the turning on of the switching transistor M1. Thus, although not shown in FIG. 5, a switch is installed between the ZT terminal and a ground, and when the ZT terminal has a negative voltage, the switch may be turned on to fix the ZT terminal to 0V.

[0101] Next, an operation of the DC/DC converter 200 of FIG. 6 will be described with reference to FIG. 8B. FIG. 8B is an operational waveform diagram of the DC/DC converter 200 of FIG. 6. The auxiliary signal S.sub.AUX is superimposed on the ZT terminal by the starting control circuit 240a. Thus, the zero current detection signal V.sub.ZT becomes higher than a voltage level V.sub.OUT×n.sub.P/n.sub.S that is proportional to the output voltage V.sub.OUT′ to exceed the first threshold voltage V.sub.TH1.

[0102] When the zero current detection signal V.sub.ZT exceeds the first threshold voltage V.sub.TH1, the set signal S.sub.SET2 is not generated. Therefore, the forcible OFF of the switching transistor M1 by the timer circuit 322 (first timer) is invalidated. Thus, it is possible to make an OFF time longer than the first time τ.sub.1. As the OFF time lengthens, a decrement of the current I.sub.S of the secondary winding W2 increases and the residual energy of the transformer at a timing at which the switching transistor M1 is turned on can be reduced to suppress the secondary side surge noise.

[0103] In particular, after a second cycle of FIG. 8B, when the current I.sub.S of the secondary winding W2 becomes zero after the component of the auxiliary signal V.sub.AUX is attenuated, the voltage V.sub.ZT becomes lower than the second threshold voltage V.sub.TH2. As a result, a valid bottom detection signal S.sub.BOTTOM is generated to turn on the switching transistor M1. That is, an operation of a critical mode can be obtained.

[0104] Further, in a first cycle of FIG. 8B, since the output voltage V.sub.OUT is low, V.sub.OUT×n.sub.P×n.sub.S is lower than the second threshold voltage V.sub.TH2. Thus, when the auxiliary signal S.sub.AUX is attenuated, V.sub.ZT is less than V.sub.TH2 (V.sub.ZT<V.sub.TH2), and the bottom detection signal S.sub.BOTTOM is asserted before the zero cross to turn on the switching transistor M1.

[0105] After the second cycle, since the output voltage V.sub.OUT increases, V.sub.OUT×n.sub.P×n.sub.S becomes higher than the second threshold voltage V.sub.TH2. The current I.sub.S of the secondary winding becomes zero and the zero current detection signal V.sub.ZT swings in a negative direction so that the bottom detection signal S.sub.BOTTOM is generated to turn on the switching transistor M1. Thus, after the second cycle, the residual energy of the transformer becomes zero when the switching transistor M1 is turned on, and the secondary side surge noise is reduced.

[0106] As in the first cycle, after the zero current detection signal V.sub.ZT exceeds the first threshold voltage V.sub.TH1, when the zero current detection signal V.sub.ZT becomes lower than the second threshold voltage V.sub.TH2 due to attenuation of the auxiliary signal S.sub.AUX, bottom detection is performed by the ZT comparator 312 to cause the pulse signal S.sub.PFM to shift to a high level. If an OFF time at this time is too short, the secondary side surge noise NS generated in a next cycle may not be sufficiently suppressed. Here, a method for solving this problem will be described with a second configuration example.

[0107] FIG. 9 is a circuit diagram illustrating a second configuration example 240b of the starting control circuit 240 controlling the start of the primary side controller 300 of FIG. 5. The starting control circuit 240b controls an electrical state of the ZT terminal such that a base line (bottom line) of the zero current detection signal V.sub.ZT exceeds the second threshold voltage V.sub.TH2 when the DC/DC converter 200 starts up.

[0108] The starting control circuit 240b of FIG. 9 controls a base line of the zero current detection signal V.sub.ZT using the power supply voltage V.sub.CC. The starting control circuit 240b further includes a second resistor R22 installed between the smoothing capacitor C2 and the ZT terminal, in addition to the starting control circuit 240a of FIG. 6. Thus, an initial offset V.sub.OFS of V.sub.CC×R.sub.ZT2/(R.sub.ZT2+R22) can be given to the zero current detection signal V.sub.ZT.

[0109] FIG. 10 is an operational waveform diagram of the DC/DC converter 200 of FIG. 9. The initial offset V.sub.OFS (e.g., 60 mV) is given to the zero current detection signal V.sub.ZT. Therefore, an attenuation time until the zero current detection signal V.sub.ZT is lower than the second threshold voltage V.sub.TH2 can be prolonged, compared with the case illustrated in FIG. 8B. Thus, it is possible to further lengthen an OFF time of the switching transistor M1 and to further reduce the secondary side surge noise.

[0110] Further, in FIG. 10, before the zero current detection signal V.sub.ZT superimposed on the auxiliary signal S.sub.AUX is attenuated to the second voltage VTH.sub.2 in the first cycle, the current of the secondary winding W2 becomes zero, so that the zero current detection signal V.sub.ZT swings in a negative direction.

[0111] The present disclosure has been described above based on the embodiments. It is to be understood by those skilled in the art that the embodiments are merely illustrative and may be differently modified by any combination of the components or processes, and the modifications are also within the scope of the present disclosure. Hereinafter, these modifications will be described.

(First Modification)

[0112] Referring to FIG. 5, when the timer circuit 322 does not have a 15 μs time out function, the resistor R21 and the capacitor C21 of the starting control circuit 240b of FIG. 9 may be omitted and the starting control circuit 240b may be configured with only the resistor R22.

(Second Modification)

[0113] A specific configuration of the starting control circuit 240 is not particularly limited. For example, the starting control circuit 240a of FIG. 6 may be configured as a current source of injecting (sourcing) a current pulse to the ZT terminal in response to turning off of the switching transistor M1.

[0114] In FIG. 9, the voltage of the ZT terminal is shifted using the power supply voltage V.sub.CC generated by the power supply circuit, but the present disclosure is not limited thereto. For example, instead of the power supply voltage V.sub.CC, the input voltage V.sub.IN of the DC/DC converter 200, or a DC voltage generated by any other power supply circuit may be used.

(Third Modification)

[0115] The internal configuration of the primary side controller 300 is not particularly limited. For the primary side controller 300, numerous circuits are provided by various venders and a bottom detection scheme of the ZT terminal is diverse. The starting control circuit 240 may be designed, in consideration of the internal configuration or the control scheme of the primary side controller 300, such that a time after turning off of the switching transistor M1 at its starting-up becomes longer.

(Fourth Modification)

[0116] In the embodiments, the synchronous rectification type DC/DC converter has been described, but the present disclosure is also applicable to a diode rectifier type DC/DC converter.

(Applications)

[0117] Finally, applications of the DC/DC converter 200 will be described. The DC/DC converter 200 can be used for the AC/DC converter 100 suitably used for a power supply block of an AC adapter or an electronic device.

[0118] FIG. 11 is a diagram illustrating an AC adapter 800 having the AC/DC converter 100. The AC adapter 800 includes a plug 802, a housing 804, and a connector 806. The plug 802 receives a commercial AC voltage V.sub.AC from an outlet (not shown). The AC/DC converter 100 is mounted in the housing 804. A DC output voltage V.sub.OUT generated by the AC/DC converter 100 is supplied from the connector 806 to the electronic device 810. Examples of the electronic device 810 include a laptop computer, a digital camera, a digital video camera, a mobile phone, a portable audio player, and the like.

[0119] FIGS. 12A and 12B are diagrams illustrating an electronic device 900 having the AC/DC converter 100. The electronic device 900 in FIGS. 12A and 12B is a display device, but the type of the electronic device 900 is not particularly limited thereto, and it may be a device, which incorporates a power supply device, such as an audio device, a refrigerator, a washing machine, a vacuum cleaner, and the like.

[0120] The plug 902 receives a commercial AC voltage V.sub.AC from an outlet (not shown). The AC/DC converter 100 is mounted in a housing 904. A DC output voltage V.sub.OUT generated by the AC/DC converter 100 is supplied to a load, which is mounted in the same housing 904, such as a microcomputer, a digital signal processor (DSP), a power supply circuit, a lighting device, an analog circuit, a digital circuit, or the like.

[0121] According to the present disclosure in some embodiments, it is possible to suppress surge noise generated in a secondary side rectifier circuit at the time of starting.

[0122] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.