TUNABLE HOMOJUNCTION FIELD EFFECT DEVICE-BASED UNIT CIRCUIT AND MULTI-FUNCTIONAL LOGIC CIRCUIT

Abstract

A tunable homojunction field effect device-based unit circuit and a multifunctional logic circuit, and the corresponding design scheme includes four steps: a structural construction of the tunable homojunction device, an implementation of multi-functional electrical operations of the tunable homojunction device, a design of a basic logic unit circuit, and an implementation of complex logic functions by a cascaded unit logic circuit; the first designs a tunable homojunction device based on a material with bipolar field effect characteristics; and then introduces the polarity of source-drain voltage into the device as an additional control signal; further, by cascading three reconfigurable logic units, the multi-functional logic circuit that can perform logic functions of full adder and subtractor is designed; the logic unit circuit designed in the present invention has the ability to perform reconfigurable logic functions.

Claims

1. A tunable homojunction field effect device-based unit circuit, wherein the unit circuit E comprises: a first input terminal V.sub.in1 for receiving a first input voltage signal; a second input terminal V.sub.in2 for receiving a second input voltage signal; a third input terminal V.sub.in3 for receiving a third input voltage signal; a first tunable homojunction field effect transistor M1, wherein a source S1 of the first tunable homojunction field effect transistor M1 is coupled to the first input terminal, a gate electrode 1a close to the source S1 is connected to the second input terminal, and a gate electrode 1b close to a drain of the first tunable homojunction field effect transistor M1 is coupled to the third input terminal; a second tunable homojunction field effect transistor M2, wherein a source S2 of the second tunable homojunction field effect transistor M2 is coupled to the third input terminal, a gate electrode 2a close to the source S2 is connected to the second input terminal, and a gate electrode 2b close to a drain of the second tunable homojunction field effect transistor M2 is coupled to the first input terminal; wherein the drain of the first tunable homojunction field effect transistor is connected to the drain of the second tunable homojunction field effect transistor, and an output of a connection point therebetween is used as an output terminal V.sub.out; wherein the first tunable homojunction field effect transistor M1 and the second tunable homojunction field effect transistor M2 have the same structure, comprising a substrate insulating material, a channel material layer, an insulating layer, and a metal electrode layer; the metal electrode layer comprises a drain electrode layer, a source electrode layer, a gate electrode layer A, and a gate electrode layer B, the gate electrode layer A and the gate electrode layer B are fabricated side by side on the substrate insulating material, and a gap is left between the gate electrode layer A and the gate electrode layers B to ensure electrical insulation therebetween, the insulating layer completely covers the gate electrode layer A and the gate electrode layer B, the drain electrode layer is placed on a left edge of the channel material layer above the gate electrode layer A, and the source electrode layer is placed on a right edge of the channel material layer above the gate electrode layer B, that is, the gate electrode layer A corresponds to the gate electrode 1b of M1, and the gate electrode layer A corresponds to the gate electrode 2b of M2, the gate electrode layer B corresponds to the gate electrode 1a of M1, and the gate electrode layer B corresponds to the gate electrode 2a of M2.

2. The tunable homojunction field effect device-based unit circuit according to claim 1, wherein if the first input terminal V.sub.in1 and the third input terminal V.sub.in3 input a signal A and a signal B, respectively, when the second input terminal V.sub.in2 inputs a high level, the output terminal V.sub.out outputs an AND gate, and the logical operation result is AB, when the second input terminal V.sub.in2 inputs a low level, the output terminal V.sub.out outputs an OR gate, and the logical operation result is A+B, when the second input terminal V.sub.in2 inputs a signal C, the output terminal V.sub.out outputs a borrow operation in subtractions, and the logical operation result is AB+AC+BC, if the first input terminal V.sub.in1 and the second input terminal V.sub.in2 input the signal A and the signal B, respectively, when the third input terminal V.sub.in3 is at a high level, the output terminal V.sub.out outputs the logic operation result A+B, and when the third input terminal V.sub.in3 is at a low level, the output terminal V.sub.out outputs the logic operation result AB; if the third input terminal V.sub.in3 inputs the signal A, and the first input terminal V.sub.in1 and the second input terminal V.sub.in2 are at the same level, the output terminal is a signal following, and the logical operation result is A; If the third input terminal V.sub.in3 inputs the signal A, the first input terminal V.sub.in1 is at a high level, and the second input terminal V.sub.in2 is at a low level, the output signal is always at a high level, if the first input terminal V.sub.in1 is at a low level, and the second input terminal V.sub.in2 is at a high level, the output signal is always at a low level; if the first input terminal V.sub.in1 and the third input terminal V.sub.in3 are at opposite levels, and the input signal V.sub.in2 is the input signal A, the output terminal VT.sub.out implements a NOT gate, and the logical operation result is Ā.

3. The tunable homojunction field effect device-based unit circuit according to claim 1, wherein a multi-functional logic circuit comprising two unit circuits, wherein the two unit circuits are denoted as a logic circuit E1 and a logic circuit E2, respectively, the output terminal corresponding to the logic circuit E1 is connected to the second input terminal of the logic circuit E2 to form a logic circuit with five input terminals and one output terminal, which are respectively denoted as a first input terminal V.sub.in1, a second input terminal V.sub.in2, a third input terminal V.sub.in3, a fourth input terminal V.sub.in1, and a fifth input terminal V.sub.in5 .

4. The tunable homojunction field effect device-based unit circuit according to claim 3, wherein if the first input terminal V.sub.in1and the third input terminal V.sub.in3 input the signals A and B, respectively, and the fourth input terminal V.sub.in2 and the fifth input terminal V.sub.in5 input opposite levels, when the second input terminal V.sub.in2 inputs a high level, an AND-OR gate is implemented with the logic operation result of AB, when the second input terminal V.sub.in2 inputs a low level, an OR-NOT gate is implemented with the logic operation result of A+B; if the fourth input terminal V.sub.in4 and the fifth input terminal V.sub.in5 input the signals A and B, respectively, the second input terminal V.sub.in2 inputs the signal C, and the first input terminal V.sub.in1 and the third input terminal V.sub.in3 input opposite levels, a majority gate is implemented with the logic operation result of AB+BC+AC.

5. A multi-functional logic circuit, comprising two unit circuits according to claim 1, wherein the two unit circuits are denoted as a logic circuit E1 and a logic circuit E2, respectively, the output terminal corresponding to the logic circuit E1 is connected to the third input terminal of the logic circuit E2 to form a logic circuit with five input terminals and one output terminal V.sub.om, which are respectively denoted as a first input terminal V.sub.in1, a second input terminal V.sub.in2, a third input terminal V.sub.in3, a fourth input terminal V.sub.in4, and a fifth input terminal V.sub.in5.

6. The multi-functional logic circuit according to claim 5, wherein if the first input terminal V.sub.in1, the third input terminal V.sub.in3, and the fourth input terminal V.sub.in4 input the signals A, B, and C, respectively, when both the second input terminal V.sub.in2 and the fifth input terminal V.sub.in5 input a high level, an AND gate is implemented, and the output terminal V.sub.out outputs ABC; when both the second input terminal V.sub.in2 and the fifth input terminal V.sub.in5 input a low level, an OR gate is implemented, and the output terminal V.sub.out outputs A+B+C; when the second input terminal V.sub.in2 is at a high level and the fifth input terminal V.sub.in5 inputs a low level, an AND-OR gate is implemented, and the output terminal V.sub.out outputs AB+C; when the second input terminal V.sub.in2 is at a low level and the fifth input terminal V.sub.in5 inputs a high level, an OR-AND gate is implemented, and the output terminal V.sub.out outputs (A+B)C.

7. An adder-subtractor logic circuit, wherein the adder-subtractor logic circuit is formed by cascading three unit circuits according to claim 1, denoted as a first unit, a second unit, and a third unit, respectively, the specific connection method is as follows: the first input terminal of the first unit is connected to the first input terminal of the second unit, which serves as the first input terminal of the adder-subtractor logic circuit and inputs a signal B; the second input terminal of the first unit is connected to the third input terminal of the third unit, which serves as the second input terminal of the adder-subtractor logic circuit and inputs a signal A; the third input terminal of the first unit is connected to the third input terminal of the second unit, which serves as the third input terminal of the adder-subtractor logic circuit and inputs a signal C; the output terminal of the first unit is connected to the second input terminal of the second unit and the first input terminal of the third unit, which serves as the first output terminal of the adder-subtractor logic circuit and outputs a signal B.sub.out; the output terminal of the second unit is connected to the second input terminal of the third unit, which serves as the second output terminal of the adder-subtractor logic circuit and outputs a signal C.sub.out; the output terminal of the third unit is used as the adder signal output terminal of the adder-subtractor logic circuit to output a signal Sum or as the subtractor signal output terminal of the adder-subtractor logic circuit to output a signal Diff.

8. The adder-subtractor logic circuit according to claim 7, wherein the input signal and the output signal satisfy the Boolean logic operation: B.sub.out=BC+BĀ+CĀ; the input signal and the output signal satisfy the Boolean logic operation: C.sub.out=BC+BB.sub.out+CB.sub.out=BC+BA+CA; the input signal and the output signal satisfy the Boolean logic operation: Sum/Diff=AB.sub.out+AC.sub.out+B.sub.outC.sub.out=A⊕B⊕C, wherein the output signals B.sub.out and Diff respectively represent results of the borrow operation and the difference operation of subtractor, and the output signals C.sub.out and Sum respectively represent results of the carry operation and the summation operation of adder.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG. 1 is a front view of the tunable homojunction field effect device of Embodiment 1;

[0043] FIG. 2 is a top view of the tunable homojunction field effect device of Embodiment 1;

[0044] FIG. 3 is a right view of the tunable homojunction field effect device of Embodiment 1;

[0045] FIG. 4 is a device function table of the tunable homojunction field effect device of Embodiment 1 under different electrical operations;

[0046] FIG. 5a is a schematic diagram of the unit circuit of Embodiment 1: a circuit structure diagram;

[0047] FIG. 5b is a schematic diagram of the unit circuit of Embodiment 1: a function table of a multi-functional circuit;

[0048] FIG. 6a is a schematic diagram of a logic circuit composed of the unit circuit of Embodiment 1: a circuit structure diagram;

[0049] FIG. 6b is a schematic diagram of a logic circuit composed of the unit circuit of Embodiment 1: a function table of a multi-functional circuit;

[0050] FIG. 7a is a schematic diagram of another logic circuit composed of the unit circuit of Embodiment 1: a circuit structure diagram;

[0051] FIG. 7b is a schematic diagram of another logic circuit composed of the unit circuit of Embodiment 1: a function table of a multi-functional circuit;

[0052] FIG. 8a is a schematic diagram of the adder-subtractor circuit of Embodiment 1: a circuit structure diagram;

[0053] FIG. 8b is a schematic diagram of the adder-subtractor circuit of Embodiment 1: a truth table of input and output signals of a multi-functional circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiment 1

[0054] As shown in FIG. 1, FIG. 2, and FIG. 3, the present invention first introduces a tunable homojunction-based field effect device, which includes an insulating layer 3, a metal electrode layer, a channel material layer 2, and a substrate insulating material 1. The metal electrode layer includes a drain electrode layer 41, a source electrode layer 42, a gate electrode layer A43, and a gate electrode layer B44.

[0055] The gate electrode layer A43 and the gate electrode layer B44 are fabricated side by side on the substrate insulating material 1, and a gap is left therebetween to ensure that the gate electrode layer A43 and the gate electrode layer B44 are non-conducting. The insulating layer 3 is laid on the gate electrode layer A43 and the gate electrode layer B44. The channel material layer 2 is laid on overlapping areas between the gate electrode layer A43 and the insulating layer 3 and between the gate electrode layer B44 and the insulating layer 3, so that the channel material layer 2 is completely isolated from the gate electrode layer A43 and the gate electrode layer B44 by the insulating layer 3, respectively. The drain electrode layer 41 and the source electrode layer 42 are fabricated directly above the channel material layer 2 and placed directly above the left edges and the right edges of the gate electrode layer A43 and the gate electrode layer B44, respectively, while ensuring that the drain electrode layer 41 and the source electrode layer 42 are completely isolated from the gate electrode layer A43 and the gate electrode layer B44 by the insulating layer 3.

[0056] In the present embodiment, the channel material layer 2 is an intrinsic semiconductor with a band gap ranging from 0.5 eV to 1.5 eV and a material thickness of less than 30 nm, which can exhibit bipolar field effect characteristics. The channel material layer 2 can be selected from low-dimensional semiconductor materials such as silicon nanowires, carbon nanotubes, two-dimensional layered materials, or organic semiconductor thin film materials. The metal work function of the drain electrode layer 41 and the source electrode layer 42 is the middle energy value of the band gap of the channel material layer.

[0057] In the present embodiment, the gate insulating layer can be selected from insulating material layers such as a silicon dioxide layer, an aluminum oxide layer, a hafnium oxide layer, a hexagonal boron nitride layer, and a zirconium oxide layer.

[0058] As shown in FIG. 1, the drain electrode layer 41 is applied with the bias voltage V.sub.ds, the source electrode layer 42 is grounded, the gate electrode layer A43 is applied with the gate voltage V.sub.gA, and the gate electrode layer B44 is applied with the gate voltage V.sub.gB.

[0059] In the present embodiment, the channel material layer of the device can be regulated to be an NN-type homojunction, a PP-type homojunction, a PN-type homojunction, and an NP-type homojunction under gate voltage bias. Under the operation of source-drain voltages (V.sub.ds) of different polarities, the forward bias or reverse bias state of the homojunction is further realized to determine whether the current state of the device is on or off. The specific regulation method is as follows:

[0060] As shown in FIG. 4, in the present embodiment, when V.sub.ds>0 and V.sub.gA>0, the device scans V.sub.gB to realize the function of N-type field effect transistor (FET) device. When V.sub.gB>0, the channel homojunction state is an NN junction, and the current state is on. When V.sub.gB<0, the channel homojunction state is an NP junction, and the current state is off.

[0061] In the present embodiment, when V.sub.ds<0 and V.sub.gA<0, the device scans V.sub.gB to realize the function of P-type FET device. When V.sub.gB>0, the channel homojunction state is a PN junction, and the current state is off. When V.sub.gB<0, the channel homojunction state is a PP junction, and the current state is on.

[0062] In the present embodiment, under the combined operation of V.sub.gA<0 and V.sub.gB>0, the channel homojunction state of the device is regulated as a PN junction, and the device scans V.sub.ds to realize the function of a forward diode device and acts as a forward diode. When V.sub.ds>0, the channel homojunction state is a forward-biased PN junction, and the current state is on. When V.sub.ds<0, the channel homojunction state is a reverse-biased PN junction, and the current state is off.

[0063] In the present embodiment, under the combined operation of V.sub.gA>0 and V.sub.gB<0, the channel homojunction state of the device is regulated as an NP junction, exhibiting a reverse diode, and the device scans V.sub.ds to realize the function of a forward diode device. When V.sub.ds>0, the channel homojunction state is a forward-biased NP junction, and the current state is off. When V.sub.ds<0, the channel homojunction state is a reverse-biased NP junction, and the current state is on.

[0064] Thus, a single device can achieve device functions of N-type FET, P-type FET, forward diode, and reverse diode under different electrical operations.

[0065] As shown in FIG. 5a, a multi-functional unit circuit structure E is constructed based on the above-mentioned tunable homojunction field effect device and includes:

[0066] a first input terminal V.sub.in1 for receiving a first input voltage signal;

[0067] a second input terminal V.sub.in2 for receiving a second input voltage signal;

[0068] a third input terminal V.sub.in3 for receiving a third input voltage signal;

[0069] a first tunable homojunction field effect transistor M1, wherein a source S1 of the first tunable homojunction field effect transistor M1 is coupled to the first input terminal, a gate electrode 1a close to the source S1 is connected to the second input terminal, and a gate electrode 1b close to a drain of the first tunable homojunction field effect transistor M1 is coupled to the third input terminal;

[0070] a second tunable homojunction field effect transistor M2, wherein a source S2 of the second tunable homojunction field effect transistor M2 is coupled to the third input terminal, a gate electrode 2a close to the source S2 is connected to the second input terminal, and a gate electrode 2b close to a drain of the second tunable homojunction field effect transistor M2 is coupled to the first input terminal.

[0071] The drain D of the first tunable homojunction field effect transistor is connected to the drain D of the second tunable homojunction field effect transistor, and the output of the connection point therebetween is used as an output terminal V.sub.out.

[0072] In the present embodiment, for the device M1, the input signal V.sub.in2 and the input signal V.sub.in3 determine the type of the device channel homojunction, that is, NN junction, PN junction, PP junction, or NP junction, and the relative potential between the input signal V.sub.in1 and the input signal V.sub.in2 determines the source-drain voltage bias polarity of the device. For the device M2, the input signal V.sub.in1 and the input signal V.sub.in2 determine the type of the device channel homojunction, that is, NN junction, PN junction, PP junction, and NP junction, and the relative potential between the input signal V.sub.in1 and the input signal V.sub.in2 determines the source-drain voltage bias polarity of the device.

[0073] In the present embodiment, the circuit shown in FIG. 5a, when designed according to the scheme of the input signals V.sub.in1, V.sub.in2, and V.sub.in3 shown in FIG. 5b, will show nine different logic operation functions in sequence, including the ‘AND gate’ with the logic operation result of AB; the ‘OR gate’ with the logic operation result of A+B; the ‘Not gate’ with the logic operation result of Ā; the signal following with the logic operation result of A; the maintenance of high level output with the logic operation result of 1; the maintenance of low level output with the logic operation result of 0; the ‘material implication’ with the logic operation result of A+B; the ‘NOT’ operation of ‘material implication’ with the logic operation result of AB; and the borrow operation in subtractions with the logic operation result of AB+AC+BC.

[0074] In the present embodiment, the circuit shown in FIG. 5a can be used to realize three most basic logic functions, ‘AND’, ‘OR’, and ‘NOT’. In principle, the combination of these three logic functions can implement arbitrary logic functions. Further, the circuit can perform the ‘material implication’ logical operation and thus is suitable for more diverse logic constructions. Therefore, taking the circuit of FIG. la as a basic unit and by cascading and combining the basic units of the circuit, a logic circuit capable of performing an arbitrary computing function can be efficiently constructed.

[0075] The specific implementation method of the nine operation functions is as shown in FIG. 5b:

[0076] 1. The input signal V.sub.in1 and the input signal V.sub.in3 respectively input a signal A and a signal B, the input signal V.sub.in2 is at a fixed high level (logic 1), the output signal V.sub.out is ‘AND gate’, respectively, and the logic operation result is AB;

[0077] The input signal V.sub.in2 is at a fixed low level (logic 0), the output signal V.sub.out is an ‘OR gate’, respectively, and the logic operation result is A+B.

[0078] 2. The input signal V.sub.in1 is at a high level (logic 1), the input signal V.sub.in3 is at a low level (logic 0), or the input signal V.sub.in1 is at a low level (logic 0), the input signal V.sub.in3 is at a high level (logic 1), and the input signal V.sub.in2 is the input signal A, then the output signal V.sub.out is ‘Not gate’, and the logic operation result is Ā.

[0079] 3. The input signal V.sub.in1 and the input signal V.sub.in2 are both at a high level (logic 1), or the input signal V.sub.in1 and the input signal V.sub.in2 are both at a low level (logic 0), and the input signal V.sub.in3 is the input signal A, then the output signal V.sub.out is the logical operation result is A.

[0080] 4. The input signal V.sub.in1 is at a high level (logic 1), the input signal V.sub.in2 is at a low level (logic 0), and the input signal V.sub.in3 is the input signal A, then the output signal is always at a high level (logic 1).

[0081] 5. The input signal V.sub.in1 is at a low level (logic 0), the input signal V.sub.in2 is at a high level (logic 1), and the input signal V.sub.in3 is the input signal A, then the output signal is always at a low level (logic 0).

[0082] 6. The input signal V.sub.in1 and the input signal Vint respectively input the signal A and the signal B, the input signal V.sub.in3 is at a fixed high level (logic 1), the output signal V.sub.out is the logic operation result of A+B, the input signal V.sub.in3 is at a fixed low level (logic 0), the output signal V.sub.out is the logic operation result of AB.

[0083] 7. The input signal V.sub.in1, the input signal V.sub.in2 , and the input signal V.sub.in3 respectively input the signal A, the signal B, and the signal C, then the output signal V.sub.out=AB+AC+BC.

[0084] In the present embodiment, only two components are required to implement various logic functions, which saves resources.

[0085] Further, as shown in FIG. 6, in the present embodiment, on the basis of the multi-functional unit circuit structure E described above, two circuit basic units as shown in FIG. 5a are cascaded. The circuit cascade mode is shown in FIG. 6a. The output terminal corresponding to the logic circuit E1 is connected to the second input terminal of the logic circuit E2 to form a logic circuit with five input terminals and one output terminal, which are respectively denoted as the first input terminal V.sub.in1, the second input terminal V.sub.in2, the third input terminal V.sub.in3, the fourth input terminal V.sub.in4, and the fifth input terminal V.sub.in5.

[0086] In the present embodiment, based on the circuit structure shown in FIG. 6a and under the input signal operation mode shown in FIG. 6b, the ‘NAND gate’ with the logical operation result of AB, the ‘NOR gate’ with the logic operation result of A+B, and the ‘majority gate’ with the logic operation result of AB+BC+AC can be implemented in sequence. The specific implementation method is: [0087] (1) If the first input terminal V.sub.in1 and the third input terminal V.sub.in3 input the signals A and B, respectively, and the fourth input terminal V.sub.in4 and the fifth input terminal V.sub.in5input opposite levels, when the second input terminal V.sub.in2 inputs a high level, the NAND gate is implemented with the logic operation result of AB; [0088] (2) When the second input terminal V.sub.in2 inputs a low level, the NOR gate is implemented with the logic operation result of AB; [0089] (3) If the fourth input terminal V.sub.in4 and the fifth input terminal V.sub.in5 input the signals A and B, respectively, the second input terminal V.sub.in2 inputs the signal C, and the first input terminal V.sub.in1 and the third input terminal V.sub.in3 input opposite levels, then the majority gate is implemented with the logic operation result of AB+BC+AC.

[0090] Further, as shown in FIG. 7, in the present embodiment, two circuit basic units shown in FIG. 5a are cascaded with the circuit cascade mode shown in FIG. 7a and respectively denoted as the logic circuit E1 and the logic circuit E2. The output terminal corresponding to the logic circuit E1 is connected to the third input terminal of the logic circuit E2 to form a logic circuit with five input terminals and one output terminal V.sub.out, which are respectively denoted as the first input terminal V.sub.in1, the second input terminal V.sub.in2, the third input terminal V.sub.in3, the fourth input terminal V.sub.in4, and the fifth input terminal V.sub.in5 .

[0091] In the present embodiment, based on the circuit shown in FIG. 7a and according to the signal input operation mode shown in FIG. 7b, the ‘AND gate’ with the logical operation result of ABC, the ‘AND-OR gate’ with the logical operation result of AB+C, the ‘OR-AND gate’ with the logical operation result of (A+B)C, and the ‘OR gate’ with the logical operation result of A+B+C of three input signals can be implemented in sequence.

[0092] In order to realize the above logic functions, the specific implementation method is as follows: [0093] (1) The first input terminal V.sub.in1, the third input terminal V.sub.in3, and the fourth input terminal V.sub.in4 input the signals A, B, and C, respectively, if both the second input terminal V.sub.in2 and the fifth input terminal V.sub.in5 input a high level, then the AND gate is implemented, and the output terminal V.sub.out outputs ABC; [0094] (2) If both the second input terminal V.sub.in2 and the fifth input terminal V.sub.in5 input a low level, then the OR gate is implemented, and the output terminal V.sub.out outputs A+B+C; [0095] (3) If the second input terminal V.sub.in2 is at a high level and the fifth input terminal V.sub.in5 inputs a low level, then the AND-OR gate is implemented, and the output terminal V.sub.out outputs AB+C; [0096] (4) If the second input terminal V.sub.in2 is at a low level and the fifth input terminal V.sub.in5 inputs a high level, then the OR-AND gate is implemented, and the output terminal V.sub.out outputs (A+B)C.

[0097] Further, as shown in FIG. 8a, the structure of the adder-subtractor circuit based on the tunable homojunction field effect device in the present embodiment includes three unit circuits, denoted as the first unit, the second unit, and the third unit, respectively. The specific connection method is:

[0098] The first input terminal of the first unit is connected to the first input terminal of the second unit, which serves as the first input terminal of the adder-subtractor logic circuit and inputs the signal B;

[0099] The second input terminal of the first unit is connected to the third input terminal of the third unit, which serves as the second input terminal of the adder-subtractor logic circuit and inputs the signal A;

[0100] The third input terminal of the first unit is connected to the third input terminal of the second unit, which serves as the third input terminal of the adder-subtractor logic circuit and inputs the signal C;

[0101] The output terminal of the first unit is connected to the second input terminal of the second unit and the first input terminal of the third unit, which serves as the first output terminal of the adder-subtractor logic circuit and outputs the signal B.sub.out;

[0102] The output terminal of the second unit is connected to the second input terminal of the third unit, which serves as the second output terminal of the adder-subtractor logic circuit and outputs the signal C.sub.out;

[0103] The output terminal of the third unit is used as the adder signal output terminal of the adder-subtractor logic circuit to output the signal Sum or the subtractor signal output terminal of the adder-subtractor logic circuit to output the signal Diff.

[0104] The specific structure of each unit and the connection mode between the various units are as follows:

[0105] For the first unit circuit, the input signal B is input to the source terminal (S) of the device M1 and the gate electrode (2b) near the drain terminal (D) of the device M2; the input signal C is input to the source terminal (S) of the device M2 and gate electrode (1b) near the drain terminal (D) of the device M1; the input signal A is input to the gate electrode (1a) near the source terminal (S) of the device M1 and the gate electrode (2a) near the source terminal (S) of the device M2. The output signal B.sub.out is output through the connection point of the drain terminals (D) of the device M1 and the device M2. The input signal and the output signal satisfy the Boolean logic operation: Bout=B.sub.out=BC+BĀ+CĀ.

[0106] For the second unit circuit, the input signal B is input to the source terminal (S) of the device M3 and the gate electrode (4b) near the drain terminal (D) of the device M4. The input signal C is input to the source terminal (S) of device M4 and the gate electrode (3b) near the drain terminal (D) of the device M3. The output signal B.sub.out of the first unit circuit is input to the gate electrode (3a) near the source terminal (S) of the device M3 and the gate electrode (4a) near the source terminal (S) of the device M4. The output signal C.sub.out is output through the connection point of the drain terminals (D) of the device M3 and the device M4. The input signal and the output signal satisfy the Boolean logic operation: C.sub.out=BC+BB.sub.out+CB.sub.out+CB.sub.out=BC+BA+CA.

[0107] For the third unit circuit, the output signal B.sub.out of the first unit circuit is input to the source terminal (S) of the device M5 and the gate electrode (6b) near the drain terminal (D) of the device M6. The input signal A is input to the source terminal (S) of the device M6 and the gate electrode (5b) near the drain terminal (D) of the device M5. The output signal C.sub.out of the second unit circuit is input to the gate electrode (5a) near the source terminal (S) of the device M5 and the gate electrode (6a) near the source terminal (S) of the device M6. The output signal Sum or Diff is output through the connection point of the drain terminals (D) of the device M5 and the device M6. The input signal and the output signal satisfy the Boolean logic operation: Sum (or Diff)=AB.sub.out+AC.sub.out+B.sub.outC.sub.out=A−B⊕C.

[0108] In the present embodiment, the input signals of the circuit are A, B, and C, and the output signals of the circuit are B.sub.out, C.sub.out, and Sum (or Diff). The output signals B.sub.out and Diff respectively represent results of the borrow operation and the difference operation of subtractor, and the output signals C.sub.out and Sum respectively represent results of the carry operation and the summation operation of adder. Thus, the logical operations of the adder and the subtractor are simultaneously realized based on the same circuit.

[0109] FIG. 8b is a truth table of input and output of the circuit of FIG. 8a,

[0110] When A, B and C are all at a high level, the output terminal B.sub.out is at a high level, the output terminal C.sub.out is at a high level, and the output terminal Sum or Diff is at a high level;

[0111] When A and B are both at a high level and C is at a low level, the output terminal B.sub.out is at a low level, the output terminal C.sub.out is at a high level, and the output terminal Sum or Diff is at a low level;

[0112] When A and C are both at a high level and B is at a low level, the output terminal B.sub.out is at a low level, the output terminal C.sub.out is at a high level, and the output terminal Sum or Diff is at a low level;

[0113] When B and C are both at a low level and A is at a high level, the output terminal B.sub.out is at a low level, the output terminal C.sub.out is at a low level, and the output terminal Sum or Diff is at a high level;

[0114] When B and C are both at a high level and A is at a low level, the output terminal B.sub.out is at a high level, the output terminal C.sub.out is at a high level, and the output terminal Sum or Diff is at a low level;

[0115] When A and C are both at a low level and B is at a high level, the output terminal B.sub.out is at a high level, the output terminal C.sub.out is at a low level, and the output terminal Sum or Diff is at a high level;

[0116] When B and A are both at a low level and C is at a high level, the output terminal B.sub.out is at a high level, the output terminal C.sub.out is at a low level, and the output terminal Sum or Diff is at a high level;

[0117] When A, B, and C are all at a low level, the output terminal B.sub.out is at a low level, the output terminal C.sub.out is at a low level, and the output terminal Sum or Diff is at a low level.

[0118] By making full use of device functions, the logic unit circuit designed in the present invention has the ability to perform reconfigurable logic functions. Further, the logic circuit constructed by cascading unit circuits can not only perform logic functions of full adder, subtractor, etc. but also require greatly reduced transistor resources and occupied area compared with traditional CMOS technology. Therefore, the structure proposed by the present invention is simpler, and the design scheme for the circuit with reconfigurable logic function is highly competitive in terms of meeting the low power consumption application requirements in the future.