UWB pulse generator

Abstract

An ultra-wideband pulse generator, for radio communication at frequencies of 2 to 11 GHz comprises an oscillator providing an output signal at carrier frequency F0 followed by a radiofrequency switching transistor and a control circuit controlling the gate of the transistor to turn it on for duration T corresponding to the desired duration of a UWB pulse. The control circuit is arranged to successively apply, during the same UWB pulse, a first gate voltage turning the transistor on with first internal resistance value for a first part of duration T, a second gate voltage that turns the transistor on with second internal resistance value, different from the first, for a second part of duration T. These internal resistances cause the oscillation to be attenuated differently for duration T of the pulse, allowing the spectrum of the pulse to maintain it within the spectral templates imposed by the radio communication standards.

Claims

1. A UWB pulse generator comprising: an oscillator that provides an oscillating signal at a carrier frequency F.sub.0 followed by a radiofrequency switching transistor configured for selectively connecting the oscillating signal to an output of the UWB pulse generator and a control circuit that controls a gate of the radiofrequency switching transistor in order to turn the radiofrequency switching transistor it on for a duration of time T that corresponds to a desired duration of a UWB pulse, wherein the control circuit is arranged so as to successively apply, during one and the same UWB pulse, a first gate voltage that turns the radiofrequency switching transistor on with a first internal resistance value for a first part of the duration T, then at least a second gate voltage that turns the radiofrequency switching transistor on with a second internal resistance value, different from the first value, for a second part of the duration T.

2. The UWB pulse generator of claim 1, wherein the control circuit comprises: two logic inverters supplied with a supply voltage that have their outputs connected to a gate of the radiofrequency switching transistor via respective resistors; and a sequencing circuit that sets up, at an input of the first logic inverter, a first logic signal for turning the radiofrequency switching transistor on and, at an input of the second logic inverter, a second logic signal for turning the switching transistor on, with a partial overlap between the first and the second logic signal, allowing defining at least one period of time during which only one of the two logic signals is at a level for turning the radiofrequency switching transistor on and one period of time during which both logic signals are at this level, the two periods being adjacent.

3. The UWB pulse generator of claim 2, wherein the oscillating signal generated by the oscillator is a differential signal, and there are two radiofrequency switching transistors that operate symmetrically and are controlled symmetrically by the two logic inverters.

4. The UWB pulse generator of claim 2, wherein the resistors that are connected between an output of an inverter and the gate of a radiofrequency switching transistor are composed of multiple resistors that are switched in order to select a chosen resistance value.

5. The UWB pulse of claim 2, wherein the logic inverters are composed of an array of multiple inverters in parallel with different output impedance characteristics, one logic inverter being selected based on desired resistance characteristics and the logic inverters being able to be selectively placed in a high-impedance state if the logic inverters are not selected.

6. The UWB pulse generator of claim 2, wherein a value of the supply voltage of the logic inverters is modifiable.

7. The UWB pulse generator of claim 1, wherein the oscillator is a LC oscillator with a pair of differential branches whose operation is switched by application or interruption of a supply current to the pair of differential branches, the generator configured to modify the supply current of the pair of branches during the UWB pulse.

8. The UWB pulse generator of claim 7, further comprising a current injection circuit configured to inject a current into one of the outputs of the differential branches so as to unbalance said differential branches during a UWB pulse initiation phase in order to impose an oscillation phase upon initiation.

9. A UWB pulse generator comprising: an oscillator that provides an oscillating signal at a carrier frequency F.sub.0 followed by a radiofrequency switching transistor and a control circuit that controls a gate of the radiofrequency switching transistor in order to turn the radiofrequency switching transistor on for a duration of time T that corresponds to a desired duration of a UWB pulse, wherein the control circuit is arranged so as to successively apply, during one and the same UWB pulse, a first gate voltage that turns the radiofrequency switching transistor on with a first internal resistance value for a first part of the duration T, then at least a second gate voltage that turns the radiofrequency switching transistor on with a second internal resistance value, different from the first value, for a second part of the duration T, wherein the control circuit comprises: two logic inverters supplied with a supply voltage that have their outputs connected to a gate of the radiofrequency switching transistor via respective resistors; and a sequencing circuit that sets up, at an input of the first logic inverter, a first logic signal for turning the radiofrequency switching transistor on and, at an input of the second logic inverter, a second logic signal for turning the switching transistor on, with a partial overlap between the first and the second logic signal, allowing defining at least one period of time during which only one of the two logic signals is at a level for turning the radiofrequency switching transistor on and one period of time during which both logic signals are at this level, the two periods being adjacent.

10. The UWB pulse generator of claim 9, wherein the oscillating signal generated by the oscillator is a differential signal, and there are two radiofrequency switching transistors that operate symmetrically and are controlled symmetrically by the two logic inverters.

11. The UWB pulse generator of claim 9, wherein the resistors that are connected between an output of an inverter and the gate of a radiofrequency switching transistor are composed of multiple resistors that are switched in order to select a chosen resistance value.

12. The UWB pulse of claim 9, wherein the logic inverters are composed of an array of multiple inverters in parallel with different output impedance characteristics, one logic inverter being selected based on desired resistance characteristics and the logic inverters being able to be selectively placed in a high-impedance state if the logic inverters are not selected.

13. The UWB pulse generator of claim 9, wherein a value of the supply voltage of the logic inverters is modifiable.

14. The UWB pulse generator of claim 9, wherein the oscillator is a LC oscillator with a pair of differential branches whose operation is switched by application or interruption of a supply current to the pair of differential branches, the generator configured to modify the supply current of the pair of branches during the UWB pulse.

15. The UWB pulse generator of claim 14, further comprising a current injection circuit configured to inject a current into one of the outputs of the differential branches so as to unbalance said differential branches during a UWB pulse initiation phase in order to impose an oscillation phase upon initiation.

16. A UWB pulse generator comprising: an oscillator that provides an oscillating signal at a carrier frequency F.sub.0 followed by a radiofrequency switching transistor configured for selectively connecting the oscillating signal to an output of the UWB pulse generator and a control circuit that controls a gate of the radiofrequency switching transistor in order to turn the radiofrequency switching transistor on for a duration of time T that corresponds to a desired duration of a UWB pulse, wherein the control circuit is arranged so as to successively apply, during one and the same UWB pulse, a first gate voltage that turns the radiofrequency switching transistor on with a first internal resistance value for a first part of the duration T, then at least a second gate voltage that turns the radiofrequency switching transistor on with a second internal resistance value, different from the first value, for a second part of the duration T, wherein the control circuit comprises: two logic inverters supplied with a supply voltage that have their outputs connected to the gate of the radiofrequency switching transistor via respective resistors; and a sequencing circuit that sets up, at the input of the first logic inverter, a first logic signal for turning the radiofrequency switching transistor on and, at an input of the second logic inverter, a second logic signal for turning the switching transistor on, with a partial overlap between the first and the second logic signal, allowing defining at least one period of time during which only one of the two logic signals is at a level for turning the radiofrequency switching transistor on and one period of time during which both logic signals are at this level, the two periods being adjacent.

17. The UWB pulse generator of claim 16, wherein the oscillating signal generated by the oscillator is a differential signal, and there are two radiofrequency switching transistors that operate symmetrically and are controlled symmetrically by the two logic inverters.

18. The UWB pulse generator of claim 16, wherein the resistors that are connected between an output of an logic inverter and the gate of a radiofrequency switching transistor are composed of multiple resistors that are switched in order to select a chosen resistance value.

19. The UWB pulse of claim 16, wherein the logic inverters are composed of an array of multiple inverters in parallel with different output impedance characteristics, one logic inverter being selected based on desired resistance characteristics and the logic inverters being able to be selectively placed in a high-impedance state if the logic inverters are not selected.

20. The UWB pulse generator of claim 16, wherein a value of the supply voltage of the logic inverters is modifiable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other characteristics and advantages of the invention will become apparent upon reading the detailed description which follows, given with reference to the appended drawings in which:

(2) FIG. 1, already described, shows a UWB pulse with a carrier frequency of 4 GHz, with a duration of around 5 nanoseconds;

(3) FIG. 2, already described, shows the spectrum of this pulse, with a passband bandwidth at −10 dB of around 500 MHz;

(4) FIG. 3, already described, shows the principle of a pulse generator with an LC oscillator and a downstream radiofrequency switch;

(5) FIG. 4 shows the generator according to the invention with an oscillator of a particular type;

(6) FIG. 5 shows the variation profile of the gate voltage of the switching transistor during the UWB pulse;

(7) FIG. 6 shows an exemplary variation curve of the internal resistance of the switching transistor in the “on” state;

(8) FIG. 7 shows an equivalent circuit diagram of the switching transistor;

(9) FIG. 8 shows a control circuit allowing the invention to be implemented;

(10) FIG. 9 shows an equivalent circuit diagram of when a single inverter I1 turns the switching transistor on;

(11) FIG. 10 shows an equivalent circuit diagram of when the other inverter I2 turns the switching transistor on;

(12) FIG. 11 shows the input signals that are applied to the control circuit of FIG. 8 and the resulting gate voltage profile of the switching transistor;

(13) FIG. 12 shows a complete diagram of the generator, including means for controlling the binary phase (0 or 180°) of the pulse and means for controlling the form of the current of the oscillator;

(14) FIG. 13 shows an operating timing diagram of the generator of FIG. 12.

DETAILED DESCRIPTION

(15) The invention is based upon the principle of the architecture of FIG. 3, but with a particular control of the switch SW. It will be described in more detail in a configuration using an oscillator of a particular type, which is an LC resonating-charge oscillator with symmetrical output, supplied with current by a current source that is switched in order to activate or deactivate the oscillator. However, the invention is applicable to other types of oscillator.

(16) FIG. 4 shows the generator according to the invention. The oscillator comprises a pair of two balanced differential branches that are supplied with power by, at one end, a supply voltage source Vdd and, at the other end, by a common current Ip. This common current is present for a duration T.sub.OSC that is longer than the duration T of the UWB pulse. It may be permanent and may be interrupted, in order to reduce consumption, only in the phases during which the UWB communication is interrupted. The control circuit CTRL, located downstream, will select a time window of the oscillation, for a duration T of a few nanoseconds, that will be the duration of the pulse.

(17) The differential branches each comprise a transistor, T1 for the first branch, T′1 for the second branch. A load is inserted between the drain of the transistor and the supply voltage source Vdd. This load is an LC circuit, resonating at the carrier frequency F.sub.0 of the UWB pulse to be transmitted. In the example shown, the load is shared between the branches; it comprises an inductor L.sub.r and a capacitor C.sub.r in parallel, as well as a damping resistor R.sub.r that may be the intrinsic internal resistance of the inductor. These elements in parallel are connected between the output S of the first branch and the output S′ of the second branch. The outputs S and S′ may be made at the drains of the respective transistors T1 and T′1 of the first and the second branch.

(18) The supply voltage source is preferably connected, as is the case in FIG. 4, to a center tap on the loading inductor L.sub.r in order to ensure that the oscillator receives a continuous supply.

(19) The oscillation is generated between the outputs S and S′, which are connected to the primary winding of a transformer TR.

(20) The loading inductor L.sub.r of the resonant circuit does not have to be present if the inductance on the side of the primary of the transformer has a value that is sufficient to fulfill the role of the loading inductor L.sub.r in the LC resonant circuit. In this case, provision must be made for the continuous voltage supply source Vdd to be connected to a center tap on the primary of the transformer in order to be able to supply the voltage Vdd symmetrically to both differential branches.

(21) The continuous oscillation present at the output of the transformer TR is applied through a switch to the output pads P.sub.L and P′.sub.L of the integrated circuit in which the pulse generator is implemented, and from there to a transmission antenna ANT. The switch defines, when it is turned on, a time window of duration T in which the oscillation may be transferred to the output pads. In a symmetrical construction as shown in FIG. 4, provision may be made for the switch to be doubled and comprise two high-speed switching transistors each connected between a respective terminal of the secondary winding of the transformer and a respective output pad. In an asymmetrical configuration, the switch may comprise a single transistor.

(22) The switches are radiofrequency switching transistors SW, SW′, i.e. transistors with very fast switching (faster than the duration of the UWB pulses). The duration of switching (passing from the “off” state to the “on” state or vice versa) is multiple times, for example at least five times, faster than the duration T of the pulse, the latter potentially being around 1 to 5 nanoseconds.

(23) A control circuit CTRL defines the time window of duration T in which the oscillation received from the secondary of the transformer will be transmitted by the switch toward the output pads. Outside the duration T, the oscillation continues but is not transmitted.

(24) The control circuit here has a function that is not a simple “on/off” switching control function, but rather a switching function with control of the control voltage value applied to the gates of the transistors SW and SW′ in the “on” state for the duration of the pulse. It sets up gate voltage values according to a well determined sequence within the duration T and, to this end, its operation may be controlled by a clock H.

(25) FIG. 5 shows an exemplary time profile of the voltage V.sub.L applied by the control circuit CTRL to the gate of one of the transistors (the gate voltage is the same for both transistors) for a duration T. This voltage comprises at least two different levels V.sub.L1 and V.sub.L2 for which, taking into account the technology used to implement the transistor, the internal resistance of the transistor in the “on” state acquires two significantly different values. One of the voltage levels, V.sub.L2, may be the general supply level Vdd of the integrated circuit. Here, there are three voltage levels V.sub.L1, V.sub.L2, and V.sub.L3.

(26) In the example of FIG. 5, it is assumed that lower gate voltage levels V.sub.L1 and V.sub.L3 are applied at the start and at the end of the pulse and a higher level, V.sub.L2, is applied in the middle of the pulse. It must be understood that it is possible to have identical levels V.sub.L1=V.sub.L3 at the start and at the end, respectively, and a higher level V.sub.L2 in the middle, or even to have the level V.sub.L2 at the start or at the end (but not both) rather than a lower level V.sub.L1 or V.sub.L3.

(27) The voltage level variation at the gate of the switching transistors induces a variation in the attenuation by the switching transistors of the current level of the oscillation transmitted by the transformer TR. This temporal variation in the attenuation results from the fact that the internal resistance of the switching transistors SW, SW″ varies depending on the gate voltage. The temporal variation in the attenuation, even during the UWB pulse, modifies the rising and falling slopes and therefore the spectrum of this pulse. The modification chiefly acts upon the side lobes of the spectrum and it is therefore possible to look for voltage profile forms, such as the simple profile with two levels of FIG. 5, that improve the spectrum in a desired way, in particular in such a way as to reduce the side lobes in order to respect the template specification.

(28) The attenuation of the oscillation at a given instant depends on the impedance of the antenna and the series impedances of the transistors in the “on” state. The impedance of the transistor involves the resistance R.sub.ON of the conductive transistor and the impedance of the capacitor C.sub.ON between the drain and the source of this transistor, namely 1/(2πF.sub.0C.sub.ON).

(29) FIG. 6 shows an exemplary internal resistance curve of an NMOS radiofrequency switching transistor as a function of the voltage V.sub.L that is applied to the gate of the transistor. The internal resistance has a value of around 7 ohms when the voltage Vdd (here: 1.2 volts) is applied to the gate, a value of 50 ohms when V.sub.L is equal to 0.35 volts, and a value of around 170 ohms when V.sub.L=0.25 volts. The variation is therefore large and serves, according to the invention, to attenuate the start and/or the end, or even the middle, of the transmitted pulse in order to modify the spectrum thereof.

(30) In a digital example at a carrier frequency F.sub.0 of 4 GHz, the resistance R.sub.ON of the transistor follows the curve of FIG. 6 and has a value of 7 ohms at a gate voltage V.sub.L=Vdd=1.2 volts. Its source-drain capacitance is 80 femtofarads and the impedance of the antenna is 50 ohms. It has been found to be possible to attenuate the pulse at an attenuation ratio of around 2.2 for a gate voltage of 0.3 volts, and with a ratio of around 3.4 for a gate voltage of 0.24 volts. In another example with the same digital values but at a frequency F.sub.0 of 8 GHz, the attenuation ratios are about 2 and 2.8 for 0.3 volts and 0.24 volts, respectively.

(31) FIG. 7 shows a radiofrequency switching transistor SW. It is an NMOS transistor (faster and a better conductor than a PMOS transistor). Its particularity is that its channel is not directly at the potential of the substrate (0 volts) but rather it is connected to the substrate via a resistor R.sub.B of a few kiloohms, whose function is to reduce the conductivity of the drain-substrate and source-substrate diodes, thereby improving power transmission and reducing insertion losses. Furthermore, its gate is controlled via a series resistor R.sub.E of a few kiloohms that reduces the variations in the gate-source voltage when the control voltage varies.

(32) FIG. 8 shows a preferred exemplary embodiment of the control circuit CTRL allowing the invention to be implemented. The sources of the switching transistors are connected to an antenna that is symbolized by an antenna impedance R.sub.ANT. The drains receive the signals issued by the secondary of the transformer TR. The gates receive a gate voltage V.sub.L that is provided by the control circuit. The control circuit comprises two logic inverters I1 and I2, and four resistors: R0 et R′0, with the same value, respectively connected between the output of the inverter I1 and the gates of the switching transistors SW and SW′; R1 and R′1, with the same value, respectively connected between the output of the inverter I2 and the gates of the switching transistors SW and SW′.

(33) The resistors R0, R′0, R1, R′1 constitute resistive loads at the output of the inverters I1 and I2 and the output voltage produced by the inverters in the “on” state depends not only on the value of these loads, but also on the intrinsic internal resistances of the inverters. The intrinsic internal resistances of the inverters furthermore depend on their output logic state.

(34) The inverters receive, from a sequencing circuit SEQ controlled by a clock H, respective input logic signals S.sub.E1 and S.sub.E2 that are signals for blocking, then turning on, the switching transistors SW and SW′. These signals are at the high logic level outside the UWB pulses and the inverters then block the conduction of the transistors. They drop to the low level during time slots, the combination of which creates a gate voltage profile such as, for example, that of FIG. 5. They do not have the same duration and they are in partial overlap; the total duration from the first falling edge of the slots until the last rising edge of the slots is the duration T of the pulse.

(35) When the two inverters receive as input a signal for blocking the transistors SW and SW′ (S.sub.E1 and S.sub.E2 at the high logic level), they both provide a zero output voltage and this voltage is transferred to the gates of the switching transistors SW and SW′.

(36) When they both receive as input a signal for turning on the transistors SW and SW′ (S.sub.E1 and S.sub.E2 at the low logic level), they both provide an output voltage Vdd and this voltage is transferred to the gates of the switching transistors.

(37) However, when one of the inverters receives a blocking signal and the other receives a signal for turning it on, the intermediate voltage V.sub.L applied to the gates may be calculated as a function of the resistors R0 and R1 and the internal resistances of the inverters.

(38) The inverters are generally composed of a pair of transistors in series, the transistors being a PMOS transistor and an NMOS transistor. In principle, the NMOS transistor conducts in order to provide a blocking signal to the transistors SW and SW′ and the internal impedance of the inverter is then the resistance R.sub.N of the NMOS transistor in the “on” state; conversely, the PMOS transistor conducts in order to provide a signal for turning the transistors on and the internal impedance of the inverter is then the resistance R.sub.N of the PMOS transistor in the “on” state. The resistances R.sub.N and R.sub.P are generally different but in principle they are the same for both inverters. Nevertheless, provision may be made for the inverters to be different and to have different internal resistances, both for the NMOS transistor and for the PMOS transistor.

(39) If the inverter I1 is alone in providing a signal for turning the transistors on, its internal resistance is R.sub.P1 at the moment at which the internal resistance of the inverter I2 is R.sub.N2. It may therefore be assumed that there is a powered resistive voltage divider between the supply voltage Vdd and the ground; this voltage divider provides identical intermediate voltages V.sub.L and V′.sub.L to the junction point between the resistors R0 and to the junction point between the resistors R1. These intermediate voltages are applied to the gates of the high-speed switching transistors.

(40) The equivalent diagram of the voltage divider is shown in FIG. 9 in the case in which the inverter I1 is alone in providing a signal for turning the transistors on, and in FIG. 10 in the case in which the inverter I2 is alone in providing a signal for turning the transistors on. The resistors R0 and R′0 are identical and have been represented by two resistors R0. Likewise for R1 et R′1.

(41) It can be shown that in the first case, the voltage V.sub.L=V′.sub.L is:
V.sub.L1=V′.sub.L1=Vdd×[R1+2R.sub.N2]/[2R.sub.N2+2R.sub.P1+R0+R1],
while in the second case it becomes:
V.sub.L3=V′.sub.L3=Vdd×[R0+2R.sub.N1+]/[2R.sub.N1+2R.sub.P2+R0+R1].

(42) For example, if R.sub.N1=500 ohms, R.sub.N2=250 ohms, R.sub.P1=4000 ohms, R.sub.P2=5000 ohms; if Vdd=1.2 volts and if R0=2500 ohms and R1=2000 ohms are chosen, it is found that V.sub.L1≈0.23 volts and V.sub.L3=0.27 volts.

(43) On the curve in FIG. 6, it may be seen that the resistances of the high-speed switching transistors are then around 240 ohms and 120 ohms respectively.

(44) If a profile such as that of FIG. 5 is used, only the inverter I1 is activated in order to turn the transistors SW and SW′ on at the start of the pulse, then the two switches are simultaneously activated in the middle of the pulse, and finally only the inverter I2 is activated at the end of the pulse. The resistance of the radiofrequency switching transistor in the “on” state is 240 ohms at the start, then around 7 ohms, then 120 ohms.

(45) In order to define the desired voltage values V.sub.L for each phase precisely and in a controlled manner, provision may be made for the resistors R0 and/or R1 to be implemented by an array of resistors in parallel that may be turned on and off by switches in order to give a desired value to R0 and/or R1.

(46) Provision may also be made for each inverter to be composed of an array of multiple inverters in parallel with different output impedance characteristics R.sub.P, R.sub.N, one inverter being selected on the basis of desired resistance characteristics and the inverters being able to be selectively placed in a high-impedance state if they are not selected.

(47) Lastly, as the value of the supply voltage of the inverters plays a role in the calculation of V.sub.L, provision may be made for this supply voltage not to be necessarily equal to the general supply voltage Vdd. For example, the supply voltage of the inverters is a voltage that is lower than Vdd; it may be obtained by inserting a resistor, diodes or any other regulating element between the general supply Vdd and the sources of the transistors of which the inverters are composed. The resistor or the diodes may be controllable in order to define a desired supply voltage of the inverters, and this supply voltage may be different for the two inverters.

(48) FIG. 11 shows a timing diagram for the turning on of the two switches I1 and I2 by the signals S.sub.E1 and S.sub.E2 that are generated in the control circuit CTRL and applied to the inputs of the inverters I1 and I2 (turning the switching transistors on for S.sub.E1 or S.sub.E2 at the low level); the resulting voltage profile V.sub.L, V.sub.L′ at the gates of the transistors is shown in the case in which only switch I1 is activated at the start and at the end of the pulse; the voltage V.sub.L successively acquires the values V.sub.L1, V.sub.L2=Vdd, and then V.sub.L1 again. Also shown is the oscillation that occurs on the secondary of the transformer TR and the pulse UWB in the window of duration T, with a pulse amplitude envelope that is attenuated at the start and at the end of the pulse.

(49) In the foregoing, the oscillator is assumed to have been operating with a constant current Ip before, during and after the duration T of the UWB pulse, meaning that a constant current source of value Ip was being switched in an “on/off” manner in order to turn it on when an oscillation was to be set up and to turn it off when no oscillation was to be set up.

(50) However, provision may be made for the current source to be switched stepwise between multiple values Ip1, Ip2, Ip3, etc.

(51) In this case, a current-switching circuit CCOM provides the current Ip. This circuit comprises multiple current sources in parallel, allowing current values Ip1, Ip2, Ip3, etc. to be provided, and switches that are associated with each current source in order to selectively control the sources so as to set up the desired current at a given instant. Each current value may be set up either by a single source with the value Ip1, Ip2, Ip3, etc. or by multiple sources in parallel whose sum is equal to Ip1, Ip2 or Ip3, etc. A sequencer SEQ2 controlled by the general clock H precisely defines the instants for switching the current.

(52) FIG. 12 shows the oscillator LC switched by variable current, with the same elements as in FIG. 4 and a current-switching circuit CCOM.

(53) In the case in which the oscillator LC so comprises multiple current sources that may be switched according to very precise sequences, provision may be made for the value of the source current to be modified during the pulse of duration T. This modification induces changes in the level of the oscillation received by the antenna downstream of the radiofrequency switching transistors SW, SW′. These changes in level may be combined with the changes in attenuation introduced by the switching transistors in order to fine-tune the UWB pulse spectrum.

(54) All of the control signals (signals that control the various current values and the signals that define the various gate voltages of the radiofrequency switching transistors) must be controlled jointly in order to respond to the need to respect the spectral template specification.

(55) For communication with frequency modulation, it is possible to act upon the value of the variable capacitance C.sub.r of the oscillator (FIG. 4 or FIG. 12) in order to modulate the frequency from one pulse to the next. The capacitor may then be composed of a varactor diode or equivalent; the capacitance varies depending on a bias voltage applied to the diode and the bias voltage varies, for example, between two values; this allows binary modulation as a function of binary information to be transmitted, and the resulting frequency variation may be detected in a receiver.

(56) For communication with amplitude modulation, it is possible to act upon the value of the supply current Ip of the differential pair at the peak of the variation envelope of the signal level during the pulse. By modulating the value of the supply current in a binary manner between two levels (or in an “on/off” manner for OOK modulation) from one pulse to the next, the transmitted pulse is modulated in amplitude and this modulation may be detected in a detector.

(57) For binary phase-shift keying (BPSK), two current-injecting branches, respectively connected to the two outputs S and S′, may be added to the oscillator as shown in FIG. 12, along with a phase control circuit that allows an injection of current into either one or the other injection branch just as an oscillation is initiated in the oscillator, i.e. just as a supply current Ip is applied to the differential pair, after which the injected current is quenched in the two branches.

(58) Thus, at the start of the pulse, the differential branches are unbalanced due to the current injected into one of the outputs, and an oscillation initiation phase is defined as a function of the direction of this imbalance. Two opposite phases are possible depending on the direction of the imbalance, since either one or the other of the differential branches becomes conductive first when the current-switching circuit allows a current to flow through the pair of differential branches.

(59) FIG. 12 shows these two injecting branches and the phase control circuit PHC.

(60) The group of two bypass branches comprises an injection current source (current of amplitude Id) common to both branches that are connected at their base; the injecting branches each comprise a respective transistor T2, T′2; the injection current source draws a current Id from the two injecting branches that are connected at their base by the emitters of these two transistors. The transistors T2 and T′2 are not on at the same time, so that the current (−Id) is injected either into the output S or into the output S′ depending on whether the transistor T2 or the transistor T′2 has been turned on. The transistors T2 and T′2 may be simultaneously blocked when no current is to be injected into either the output S or the output S′.

(61) Depending on the desired phase upon initiation of the oscillation, the transistor T2 or the transistor T′2 is turned on just as the oscillation is initiated, i.e. just before a current Ip is applied to the oscillator; then this transistor remains on for a brief moment, after which it is blocked once more for the entirety of the remainder of the duration of the oscillation.

(62) If it is the transistor T2 that is on at the start of the oscillation, it is the transistor T1 that tends to conduct initially upon initiation of the oscillation. If, on the other hand, it is the transistor T′2 that is on for the first part of the duration T, it is the transistor T1, rather than the transistor T1, that tends to conduct initially upon initiation of the oscillation. The initiation phase will therefore be inverted depending on the side from which the current Id is injected. This phase is subsequently maintained throughout the oscillation.

(63) The phase control circuit therefore initially sets up a control signal for turning the transistor on ST2 at the gate of the transistor T2 or a control signal ST′2 at the gate of the transistor T′2 depending on the desired phase. These signals are preferably set up on the basis of a periodic synchronization signal CLK_PH that is composed of slots that define, in each period, the start and the end of the application of a bypass current; these slots are applied to two AND gates of which one receives a logic signal PH for selecting the phase PH and the other the inverse PH_B of this signal PH via an inverter. The outputs of the AND gates provide the signals ST2 and ST′2 that are applied to the gates of the transistors T2 and T′2.

(64) The timing diagram of FIG. 13 shows the phase control signals and the UWB pulse generated, with two different phase values, 0 and 180°, for the two UWB pulses shown; all of these signals are set up by sequencing circuits based on a general clock H that is not shown, allowing the instants corresponding to the starts and ends of the various signals to be very precisely defined.

(65) The following signals are shown:

(66) CLK, representing the periodicity of the UWB pulses; CLK is shown in the form of periodic slots of duration T and of period Tp, corresponding to the desired rate of transmission of the UWB pulses;

(67) a timing signal CLK_PH of the same period Tp and whose duration T.sub.INI defines the duration for which the signals ST2 or ST′2 must be applied during the initialization of the oscillation;

(68) a phase selection signal PH, first at the high logic level to define a 0 phase, then at the low level to define a 180° phase;

(69) a signal ST2 that is generated by one of the AND gates for the zero phase;

(70) a signal ST′2 that is generated by the other AND gate for the opposite 180° phase;

(71) a current Ip applied to the differential pair (in the simplest case of a current Ip set up at a single constant level throughout the duration of the oscillation); this current is set up with the transmission period Tp of the UWB pulses, and for a duration T.sub.OSC that is shorter than Tp;

(72) an oscillation V.sub.OSC generated by the current Ip, with an initiation phase of this oscillation that has two opposite values depending on whether the signal ST2 or the signal ST′2 is issued upon initiation of the oscillation;

(73) a voltage V.sub.L for turning on the radiofrequency switching transistors SW and SW′ in the time slot of duration T and with a profile that allows a variable attenuation over the course of this duration;

(74) a UWB pulse in the clock pulse of duration T that reproduces the phase of the oscillation voltage V.sub.OSC, the first pulse having a 0° phase and the second having a 180° phase.

(75) In FIG. 13, it is assumed that the current Ip is not acted upon for the duration T, but as explained above, it is possible to do it from the moment that the switched oscillator LC comprises multiple current sources and control circuits of these sources synchronized with the clocks that generate the starts and ends of the UWB pulses.