RADIATION-EMITTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP

Abstract

The invention relates to a radiation-emitting semiconductor chip, having: a semiconductor body comprising an active region which is designed to generate electromagnetic radiation; a resonator which comprises a first end region and a second end region; and at least one cut-out in the semiconductor body, said cut-out passing completely through the active region, wherein: the active region is situated in the resonator, and the cut-out defines a reflectivity for the electromagnetic radiation. The invention also relates to a radiation-emitting semiconductor component, a method for producing a radiation-emitting semiconductor chip, and a method for producing radiation-emitting semiconductor components.

Claims

1. A radiation emitting semiconductor chip comprising, a semiconductor body comprising an active region configured to generate electromagnetic radiation, a resonator comprising a first end region and a second end region, and at least one recess in the semiconductor body, which completely penetrates the active region, wherein the active region is arranged in the resonator, and the recess presets a reflectivity for the electromagnetic radiation, and a highly reflective mirror layer is arranged on the semiconductor body in the second end region, wherein the recess is arranged in the first end region or the recess is arranged between the first end region and the second end region.

2. (canceled)

3. The radiation emitting semiconductor chip according to claim 1, wherein a first contact layer is arranged on the semiconductor body, which is configured to impress a current into the semiconductor body.

4. The radiation emitting semiconductor chip according to claim 1, wherein a second contact layer is arranged on the semiconductor body, the first contact layer is spaced apart from the second contact layer in lateral direction, and the recess is arranged between the first contact layer and the second contact layer.

5. The radiation emitting semiconductor chip according to claim 1, wherein a dielectric layer is arranged in the recess.

6. The radiation emitting semiconductor chip according to claim 1, wherein the dielectric layer completely covers at least one side surface of the recess, or the dielectric layer is spaced apart from each side surface of the recess.

7. The radiation emitting semiconductor chip according to claim 1, wherein a further dielectric layer is arranged on the dielectric layer, and/or the further dielectric layer is arranged on at least one side surface of the recess, or the further dielectric layer is spaced apart from each side surface of the recess.

8. The radiation emitting semiconductor chip according to claims 5, wherein a waveguide structure is arranged in the recess in which the dielectric layer and/or the further dielectric layer is arranged.

9. A radiation emitting semiconductor device comprising, at least two radiation emitting semiconductor chips according to claim 1, wherein the semiconductor chips are arranged next to one another in lateral direction.

10. A method for producing a radiation-emitting semiconductor chip, comprising: providing a semiconductor body comprising an active region configured to generate electromagnetic radiation, generating a recess in the semiconductor body, which completely penetrates the active region, generating a resonator comprising a first end region and a second end region, wherein the active region is arranged in the resonator, wherein the recess presets a reflectivity for the electromagnetic radiation a highly reflective mirror layer is arranged on the semiconductor body in the second end region, and the recess is arranged in the first end region, or the recess is arranged between the first end region and the second end region.

11. A method for producing radiation emitting semiconductor devices, comprising: providing a semiconductor wafer comprising active regions each configured to generate electromagnetic radiation, generating recesses in the semiconductor wafer, which completely penetrate the active regions, respectively, generating resonators each of which comprising a first end region and a second end region, wherein one of the active regions is arranged in one of the resonators, respectively, singulating the semiconductor wafer into semiconductor devices, wherein the recesses, which are each adjacent to one of the resonators, preset a first reflectivity for the electromagnetic radiation in the first end region and preset a second reflectivity for the electromagnetic radiation in the second end region and wherein a layer stack is generated in the recesses, and the layer stack is at least partially removed in each case in a second region in the recesses.

12. (canceled)

13. The method according to claim 11, wherein a mask layer is applied to the layer stack, and the mask layer covers in each case a first region of the layer stack in the recesses

14. (canceled)

15. The method according to claim 11, wherein the layer stack has an etch stop layer arranged between dielectric layers of the layer stack.

16. The method according to claim 13, wherein a further layer stack is generated in the recesses on the mask layer and the layer stack, and the further layer stack is completely removed in each case in the first region in the recesses.

17. The method according to claim 11, wherein the semiconductor wafer is singulated through the recesses, and the layer stack in the first regions presets in each case the first reflectivity and the layer stack in the second regions presets in each case the second reflectivity.

Description

DETAILED DESCRIPTION

[0054] In the following, the semiconductor chip described herein, the semiconductor device, and the method for producing the semiconductor chip described herein are explained in more detail with reference to exemplary embodiments and the accompanying Figures.

[0055] FIG. 1 shows a top view of a semiconductor chip 1 according to an exemplary embodiment with a semiconductor body 2 comprising a ridge 21. Furthermore, a first contact layer 15 and a second contact layer 16 are arranged on the semiconductor body 2. Between the contact layers 15 and 16, a recess 11 is arranged in which a dielectric layer 17 is arranged. The semiconductor body 2 extends from a first end face 9 to a second end face 10. An anti-reflective layer 13 is arranged on the first end face 9 and a highly reflective mirror layer 12 is arranged on the second end face 10. In addition, a resonator 6 extends between a first end region 7 and a second end region 8.

[0056] Constant current is supplied to the semiconductor body 2 through the first contact layer 15, while radiation generated by an active region 3 is modulated through the second contact layer 16.

[0057] FIG. 2 shows a top view of a semiconductor chip 1 according to a further exemplary embodiment in which the resonator 6 extends between a first end face 9 and a second end face 10. For example, the semiconductor chip 1 can be turned on and off by operating the second contact layer 16. Higher switching speeds can thus advantageously be achieved.

[0058] FIG. 3 shows a top view of a semiconductor device 22 according to an exemplary embodiment with four semiconductor chips 1 according to FIG. 2. At least two of the recesses 11 can have different reflectivities. Thus, differences caused by different thermal coupling of the semiconductor chips 1 can be compensated. The recesses 11 of the inner semiconductor chips 1 can have a higher reflectivity than the recesses 11 of the outer semiconductor chips 1, since these are cooled more poorly and thus have a higher laser threshold.

[0059] FIG. 4 shows a top view of a semiconductor device 22 according to an exemplary embodiment with four semiconductor chips 1 which, in contrast to FIG. 1, exclusively have a first contact layer 16.

[0060] FIGS. 5 and 6 each show a top view of a semiconductor device 22 according to an exemplary embodiment, wherein the resonators 6 of the semiconductor chips 1 each have different lengths.

[0061] FIGS. 7, 8 and 9 and FIGS. 10 and 11 show method stages for producing a semiconductor device 22. Initially, first recesses 11 are generated at wafer level (FIG. 7). A dielectric layer 17 is introduced in each of the recesses 11. Subsequently, the semiconductor chips 1 are singulated at wafer level to form semiconductor devices 22.

[0062] FIGS. 12, 13, 14, 15, 16, 17, 18, 19 and 20 each show a sectional view of a recess 11 in which a dielectric layer 17 is arranged. FIGS. 21, 22, 23, 24, 25, 26 and 27 each show a sectional view of a recess 11 in which a dielectric layer 17 and a further dielectric layer 18 are arranged.

[0063] FIGS. 28 and 29 each show a sectional view of two recesses 11 in a semiconductor chip 1 in which a dielectric layer 17 is arranged.

[0064] FIG. 30 shows a sectional view of a recess 11 in which a waveguide structure 19 is arranged.

[0065] FIGS. 31, 32 and 33 show exemplary diagrams of a reflectivity R for radiation at a recess 11 with a dielectric layer 17, for example SiO.sub.2, as shown in FIGS. 12 and 13. The width d1 is the width of a dielectric layer 17 arranged on a side surface of the recess 20. In FIG. 31, the width of the recess is d=d1+d2+d1=500 nm, a refractive index of the semiconductor body is n.sub.HT=2.4, and a refractive index of the dielectric layer is n.sub.M=1.5. In contrast, in FIG. 31, the width of the recess is d=d1+d2+d1 =560 nm, and in FIG. 33, d=d1+d2+d1=620 nm. Preferably, a width d1 is selected at which there is a local maximum or minimum reflectivity, so that small changes of the width do not have a significant effect on the reflectivity.

[0066] FIGS. 34, 35, 36 and 37 each show exemplary diagrams of a reflectivity R for radiation at a recess 11 with a dielectric layer 17 as a function of a wavelength λ of the radiation. Here, n.sub.HT, is in each case approximately 2.47. In FIG. 34, the recess has a width d=570 nm, wherein a width d1 and d3 of a dielectric layer 17, e.g. SiO.sub.2 with n.sub.M=1.47, each has 41 nm. In FIG. 35, the recess has a width d=600 nm, wherein a width d1 of a dielectric layer 17, e.g. SiO.sub.2 with n.sub.M=1.47, has 9 nm and a width d3 of further dielectric layer 18, e.g. SiN with n.sub.M=2.08, has 22 nm. In contrast to FIG. 35, the recess has a width d=630 nm, wherein a width dl of a dielectric layer 17, e.g. SiO.sub.2 with n.sub.M=1.47, has 165 nm and a width d3 of a further dielectric layer 18, e.g. SiN with n.sub.M=2.08, has 51 nm. In FIG. 37, the recess has a width d=630 nm, wherein a width d1 and d3 of a dielectric layer 17, e.g. SiN with n.sub.M=2.08, each has 41 nm.

[0067] FIG. 38 shows an exemplary diagram in which a quotient of n.sub.M and n.sub.HL is plotted as a function of the reflectivity R. Here, the following applies n.sub.M/n.sub.HT=1-0.08397*sqrt(R). This relation applies to a completely filled recess 11 as shown in FIGS. 19 and 20.

[0068] FIGS. 39 and 40 show method stages for producing a semiconductor device 22. At wafer level, first recesses 11 are initially generated in a semiconductor wafer 28. A layer stack 23 is introduced into each of the recesses 11 according to the method stages of FIGS. 41, 42, 43 and 44. Subsequently, the semiconductor wafer 28 is singulated at wafer level to form semiconductor devices 22.

[0069] For example, the semiconductor wafer 28 is singulated at wafer level into semiconductor devices 22 by sawing, laser cutting, stealth dicing, or breaking.

[0070] Referring to FIG. 41, a layer stack 23 is generated in the recess 11. In this embodiment, the layer stack 23 comprises six dielectric layers stacked on top of one another. On a side surface of the recess 20, the dielectric layers are stacked on top of each other in lateral directions, and on a bottom surface of the recess, the dielectric layers are stacked on top of each other in vertical directions.

[0071] For example, the dielectric layers of the layer stack 23 are successively deposited on the semiconductor body 2 by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. Alternatively, the dielectric layers of the layer stack 23 can be deposited by a sputtering process or a vapor deposition process. For example, the dielectric layers can be deposited from a combination of these processes.

[0072] In this embodiment, the fourth dielectric layer of the six dielectric layers is formed as an etch stop layer 24. For example, the etch stop layer 24 comprises tantalum oxide.

[0073] Referring to FIG. 42, a mask layer 25 is applied to the layer stack 23 to cover a first region 26 of the layer stack 23 in the recess 11. A second region 27 directly adjacent thereto is free of the mask layer 25. The mask layer 25 is, for example, a photoresist or an etch-resistant protective layer.

[0074] Subsequently, the dielectric layers of the layer stack 23 in the second region 27 are removed up to the etch stop layer 24 by means of an etching process.

[0075] According to FIG. 43, the mask layer 25 is subsequently removed. In the first region 26, the dielectric layers of the layer stack 23 are not removed by using the mask layer 25.

[0076] The dielectric layers in the first region 26 are, for example, highly reflective for radiation generated in the active region. The dielectric layers in the second region 27 are, for example, anti-reflective for radiation generated in the active region.

[0077] According to FIG. 44, the semiconductor chips 1 are singulated to form semiconductor devices 22. The singulation is performed by singulating the semiconductor chips 1 in the recess 11, where the first region 26 and the second region 27 are adjacent to one another.

[0078] Advantageously, a plurality of semiconductor devices 22 are thus produced, each of which has the dielectric layers at a first end region 7, which are formed highly reflective, and the dielectric layers at a second end region 8, which are formed anti-reflective. This is that a resonator can be produced advantageously in a particularly simple and precise.

[0079] The invention is not limited to the exemplary embodiments by the description based on the exemplary embodiments.