COPPER/CERAMIC BONDED BODY AND INSULATED CIRCUIT SUBSTRATE

Abstract

A copper/ceramic bonded body of the present invention is formed by bonding a copper member, which is formed of copper or a copper alloy, and a ceramic member, in which a ratio D1/D0 is 0.60 or less, D0 being an average crystal grain size of the entire copper member, D1 being an average crystal grain size of the copper member at a position 50 μm from a bonding surface with the ceramic member, D0 and D1 being obtained by observing a cross-section of the copper member along a laminating direction.

Claims

1. A copper/ceramic bonded body formed by bonding a copper member, which is formed of copper or a copper alloy, and a ceramic member, wherein a ratio D1/D0 is 0.60 or less, D0 being an average crystal grain size of the entire copper member, D1 being an average crystal grain size of the copper member at a position 50 μm from a bonding surface with the ceramic member, D0 and D1 being obtained by observing a cross-section of the copper member along a laminating direction.

2. The copper/ceramic bonded body according to claim 1, wherein Mg is diffused in a region in the copper member, the region being at least 50 μm from the bonding surface with the ceramic member in the laminating direction, and Mg concentration decreases with increasing a distance from the bonding surface.

3. An insulated circuit substrate formed by bonding a copper sheet formed of copper or a copper alloy to a surface of a ceramic substrate, wherein a ratio D1/D0 is 0.60 or less, D0 being an average crystal grain size of the entire copper sheet, D1 being an average crystal grain size of the copper sheet at a position 50 μm from a bonding surface with the ceramic substrate, D0 and D1 being obtained by observing a cross-section of the copper sheet along a laminating direction.

4. The insulated circuit substrate according to claim 3, wherein Mg is diffused in a region in the copper sheet, the region being at least 50 μm from the bonding surface with the ceramic substrate in the laminating direction, and Mg concentration decreases with increasing a distance from the bonding surface.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1 is a schematic illustration of a power module using an insulated circuit substrate of an embodiment of the present invention.

[0025] FIG. 2 is a schematic diagram of the bonded interface between the circuit layer (copper member) and metal layer (copper member) and the ceramic substrate (ceramic member) of the insulated circuit substrate of an embodiment of the present invention.

[0026] FIG. 3 is a flow diagram showing a method for manufacturing an insulated circuit substrate of an embodiment of the present invention.

[0027] FIG. 4 is an illustration showing the method for manufacturing an insulated circuit substrate of an embodiment of the present invention.

[0028] FIG. 5 is a diagram showing observation results of the crystal grain size of a copper sheet in an Example.

DESCRIPTION OF EMBODIMENTS

[0029] A description will be given below of embodiments of the present invention with reference to the accompanying drawings.

[0030] A description will be given of embodiments of the present invention with reference to FIG. 1 to FIG. 4.

[0031] The copper/ceramic bonded body according to the present embodiment is an insulated circuit substrate 10 formed by bonding a ceramic substrate 11, which is a ceramic member, with a copper sheet 22 (a circuit layer 12) and a copper sheet 23 (a metal layer 13), which are copper members.

[0032] FIG. 1 shows the insulated circuit substrate 10 of an embodiment of the present invention and a power module 1 using this insulated circuit substrate 10.

[0033] The power module 1 is provided with the insulated circuit substrate 10, a semiconductor element 3 bonded with one side of the insulated circuit substrate 10 (the upper side in FIG. 1) via a first solder layer 2, and a heat sink 51 bonded with the other side of the insulated circuit substrate 10 (the lower side in FIG. 1) via a second solder layer 8.

[0034] The insulated circuit substrate 10 is provided with the ceramic substrate 11, the circuit layer 12 arranged on one surface (the upper surface in FIG. 1) of the ceramic substrate 11, and the metal layer 13 arranged on the other surface (the lower surface in FIG. 1) of the ceramic substrate 11.

[0035] The ceramic substrate 11 prevents electrical connection between circuit layer 12 and metal layer 13 and is formed of AlN (aluminum nitride), Si.sub.3N.sub.4 (silicon nitride), Al.sub.2O.sub.3 (alumina), or the like with excellent insulation properties. In particular, the ceramic substrate 11 is preferably formed of Si.sub.3N.sub.4 (silicon nitride), which has excellent strength. Here, the thickness of the ceramic substrate 11 is preferably in a range of 0.2 mm or more and 1.5 mm or less and, in the present embodiment, may be set to 0.32 mm, for example.

[0036] As shown in FIG. 4, the circuit layer 12 is provided by bonding the copper sheet 22 formed of copper or a copper alloy with one surface of the ceramic substrate 11. In the present embodiment, a rolled sheet of oxygen-free copper is used as the copper sheet 22 forming the circuit layer 12. A circuit pattern is provided on this circuit layer 12 and one surface thereof (the upper surface in FIG. 1) is the mounting surface on which the semiconductor element 3 is mounted. Here, the thickness of the circuit layer 12 is preferably in a range of 0.1 mm or more and 2.0 mm or less and, in the present embodiment, for example, may be set to 0.6 mm.

[0037] As shown in FIG. 4, the metal layer 13 is formed by bonding the copper sheet 23 formed of copper or a copper alloy with the other surface of the ceramic substrate 11. In the present embodiment, a rolled sheet of oxygen-free copper is used as the copper sheet 23 forming the metal layer 13. Here, the thickness of the metal layer 13 is preferably in a range of 0.1 mm or more and 2.0 mm or less and, in the present embodiment, for example, may be set to 0.6 mm.

[0038] The heat sink 51 is for cooling the insulated circuit substrate 10 described above and, in the present embodiment, is a heat-dissipating sheet formed of a material with favorable thermal conductivity. In the present embodiment, the heat sink 51 is formed of copper or a copper alloy with excellent thermal conductivity. The heat sink 51 and the metal layer 13 of the insulated circuit substrate 10 are bonded via the second solder layer 8.

[0039] Here, the ceramic substrate 11 and the circuit layer 12 (copper sheet 22) as well as the ceramic substrate 11 and the metal layer 13 (copper sheet 23) are bonded via a Mg—Ti-based bonding material 25 as shown in FIG. 4.

[0040] At the bonded interface between the ceramic substrate 11 and the circuit layer 12 (the copper sheet 22) and the bonded interface between the ceramic substrate 11 and the metal layer 13 (the copper sheet 23), a TiN layer 31 is provided as shown in FIG. 2. This TiN layer 31 is created by a reaction between the Ti included in the Mg—Ti-based bonding material 25 and the nitrogen (N) included in the ceramic substrate 11.

[0041] In the present embodiment, when a cross-sectional surface of the circuit layer 12 (the copper sheet 22) and the metal layer 13 (the copper sheet 23) in a laminating direction is observed, a ratio D1/D0 of an average crystal grain size D1 at a position of 50 μm in the laminating direction from the bonding surface with the ceramic substrate 11 to an average crystal grain size D0 of the entirety of the circuit layer 12 (the copper sheet 22) and the metal layer 13 (the copper sheet 23) is 0.60 or less and preferably in a range of 0.25 or more and 0.56 or less.

[0042] That is, the crystal grain size of the circuit layer 12 (the copper sheet 22) and metal layer 13 (the copper sheet 23) is locally smaller at a position of 50 μm in the laminating direction from the bonding surface of ceramic substrate 11.

[0043] In the present embodiment, the bonding surface of the circuit layer 12 with the ceramic substrate 11 is the uppermost surface of the circuit layer 12 side of the ceramic substrate 11 in the laminating direction.

[0044] In addition, in the present embodiment, the bonding surface of the metal layer 13 with the ceramic substrate 11 is the uppermost surface of the metal layer 13 side of the ceramic substrate 11 in the laminating direction.

[0045] In the region from the bonding surface with ceramic substrate 11 to 50 μm in the laminating direction, the TiN layer 31 is interposed between the ceramic substrate 11 and the circuit layer 12 and between the ceramic substrate 11 and the metal layer 13, but the TiN layer 31 is sufficiently thin compared to the circuit layer 12 and the metal layer 13.

[0046] The circuit layer 12 and the metal layer 13 are bonded with the ceramic substrate 11 via the TiN layer 31.

[0047] The average crystal grain sizes D0 and D1 in the present embodiment are the average crystal grain sizes of the crystal grains including twin crystals.

[0048] Here, in the present embodiment, preferably, Mg is diffused in a region of the circuit layer 12 (the copper sheet 22) and the metal layer 13 (the copper sheet 23) from the bonding surface of the ceramic substrate 11 to at least 50 μm in the laminating direction and the Mg concentration decreases with increasing a distance from the bonding surface. That is, preferably, the Mg in the Mg—Ti-based bonding material 25 is sufficiently diffused to the circuit layer 12 (the copper sheet 22) side and the metal layer 13 (the copper sheet 23) side. The concentration of Mg in this region is preferably 0.1 wt % or more and 10 wt % or less.

[0049] Next, a description will be given of the method for manufacturing the insulated circuit substrate 10 of the present embodiment described above and the power module 1 with reference to FIG. 3 and FIG. 4.

[0050] (Laminating Step S01)

[0051] As shown in FIG. 4, the Mg—Ti-based bonding material 25 is arranged between the copper sheet 22 which is the circuit layer 12 and the ceramic substrate 11 and between the copper sheet 23 which is the metal layer 13 and the ceramic substrate 11 and the above are laminated. In the present embodiment, a paste material including titanium hydride powder and magnesium hydride powder is used as the Mg—Ti-based bonding material 25. Since titanium and magnesium are active metals, the use of titanium hydride powder and magnesium hydride powder makes it possible to suppress oxidation and the like of titanium and magnesium.

[0052] Here, the Mg—Ti-based bonding material 25 to be arranged preferably has a Ti amount in a range of 0.1 μm or more and 5 μm or less in terms of thickness and an Mg amount in a range of 1.5 μm or more and 10 μm or less.

[0053] (Holding Step S02)

[0054] Next, the copper sheet 22, the ceramic substrate 11, and the copper sheet 23, which are laminated, are pressed in the laminating direction, charged into a heating furnace, heated, and held at a predetermined holding temperature for a set time.

[0055] Here, in the present embodiment, the pressing load in the holding step S02 is preferably in a range of 0.049 MPa or more and 3.4 MPa or less. In addition, the inside of the heating furnace is preferably an inert gas atmosphere such as Ar.

[0056] The holding temperature is preferably in a range of 300° C. or higher and 730° C. or lower and the holding time at the holding temperature is preferably in a range of 10 minutes or more and 120 minutes or less.

[0057] By this holding step S02, the Mg of the Mg—Ti-based bonding material 25 is sufficiently diffused toward the copper sheet 22 that will become the circuit layer 12 and the copper sheet 23 that will become the metal layer 13.

[0058] (Bonding Step S03)

[0059] Next, after the holding step S02, the copper sheet 22, the ceramic substrate 11, and the copper sheet 23, which are laminated, are further heated in a state of being pressed in the laminating direction to bond the copper sheet 22, the ceramic substrate 11, and the copper sheet 23. In this bonding step S03, it is preferable to create a vacuum atmosphere in the heating furnace.

[0060] Here, the pressing load in the bonding step S03 is set in a range of 0.049 MPa or more and 3.4 MPa or less.

[0061] In addition, the heating temperature in the bonding step S03 is preferably in a range of 650° C. or higher and 1050° C. or lower.

[0062] Furthermore, the holding time at the heating temperature is preferably in a range of 10 minutes or more and 240 minutes or less.

[0063] In addition, the vacuum level in the bonding step S03 is preferably in a range of 1×10.sup.−6 Pa or more and 1×10.sup.−2 Pa or less.

[0064] As described above, the insulated circuit substrate 10 of the present embodiment is manufactured by the laminating step S01, the holding step S02, and the bonding step S03.

[0065] (Heat Sink Bonding Step S04)

[0066] Next, the heat sink 51 is bonded with the other surface side (the opposite side to the ceramic substrate 11) of the metal layer 13 of the insulated circuit substrate 10. In the present embodiment, the insulated circuit substrate 10 and the heat sink 51 are laminated via the solder material and charged into a heating furnace and the insulated circuit substrate 10 and the heat sink 51 are solder-bonded via the second solder layer 8.

[0067] (Semiconductor Element-Bonding Step S05)

[0068] Next, the semiconductor element 3 is bonded with one surface side (the opposite side to the ceramic substrate 11) of the circuit layer 12 of the insulated circuit substrate 10 by soldering.

[0069] The power module 1 shown in FIG. 1 is produced by the above steps.

[0070] According to the insulated circuit substrate 10 (the copper/ceramic bonded body) of the present embodiment formed as described above, when a cross-sectional surface of the circuit layer 12 and the metal layer 13 in a laminating direction is observed, a ratio D1/D0 of an average crystal grain size D1 at a position of 50 μm in the laminating direction from the bonding surface with the ceramic substrate 11 to an average crystal grain size D0 of the entirety of the circuit layer 12 and the metal layer 13 is 0.6 or less. Therefore, it is possible to suppress the crystal grain size in the vicinity of the bonded interface to be comparatively small, to suppress deformation of the circuit layer 12 and metal layer 13 in the region in the vicinity of the bonded interface when ultrasonic waves are applied thereto, and to suppress destruction of the TiN layer 31. In addition, the crystal grain size is not significantly different in the vicinity of the bonded interface between the entire circuit layer 12 and the metal layer 13 and it is possible to suppress the hardening of the entire circuit layer 12 and metal layer 13.

[0071] Furthermore, in the present embodiment, Mg is sufficiently diffused in a region of the circuit layer 12 and metal layer 13 from the bonding surface of the ceramic substrate 11 to at least 50 μm in the laminating direction and it is possible to make the crystal grain size in the vicinity of the bonded interface of the circuit layer 12 and metal layer 13 comparatively small.

[0072] Although the embodiments of the present invention were described above, the present invention is not limited thereto and appropriate modification is possible in a range not departing from the technical concept of the invention.

[0073] For example, the copper sheet forming the circuit layer or metal layer was described as a rolled sheet of oxygen-free copper, but is not limited thereto and may be formed of other copper or copper alloys.

[0074] In addition, it is also possible to carry out the manufacturing using a foil material as the bonding material instead of a paste material.

[0075] Furthermore, a description was given of a heat sink with a heat-dissipating sheet as an example; however, the heat sink is not limited thereto and there is no particular limitation on the structure of the heat sink. For example, the heat sink may have a passage through which a refrigerant circulates or may be provided with cooling fins. In addition, it is also possible to use a composite material (for example, AlSiC or the like) including aluminum or aluminum alloys as a heat sink.

[0076] In addition, a buffer layer formed of aluminum or a composite material (for example, AlSiC or the like) including aluminum alloys or aluminum may be provided between the top plate portion of the heat sink or the heat-dissipating sheet, and the metal layer.

[0077] In addition, in the present embodiment, a description was given of forming a power module by mounting a power semiconductor element on the circuit layer of the insulated circuit substrate; however, the power module is not limited thereto. For example, an LED module may be formed by mounting an LED element on the insulated circuit substrate, or a thermoelectric module may also be formed by mounting a thermoelectric element on the circuit layer of an insulated circuit substrate.

EXAMPLES

[0078] A description will be given of confirmatory experiments performed to confirm the effectiveness of the present invention.

[0079] A copper sheet (37 mm×37 mm, thickness of 0.8 mm) was bonded with both surfaces of a ceramic substrate (40 mm×40 mm, thickness of 0.32 mm) shown in Table 1 using the bonding material shown in Table 1 and an insulated circuit substrate (copper/ceramic bonded body) on which a circuit layer and metal layer were formed was obtained. The holding step and bonding step were carried out under the conditions shown in Table 1. In addition, the vacuum level of the vacuum furnace during bonding was 5×10.sup.−3 Pa.

[0080] The insulated circuit substrates (copper/ceramic bonded bodies) obtained in this manner were observed in a cross-sectional surface in the laminating direction and the crystal grain sizes of the circuit layer and metal layer were measured. In addition, ultrasonic waves were applied thereto and peeling at the bonded interface and cracking of the ceramic substrate were evaluated.

[0081] (Crystal Grain Size)

[0082] In the cross-sectional surface in the laminating direction of the insulated circuit substrate (circuit layer and metal layer), an average crystal grain size D0 of the entire circuit layer and the entire metal layer was measured using an EBSD measuring device. FIG. 5 shows the observation results of the crystal structure.

[0083] In addition, the average crystal grain size D1 at a position of 50 μm from the uppermost surface of the ceramic substrate to the circuit layer side and the metal layer side was calculated using the equation below by drawing a reference line parallel to the bonded interface at a position separated by 50 μm in the laminating direction from the bonded interface of the circuit layer and the metal layer with the ceramic substrate and using the number of particles N touching the reference line and the length L of the reference line. The length L of the reference line was as shown in Table 2.

D1=1.5×L/N

[0084] This measurement was performed for each of the circuit layer and the metal layer and the average values thereof are shown in Table 2.

[0085] (Peeling of Bonded Interface and Cracking of Ceramic Substrate During Ultrasonic Wave Application)

[0086] Terminal materials were ultrasonically welded under conditions of a bonding area of 3×3 mm.sup.2, a bonding time of approximately 0.6 seconds, and a sinking amount of 0.45 mm and the presence or absence of peeling at the copper/ceramic substrate bonded interface and cracking in the ceramic substrate was confirmed by ultrasonic flaw detection (SAT).

[0087] This confirmation was performed for each of the circuit layer and the metal layer and a case in which peeling of the bonded interface and cracking of the ceramic substrate were confirmed in either was set as “Yes” and a case in which neither was confirmed was set as “No” and listed in Table 2.

[0088] (Mg Diffusion Distance)

[0089] For the insulated circuit substrate (copper/ceramic bonded body), line analysis of Mg was performed using EPMA for a cross-sectional surface in the laminating direction from the bonding surface of the circuit layer (metal layer) with the ceramic substrate to the surface side of the circuit layer (metal layer). The distance from the bonding surface of the circuit layer (metal layer) with the ceramic substrate to the location where the concentration of Mg was 0.1 wt % was set as the Mg diffusion distance. This measurement was performed at five locations in each of the circuit layer and metal layer and the average values are listed in Table 2.

TABLE-US-00001 TABLE 1 Bonding material (converted thickness) Ceramic Holding step Bonding step Mg Ti substrate Temperature Time Temperature Time (μm) (μm) Shape Substance (° C.) (min) (° C.) (min) Invention 3.0 0.1 Paste Si.sub.3N.sub.4 600 30 750 100 example 1 Invention 3.0 0.0 Foil AlN 600 30 850 30 example 2 Invention 10.0 0.0 Foil AlN 600 30 850 30 example 3 Invention 6.0 0.0 Paste AlN 600 30 850 30 example 4 Comparative Ag: 5.0 1.0 Paste Si.sub.3N.sub.4 600 30 850 30 example

TABLE-US-00002 TABLE 2 Ultrasonic wave Average crystal grain size (including twin crystals) application test Reference Interface Mg Presence or Presence or Particle line vicinity Entirety diffusion absence of absence of number* N length L D1 D0 D1/ distance ceramic bonded interface (particles) (μm) (μm) (μm) D0 (μm) cracking cracking Invention 21 1200 86 341 0.25 50 No No example 1 Invention 66 4000 91 223 0.41 86 No No example 2 Invention 62 4000 97 172 0.56 98 No No example 3 Invention 82 4000 73 271 0.27 92 No No example 4 Comparative 37 4000 162 250 0.65 58 No Yes example *Number of particles touching reference line set at position of 50 μm from interface to copper sheet side

[0090] In the Comparative Example, the ratio D1/D0 of the average crystal grain size D1 at a position of 50 μm in the laminating direction from the bonding surface of the circuit layer and the metal layer with the ceramic substrate to the average crystal grain size D0 of the entire circuit layer and metal layer was 0.65 and cracking was generated at the bonded interface when ultrasonic waves were applied thereto. This is assumed to be because Ag—Ti paste was used as the bonding material, the crystal grains in the vicinity of the bonded interface were not sufficiently refined, and it was not possible to suppress deformation in the region in the vicinity of the bonded interface in the circuit layer and metal layer when ultrasonic waves were applied thereto.

[0091] In Invention Examples 1 to 4, the ratio D1/D0 of the average crystal grain size D1 at a position of 50 μm in the laminating direction from the bonding surface of the ceramic substrate with the circuit layer and the metal layer to the average crystal grain size D0 of the entire circuit layer and metal layer was 0.60 or less and it was possible to suppress the generation of cracking at the bonded interface when ultrasonic waves were applied thereto. This is assumed to be because material containing Mg was used as the bonding material, Mg was diffused to the circuit layer side and metal layer side by further carrying out the holding step and bonding step shown in Table 1 such that the crystal grains in the vicinity of the bonded interface were sufficiently refined and it was possible to suppress deformation in the region in the vicinity of the bonded interface in the circuit layer and metal layer when ultrasonic waves were applied thereto.

[0092] From the above, it was confirmed that, according to the Invention Examples, it is possible to provide a copper/ceramic bonded body in which a copper member, which is formed of copper or a copper alloy, and a ceramic member are reliably bonded and the bonding reliability is excellent even when ultrasonic waves are applied thereto, as well as an insulated circuit substrate.

REFERENCE SIGNS LIST

[0093] 10: Insulated circuit substrate [0094] 11: Ceramic substrate [0095] 12: Circuit layer [0096] 13: Metal layer [0097] 31: TiN layer