VOLTAGE REGULATION USING A DELTA-SIGMA MODULATOR, DEVICE AND METHOD

Abstract

It is described a voltage regulator device (100), comprising: i) a power device (150), configured to receive an input signal (151) and to produce a corresponding output signal (152); ii) a comparator device (110), coupled via a feedback path (140) to the power device (150), and configured to receive the output signal (152) as a feedback signal (141), and to produce a compared feedback signal (112); and iii) a digital modulation device (120), arranged between the comparator device (110) and the power device (150), and configured to digitally modulate the compared feedback signal (112), and to provide the digitally modulated signal (121) to the power device (150), wherein the digital modulation device (120) comprises: iiia) a delta-sigma (122), iiib) a quantizer (124), and iiic) a feedforward path (128), configured to feedforward the compared feedback signal (112) beyond the delta-sigma (122).

Claims

1. A voltage regulator device, comprising: a power device, configured to receive an input signal and to produce a corresponding output signal; a comparator device, coupled via a feedback path to the power device, and configured to receive the output signal as a feedback signal, and produce a compared feedback signal; and a digital modulation device, arranged between the comparator device and the power device, and configured to digitally modulate the compared feedback signal, and provide the digitally modulated signal to the power device, wherein the digital modulation device comprises: a delta-sigma, a quantizer, and a feedforward path, configured to feedforward the compared feedback signal beyond the delta-sigma.

2. The voltage regulator device according to claim 1, wherein the digital modulation device comprises a pulse density modulation, PDM, device.

3. The voltage regulator device according to claim 1, wherein the quantizer is a multi-bit quantizer.

4. The voltage regulator device according to claim 1, wherein the digital modulation device further comprises: a digital modulation feedback path, configured to feed-back the output of the quantizer to the delta-sigma.

5. The voltage regulator device according to claim 1, wherein the feedforward path is configured to feedforward the compared feedback signal to a coupling between the delta-sigma and the quantizer.

6. The voltage regulator device according to claim 1, further comprising at least one of the following features: a driver device arranged between the digital modulation device and the power device; a driver device and a level shifter device arranged between the digital modulation device and the power device; a level shifter between the comparator device and the digital modulation device.

7. The voltage regulator device according to claim 6, wherein the feedforward path is configured to feedforward the compared feedback signal to the driver device or to the driver device and the level shifter device.

8. The voltage regulator device according to claim 1, wherein the comparator device is part of an analog domain, and wherein the digital modulation device is part of a digital domain.

9. The voltage regulator device according to claim 1, wherein the voltage regulator device is configured as a low dropout, LDO, device.

10. The voltage regulator device according to claim 1, wherein the comparator device is configured to compare the feedback signal with a reference voltage to produce the compared feedback signal.

11. The voltage regulator device according to claim 1, further comprising: a clock device, configured to provide a clock signal to the digital modulation device.

12. The voltage regulator device according to claim 11, wherein the clock device is further configured to provide a further clock signal to the comparator device.

13. The voltage regulator device according to claim 1, wherein the power device comprises a plurality of power units configured as power switches.

14. A method of operating a voltage regulator device, comprising: receiving an input signal and producing a corresponding output signal by a power device; receiving the output signal as a feedback signal and producing a compared feedback signal by a comparator device; digitally modulating the compared feedback signal by a digital modulation device that comprises a delta-sigma and a quantizer to obtain a digitally modulated signal; providing the digitally modulated signal to the power device; wherein the method further comprises: feeding forward the compared feedback signal via a feedforward path beyond the delta-sigma.

15. (canceled)

16. The method of claim 14, further comprising feeding back an output signal of the quantizer to the delta-sigma of the digital modulation device by way of a digital modulation feedback path to obtain the digitally modulated signal.

17. The method of claim 14, wherein feeding forward the compared feedback signal via the feedforward path further comprises feeding forward the compared feedback signal to a coupling between the delta-sigma and the quantizer.

18. The method of claim 14, wherein feeding forward the compared feedback signal via the feedforward path further comprises feeding forward the compared feedback signal to a driver device.

19. The method of claim 14, further comprising comparing the feedback signal with a reference voltage by way of the comparator device to produce the compared feedback signal.

20. The method of claim 14, further comprising providing a clock signal to the digital modulation device by way of a clock device.

21. The method of claim 14, wherein the voltage regulator device) is configured as a low dropout, LDO, device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG. 1 illustrates a voltage regulation device according to an exemplary embodiment of the present disclosure.

[0039] FIG. 2 illustrates a voltage regulation device according to a further exemplary embodiment of the present disclosure.

[0040] FIG. 3 illustrates a digital modulation device according to a further exemplary embodiment of the present disclosure.

[0041] FIGS. 4 to 7 illustrate respectively a voltage regulation device according to further exemplary embodiments of the present disclosure.

[0042] FIG. 8 illustrates alternative representations of the integrator for transfer function computation in Laplace domain or in Z-domain.

[0043] FIG. 9 illustrates in detail the multi-bit quantizer according to an exemplary embodiment of the present disclosure.

[0044] FIG. 10 illustrates in detail the power device according to an exemplary embodiment of the present disclosure.

[0045] FIG. 11 illustrates in a diagram a simulation of the output signal in comparison to a load current according to an exemplary embodiment of the present disclosure.

[0046] FIG. 12 illustrates a digital modulation device, used to perform calculations regarding the transfer function, according to an exemplary embodiment of the present disclosure.

[0047] FIGS. 13 to 16 illustrate conventional LDOs (see description above).

[0048] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.

DETAILED DESCRIPTION OF THE DRAWINGS

[0049] Before referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the present disclosure have been developed.

[0050] According to exemplary embodiments of the present disclosure, there is described a novel control method for an LDO that combines a comparator with a PDM controller and a power stage. The PDM controller is achieved through a digital delta-sigma modulator with a multi-bit quantizer and a feedforward path. This approach reduces complexity in terms of design and stability analysis, saves chip area (as power devices operate only in linear region), improves scalability and portability for digital technology node.

[0051] According to exemplary embodiments of the present disclosure, the control method can comprise the following features:

i) decrease design and stability analysis complexity.
ii) improve scalability and portability for digital technology node.
iii) PDM controller is achieved through a delta-sigma and a multibit quantizer.
iv) use a feedforward path in the delta-sigma modulation to reduce the quantization noise and consequently the ripple and also to improve stability.
v) save area by using the power stage devices in linear region (as switches) and not in saturation as for analog or class D LDO.
vi) do not have stability issue like internal pole and zero variations due to large current load variation.
vii) has a reduced number of poles and zeros compared to an analog solution.
viii) does not require error amplifier with stability, buffer, pole tracking or power device in saturation.
ix) can operate at lower voltage compared to analog regulator, as only a comparator and power switches are required in the analog part.
x) the control part is fully digital and can be synthetized.

[0052] FIG. 1 illustrates a voltage regulation device 100 according to an exemplary embodiment of the present disclosure. The device 100 comprises a power device 150, wherein the power device 150 is configured to receive an input signal 151 (voltage V.sub.IN) and to produce a corresponding output signal 152 (voltage V.sub.OUT). A feedback path 140 is coupled to the power device 150 in order to regulate the output signal 152. The feedback path 140 guides the output signal 152 as a feedback signal 141 back to a comparator device 110, e.g. an error amplifier. The feedback path 140 can comprise a resistor ladder 142. The comparator 110 compares the (analog) feedback signal 141 to a reference voltage 115 and produces a corresponding compared feedback signal 112 as an output. The comparator output 112 will define, if the output voltage 152 is higher or lower than the target voltage. Said compared feedback signal 112 is then further provided to a digital modulation device 120 that is arranged between the comparator device 110 and the power device 150, thereby closing the feedback/regulation loop. The digital modulation device 120 is implemented as a pulse density modulation (PDM) device and configured to digitally modulate the compared feedback signal 112 and to provide the digitally modulated signal 121 back to the power device 150.

[0053] FIG. 2 illustrates a voltage regulation device 100 according to an exemplary embodiment of the present disclosure. The device 100 is very similar to the one shown in FIG. 1 but shows more details. It can be seen that the PDM device 120 is implemented as a delta-sigma modulator that comprises a delta-sigma 122 and a multi-bit quantizer 124. A clock device 160 provides a clock signal 161 to the PDM device 120 for the digital modulation. Between the PDM device 120 and the power device 150, there is coupled a driver (and optionally a level shifter) device 155. The power device 150 (which can comprise a plurality of power units) and the driver/level shifter device 155 form a power stage 156. Further, it is illustrated that the comparator device 110, the feedback path 140 (in principle also the power device 150) and the driver/level-shifter devices 155 form an analog (signal) domain, while the PDM 120 forms a digital (signal) domain. The output 152 further comprises an output capacitor 154 that can be internal or external to the device 100.

[0054] FIG. 3 illustrates the digital modulation device 120 according to an exemplary embodiment of the present disclosure in detail. The (analog) compared feedback signal 112 from the comparator device 110 is the input, while the digitally modulated signal 121 (data stream) is the output to the power device 150. The delta-sigma 122 comprises a delta domain 122a (difference) and a sigma domain 122b (integrator). There is established a feedforward path 128, configured to feedforward the compared feedback signal 112 beyond (around) the delta-sigma 122. In particular, in this example, the feedforward path 128 feeds forward the compared feedback signal 112 to the coupling point 125 (sum) between delta-sigma 122 and quantizer 124. The feedforward path 128 can comprise a gain Gc.

[0055] Further, the digital modulation device 120 comprises a feedback path 126 that is established between the output of the quantizer 124 and the coupling point 123 (difference) of the delta domain 122a, the sigma domain 122b, and the comparator output 121. The feedback path 126 can further comprise a gain Gb, which is the gain of the delta sigma feedback loop. The feedback path 126 is a digital path, and computes the digital quantizer output 121 to a digital value used as negative input of the delta sigma. It can be considered by analogy, that the feedback path functionality is similar to digital-analog converter (DAC) functionality.

[0056] The signal feedback FB corresponds in this example to the sum of the binary bits on the data stream bus <N:1>, in other words, it follows the following equation: FB=Σ.sub.n=1.sup.n=Nbn. For example, in the case of a 8-bit bus (N=8) and there would be the following bit correspondence: {b8, b7, b6, b5, b4, b3, b2, b1}=0000 1111, or FB=Σ.sub.n=1.sup.n=8bn=1+1+1+1+0+0+0+0=4.

[0057] FIG. 4 illustrates a voltage regulation device 100 according to a further exemplary embodiment of the present disclosure. FIG. 4 shows in principle the detail view of the digital modulation device 120 of FIG. 3 in the device of FIG. 2.

[0058] FIG. 5 illustrates a voltage regulation device 100 according to a further exemplary embodiment of the present disclosure. In this example, the clock device 160 is further connected to the comparator device 110 and provides the clock signal 161 thereto. In this manner, the comparator device 110 can be operated as a latch comparator.

[0059] FIG. 6 illustrates a voltage regulation device 100 according to a further exemplary embodiment of the present disclosure. In this example, which is based on the example of FIG. 5, there is a first level shifter device 155a coupled between the comparator device 110 and the digital modulation device 120, while a second driver and level shifter device 155b is coupled between the digital modulation device 120 and the power device 150. Thereby, potentially different power domains may be established in the device 100.

[0060] FIG. 7 illustrates a voltage regulation device 100 according to a further exemplary embodiment of the present disclosure. In this example, which is based on the example shown in FIG. 4, the feedforward path 128 is configured to feedforward the compared feedback signal 112 to the (second) driver and level shifter device 155b. In this case, the forward path 128 goes outside the modulator 120 to control directly the power stage 156 (and/or power device 150).

[0061] FIG. 8 illustrates alternative representations of the integrator 122b for transfer function computation in Laplace domain or in Z-domain. While in the example on the left side an integrator 122b is applied (see also the previous Figures), the example in the middle applies a Laplace transform/domain for continuous time modelisation. Further, the example on the right side applies a Z-transform/domain for discrete time modelisation.

[0062] FIG. 9 illustrates in detail the multi-bit quantizer 124 according to an exemplary embodiment of the present disclosure. The digital modulation device 120 is configured as described above, but, in this detailed Figure, it can be seen that the multi-bit quantizer 124 applies a plurality of stages in order to provide the quantizer output(s) 121.

[0063] FIG. 10 illustrates in detail the power device 150 according to an exemplary embodiment of the present disclosure. In this detailed example, the power device 150 comprises a plurality of power units 158 that are configured as power switches connected in parallel. In this example, each quantizer output 121 is connected to a specific power switch 158.

[0064] FIG. 11 illustrates in a diagram a simulation of the output signal 152 in comparison to a DC load current 153 provided to the power device 150 according to an exemplary embodiment of the present disclosure. Even though the DC load current 153 increases significantly in a linear manner, the voltage output 152 is regulated in an efficient and reliable manner by the described voltage regulator device 100.

[0065] FIG. 12 illustrates a digital modulation device 120, here a delta-sigma modulator, according to an exemplary embodiment of the present disclosure. This Figure is used as a base for the following calculations regarding the transfer function. Hereby, Ti is the period of the clock (comparable to the sampling period of the integrator). An assumption is that the power stage is considered as having a transfer function like a low pass filter.

[0066] For the following computation, we consider

[0067] a is the comparator gain

[0068] b is the delta sigma modulator feedback gain

[0069] c is the feedforward path gain

[0070] d is the regulator feedback gain

[0071] V.sub.out(s) is the output of the regulator

[0072] Ti is the period of the clock

[0073] V.sub.FB(s) is the regulator feedback

[0074] V.sub.REF(s) is the reference of the regulator

[0075] Transfer Function Calculation

x(s)=a.Math.V.sub.REF(s)

w(s)=c.Math.x(s)+[x(s)−b.Math.y(s)].Math.[1/(Ti.Math.s)]

y(s)=w(s)+N(s)

V.sub.out(s)=H.sub.LPF(S).Math.y(s)

V.sub.FB(s)=d.Math.Vout(s)

y(s)=[(c.Math.Ti.Math.s+1)/(Ti.Math.s+b)].Math.x(s)+[(Ti.Math.s)/(Ti.Math.s+b)].Math.N(s),with x(s)=a.Math.V.sub.REF(s)

[0076] the transfer function is

y(s)=a.Math.[(c.Math.Ti.Math.s+1)/(Ti.Math.s+b)].Math.V.sub.REF(s)+[(Ti.Math.s/b)/(Ti.Math.s/b+1)].Math.N(s)

[0077] 1) if N(s)=0, the open loop signal transfer function is

y(s)=a[(c.Math.Ti.Math.s+1)/(Ti.Math.s+b)].Math.V.sub.REF(s) [0078] The open loop signal transfer function is

(V.sub.FB(s)/V.sub.REF(s))=(a.Math.d.Math.c/T.sub.LPF).Math.[s+1/(c.Math.Ti)]/[(s+b/Ti).Math.(s+1/T.sub.LPF)]

[0079] From this transfer function, poles and zeros can be described as follows:

P.sub.LPF=−1/T.sub.LPF (power stage pole assumed acting as a low pass filter)

pi=−b/Ti (integrator pole)

zi=−1/(c.Math.Ti) (integrator zero)

Gain.sub.DC=a.Math.d.Math.c/T.sub.LPF (DC Gain of the regulator)

By having b=1/c in a computation, the pole and zero of the integrator (of the delta-sigma) cancel each other, thereby simplifying stability as the stability response is similar to a first order stability system. It follows in particular, that by providing the feedforward path (see c) and the feedback path (see b), the stability of the described voltage regulator device can be improved.

[0080] 2) if V.sub.REF(s)=0, the open loop noise transfer function is

y(s)=[(Ti.Math.s/b)/(Ti.Math.s/b+1)].Math.N(s)

[0081] The open loop noise transfer function is

(V.sub.FB(s)/N(s))=(d/T.sub.LPF).Math.[(s/(s+(b/Ti))].Math.[(1/(s+(1/T.sub.LPF))],

[0082] wherein [s/(s+(b/Ti))] represents a high pass filter.

REFERENCE NUMERALS

[0083] 100 Voltage regulation device [0084] 110 Comparator device [0085] 112 Compared feedback signal, comparator output [0086] 115 Reference signal/voltage [0087] 120 Digital modulation device [0088] 121 Quantizer output, data stream [0089] 122 Delta-sigma [0090] 122a Delta domain [0091] 122b Sigma domain, integrator [0092] 123 First coupling point (difference) [0093] 124 Quantizer [0094] 125 Second coupling point (sum) [0095] 126 Digital modulation feedback path [0096] 128 Feedforward path [0097] 140 Feedback path [0098] 141 Feedback signal [0099] 142 Resistor ladder or unity gain feedback path [0100] 150 Power device [0101] 151 Input signal/voltage [0102] 152 Output signal/voltage [0103] 153 DC load current [0104] 154 Output capacitor [0105] 155 Driver device [0106] 155a Level-shifter device [0107] 155b Driver and level-shifter device [0108] 156 Power stage [0109] 158 Power unit, power switch [0110] 160 Clock device [0111] 161, 161a,b Clock signal