Frequency Converter

Abstract

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

Claims

1-11. (canceled)

12. A frequency converter, comprising: a control unit, comprising: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value, and a power unit which is in data connection to the control unit and comprises: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which is in signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

13. The frequency converter as claimed in claim 12, wherein: the control unit is designed to transmit data packets with a predefined duration and/or with a predefined time interval between one another via the control unit interface, and the clock pulse generator adjustment unit is designed to adjust the power unit clock pulse depending on the predefined duration and/or the predefined time interval.

14. The frequency converter as claimed in claim 12, wherein the control unit is designed to transmit data packets periodically with a predefined cycle time via the control unit interface, and the clock pulse generator adjustment unit is designed to adjust the power unit clock pulse depending on the cycle time.

15. The frequency converter as claimed in claim 14, wherein: the clock pulse generator adjustment unit comprises a counter unit which is clocked depending on the power unit clock pulse, wherein the clock pulse generator adjustment unit is designed to define an associated counter status on reception of a respective data packet, to calculate a difference between counter statuses belonging to successive data packets and to adjust to the power unit clock pulse depending on the difference between the counter statuses.

16. The frequency converter as claimed in claim 13, wherein: the control unit is designed to perform repeated control unit processes synchronously with the transmitted data packets, and the power unit is designed to perform repeated power unit processes synchronously with the received data packets.

17. The frequency converter as claimed in claim 14, wherein: the control unit is designed to perform repeated control unit processes synchronously with the transmitted data packets, and the power unit is designed to perform repeated power unit processes synchronously with the received data packets.

18. The frequency converter as claimed in claim 15, wherein: the control unit is designed to perform repeated control unit processes synchronously with the transmitted data packets, and the power unit is designed to perform repeated power unit processes synchronously with the received data packets.

19. The frequency converter as claimed in claim 15, wherein: the clock pulse generator adjustment unit is designed to define an associated counter status as a local timestamp on reception of a respective data packet and to adapt the power unit clock pulse on the basis of a difference between the defined counter status and a predefined phase reference value in such a way that the power unit operates synchronously with the control unit with a phase relationship which is dependent on the phase reference value.

20. The frequency converter as claimed in claim 16, wherein: the clock pulse generator adjustment unit is designed to define an associated counter status as a local timestamp on reception of a respective data packet and to adapt the power unit clock pulse on the basis of a difference between the defined counter status and a predefined phase reference value in such a way that the power unit operates synchronously with the control unit with a phase relationship which is dependent on the phase reference value.

21. The frequency converter as claimed in claim 12, wherein the frequency converter is designed to implement a closed control loop, wherein a controller of the control loop for calculating the control parameter is disposed in the control unit, an adjustment device of the control loop is disposed in the power unit, and the sensor unit forms a measuring device of the control loop.

22. The frequency converter as claim in claim 21, wherein the closed control loop is a current control loop.

23. The frequency converter as claimed in claim 12, wherein: the at least one control parameter is selected from a group having the following control parameters: reference motor currents, reference motor voltages, a reference motor torque, and a reference pulse duty factor of a pulse width modulation.

24. The frequency converter as claimed in claim 23, wherein: the at least one actual value is selected from a group having the following actual values: motor currents, motor voltages, rotation angle settings of a rotor shaft, an intermediate loop voltage, and a temperature.

25. The frequency converter as claimed in claim 12, wherein: the at least one actual value is selected from a group having the following actual values: motor currents, motor voltages, rotation angle settings of a rotor shaft, an intermediate loop voltage, and a temperature.

26. The frequency converter as claimed in claim 12, wherein: the control unit interface and the power unit interface form an electrically isolating 2-line interface, wherein, in relation to the control unit, data are transmitted on a first line of the two lines and data are received on a second line of the two lines.

27. The frequency converter as claimed in claim 12, wherein: the control unit interface and the power unit interface are Universal Asynchronous Receiver Transmitter (UART) interfaces.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The invention is described in detail below with reference to the drawings, in which:

[0034] FIG. 1 shows schematically a frequency converter according to the invention, and

[0035] FIG. 2 shows schematically a variation with time of data packets which are transmitted from a control unit of the frequency converter shown in FIG. 1 to a power unit of the frequency converter shown in FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

[0036] FIG. 1 shows a frequency converter 1 with a control unit 2 which is disposed in a control unit housing (not shown in detail).

[0037] The control unit 2 has a serial 2-wire UART control unit interface 3.

[0038] The control unit 2 furthermore has a control unit clock pulse generator 4 in the form of a quartz oscillator to generate a control unit clock pulse. Data are transmitted via the control unit interface 3 in terms of their timing depending on the control unit clock pulse.

[0039] The control unit 2 furthermore has a control unit microprocessor 5 which is designed to calculate at least one control parameter depending on at least one actual value.

[0040] The frequency converter 1 furthermore has a power unit 6 which is disposed in a power unit housing and has a serial data connection to the control unit 2.

[0041] The power unit 6 has a number, for example six, of power semiconductors 7.

[0042] The power unit 6 furthermore has a power unit clock pulse generator 8 in the form of a DCO for generating an adjustable power unit clock pulse.

[0043] The power unit 6 furthermore has a serial 2-wire UART power unit interface 9 which is operatively connected to the control unit interface 3 to set up a data connection. The control unit interface 3 and the power unit interface 9 form an electrically isolating 2-line interface, wherein, in relation to the control unit 2, data are transmitted on a first line 14 of the two lines 14, 15 and data are received on a second line 15 of the two lines 14, 15. No specific sync channel is provided between the control unit 2 and the power unit 6.

[0044] The power unit 6 furthermore has a clock pulse generator adjustment unit 10 which has a signal connection to the power unit interface 6 and is designed to adjust the power unit clock pulse depending on a cycle time TZ (see FIG. 2) with which data packets 13 are transmitted from the control unit 2 to the power unit 6.

[0045] The power unit 6 furthermore has a power unit microprocessor 11 which is designed to control the power semiconductors 7 depending on the control parameter and the power unit clock pulse.

[0046] The power unit 6 furthermore has at least one sensor unit 12 which is designed to determine the at least one actual value, here, for example, a motor current.

[0047] The control unit 2 is designed to transmit the at least one control parameter via the control unit interface 3 to the power unit 6, and the power unit 6 is designed to transmit the at least one actual value via the power unit interface 9 to the control unit 2.

[0048] The clock pulse generator adjustment unit 10 has a counter unit (not shown in detail) in the form of a capture/compare unit which is clocked depending on the power unit clock pulse, wherein the clock pulse generator adjustment unit 10 or its capture/compare unit is designed to read and temporarily store an associated counter status on reception of a falling edge of a start bit of a respective data packet 13, to calculate a difference between counter statuses belonging to successive data packets, and to adjust the power unit clock pulse depending on the difference between the counter statuses. For this purpose, the difference is compared with a reference value, wherein, if the difference is greater than the reference value, the power unit clock pulse is reduced by an amount which is dependent on a difference between the reference value and the counter status difference. If the difference is less than the reference value, the power unit clock pulse is increased by an amount which is dependent on the difference between the reference value and the counter status difference.

[0049] This synchronization of the power unit clock pulse depending on the cycle time TZ and therefore depending on the control unit clock pulse can be performed once only, for example in an initialization routine. Alternatively, the synchronization can also be performed cyclically at specific time intervals, for example with each reception of a data packet 13. Again alternatively, the power unit clock pulse can first be synchronized with the control unit clock pulse, as described above, in the initialization routine. Thereafter, only one counter value of the capture/compare unit can be determined on the edge of the start bit of a respective data packet, wherein the counter value determined in this way is monitored in order to determine whether it corresponds to a reference value. If, for example, a counter overflow occurs precisely once every cycle time TZ of the data packets 13 when the power unit clock pulse and control unit clock pulse are synchronized, the determined counter value remains constant. If the counter value then changes, this indicates that the power unit clock pulse is drifting in relation to the control unit clock pulse, so that the power unit clock pulse must be synchronized by means of the clock pulse generator adjustment unit 10.

[0050] The frequency converter 1 is designed to implement a closed motor current control loop, wherein a controller of the control loop for calculating the control parameter 2 is disposed in the control unit, an adjustment device of the control loop is disposed in the power unit 6, and the sensor unit 12 forms a measuring device of the control loop.

[0051] The control unit 2 is designed to perform repeated control unit processes synchronously with the transmitted data packets 13. The power unit 6 is designed accordingly to perform repeated power unit processes synchronously with the received data packets 13.

[0052] For example, the control unit 2 can transmit the instantaneous control parameter in a respective data packet 13 to the power unit 6, and the power unit 6 can transmit the actual value(s) to the control unit 2 at a predefined time interval in relation to the start bit of a respective data packet 13.

[0053] The control unit 2 can furthermore execute a control algorithm on the basis of the received actual value(s), and the power unit 6 can set a pulse duty factor of a pulse width modulation on the basis of the control parameter. Here, the control parameter may, for example, be a reference pulse duty factor of a pulse width modulation and one of the actual values may be a motor current. Further, in particular cascaded, control loops can obviously be provided, as is customary in the case of frequency converters.

[0054] The power unit clock pulse generator 8, the serial power unit interface 9, the clock pulse generator adjustment unit 10, the power unit processor 11 and, where relevant, the sensor unit 12 or parts thereof can be integrated on a single microcontroller.