ONE INS NETWORK-BASED ANTI-FAULT ATTACK METHOD OF RANDOM INFECTION

Abstract

The present invention discloses an INS network-based anti-fault attack method of random infection, comprising the steps of sending the plain-text into an encryption processor, wherein two groups of cipher text are outputted through temporal or spatial redundancy; conducting XOR operation) on the two groups of said cipher text output to obtain the output difference; sending the said output difference into an infection function module to initiate an infection operation to obtain the infection result; conducting XOR operation on any of said groups of cipher text output to generate the final output. The present invention can realize the randomization of infection function in infection countermeasures, reduce the successful probability of fault attack and improve the safety of the circuit.

Claims

1. A method for of implementing an INS network-based anti-fault attack of random infection, comprising: Sending the plain-text into an encryption processor, wherein two groups of cipher text are outputted through temporal or spatial redundancy. conducting XOR operation on the two groups of said cipher text output to obtain the output difference; sending the said output difference into an infection function module to initiate an infection operation, so that the infection result can be obtained; obtaining said infection results, then conducting XOR decipher on any of the said groups of cipher text output to generate the final output.

2. A method as in claim 1, said method further comprising: generating normal execution results and redundant calculation results via a time redundancy mode through redundant computation; generating normal execution results and redundant calculation results via a spatial redundancy mode in the two same circuits through copying the circuit, respectively.

3. A method as in claim 1, said method further comprising: Generating the output difference by the corresponding cipher text XOR or other corresponding intermediate variables XOR that are calculated by normal execution and redundancy.

4. A method as in claim 1, said method further comprising: Sending the said output difference into an infection function module, wherein the output difference is sent into the INS network to perform hamming weight balanced process; Continuously sending the resulting output to the INS network after the hamming weight balanced process is performed; and Initiating an output confusion operation to generate the infection results.

5. A method as in claim 1, said method further comprising: Selecting the XOR value of infection results corresponding to the intermediate variable; Generating the infection results as XOR with the selected intermediate variables if the selected intermediate variable is not cipher text; Using the XOR results to replace the original intermediate variables; and Continuously performing the cryptographic algorithm to generate the final output.

6. A method as in claim 1, said method further comprising: Sending the said output difference into the INS network to perform a hamming weight balanced process, wherein said output difference is input into the low N/2 bit of INS, and wherein if the output difference is less than N/2 bits, the remaining bits shall be filled with 0, and the INS high N/2-bit input are all bits 0; and Configuring the OR enhanced switch to the OR function, and the four-state switch is configured as a random number, and other positions are normal two-state switch; and Sending said output difference back to the INS network to perform the output confusion operation, wherein the OR enhanced switch and four-state switch functions are configured as two-state switches; and Configuring a random selection list of switches that are driven by random number 0 or 1 in the network, and performing the cross or direct operation so that the output is infection result.

7. A method as in claim 6, said method, further comprising the steps of: Generating said required random number as N/2 by the random number 0 or 1, and the required random number of randomization operation is N log.sub.2 N−N/2.

8. A method as in claim 1, said method, further comprising the steps of: according to the data width of the output difference that obtained in S2 to determine the width N of INS network, and according to the width N to determine the basic structure of the INS network, wherein the INS network topology is back-to-back butterfly network structure, the switch numbers of each stage is N/2, with a total stage of 2log.sub.2 N−1.

9. A method as in claim 8, said method further comprising the steps of: configuring every stage of the INS network from the 0th stage to stage log.sub.2 N−2 with a N/4 OR enhanced switch, wherein the OR enhanced switch position is the upper part or the lower part of the 0th stage of each sub-network in said INS network.

10. A method as in claim 8, said method further comprising the steps of: Determining, by the security needs of the designer, according to the security requirements of the designer the four-state switch position and the number in said INS network, the four-state switch is located on the stage log.sub.2 N−1 in INS network, and their number; and Setting the Hamming weight balance operation, the four-state switch configuration bits as a random number; and Setting the output confusion operation and the four-state switch configuration bit as a basic two-state switch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is, therefore, intended that the appended claims encompass any such modifications or embodiments.

[0019] FIG. 1 is a structure diagram of a 16 bits input/output Benes network;

[0020] FIG. 1b is a basic principle of the direct state switch;

[0021] FIG. 1c is a basic principle of cross-state switch;

[0022] FIG. 2 is random characteristic figure of a BENES network;

[0023] FIG. 3 is a basic implementation steps diagram of infection measures;

[0024] FIG. 4 is a 16 bits INS structure diagram;

[0025] FIG. 5 is a switches model diagram of OR enhanced switch;

[0026] FIG. 6 is a switch model diagram of four-state switches;

[0027] FIG. 7 is a schematic view of a balanced Hamming weight

[0028] FIG. 8 is an implementation process of an INS network-based infection operation.

[0029] While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not delimit the scope of the present invention.

[0030] One INS network-based anti-fault attack method of random infection that described in this invention, including the following steps:

[0031] One embodiment of the INS network-based anti-fault attack method of random infection that comprises the steps of: Sending the plain-text into an encryption processor, whereby two groups of cipher text are outputted through temporal or spatial redundancy; Conducting XOR operation on the two groups of said cipher text output to obtain the output difference; Sending the said output difference into an infection function module to initiate an infection operation, so that the infection result can be obtained; Obtaining said infection results, then conducting XOR operation on any of the said group cipher text output to generate the final output.

[0032] In one specific embodiment of the present invention, the time redundancy mode generates normal execution and redundant calculation results through repetitive computation; and, the spatial redundancy mode generates normal execution and redundant calculation results in the two same circuits through copying the circuits, respectively.

[0033] In another embodiment of the present invention, the output difference is generated by the corresponding cipher text XOR or other corresponding intermediate variables XOR that are calculated by normal execution and redundancy.

[0034] In another embodiment of the INS network-based anti-fault attack method of random infection, Sending the said output difference into an infection function module, whereby the output difference is sent into the INS network to perform hamming weight balanced process, and continuously sending the resulting output to the INS network after the hamming weight balanced process is performed; and Initiating an output confusion operation to generate the infection results.

[0035] In another embodiment of the INS network-based anti-fault attack method of random infection, the XOR value of infection results is selected corresponding to the intermediate variable; and the infection results are generated as XOR with the selected intermediate variables if the selected intermediate variable is not cipher text; and the XOR results are used to replace the original intermediate variables; and the cryptographic algorithm is continuously performed to generate the final output.

[0036] Another embodiment of the present invention includes the following steps: Sending the said output difference into the INS network to perform a hamming weight balanced process, wherein said output difference is input into the low N/2 bit of INS, and wherein if the output difference is less than N/2 bits, the remaining bits shall be filled with 0, and the INS high N/2-bit input are all bits 0. At this time, the OR enhanced switch is configured to OR function, and four-state switch is configured as random number, and other positions are normal two-state switch.

[0037] Additionally, the OR enhanced switch is configured to the OR function, and the four-state switch is configured as a random number, and the other positions are normal two-state switches. Said output difference is sent back to the INS network to perform the output confusion operation, wherein the OR enhanced switch and four-state switch functions are configured as two-state switches; and configuring a random selection list of switches that are driven by random number 0 or 1 in the network, and performing the cross or direct operation so that the output is infection result.

[0038] In another embodiment of the present invention, said required random number is generated as N/2 by the random number 0 or 1, and the required random number of randomization operation is N log.sub.2 N−N/2.

[0039] Additionally, the structure of the INS network refers to a basic BENES network. The following describes the INS design background from the two aspects of BENES basic network topologies and BENES network random characteristics.

[0040] FIG. 1 is a 16 bit input/output Benes network structure diagram. According to the definition of recursion, a Benes network is made up of multi-stage two-input/two output switches. An N bits Benes network comprises two N/2-bit Benes networks and another two stages (N/2 switches of each stage) of switches. The Dashed box in FIG. 1 marks the sub-network (including 4-input Benes network and 8 inputs Benes network). FIGS. 1b and 1c represent the basic principles of a two state switch: When configuration bit is 0 or 1, the two input switches may perform a straight-through or crossover function. If the configuration bits are entirely random, the probability of a particular input bit being mapped to each output position is the same.

[0041] FIG. 2 is a random characteristic figure of BENES network, showing the randomization feature of a Benes network. The randomization of the configuration information of the Benes network itself will generate randomization displacement output. The following comprises a network topology-based intuitive analysis from the perspective of qualitative explanation. Because of the symmetry of the Benes network, the following only discusses half of the network structure (from stage log.sub.2 N−1 to stage 2log.sub.2 N−1.) The configuration information of i+1-th stage switch will further determine whether the bit data in the i-th stage is mapped in the upper part or the lower part of some selected half part. If the configuration bits are entirely random, the probability for a particular input bit is mapped to each output position is the same. For example, the 3rd stage configuration information in this figure will decide whether the 1-bit data is mapped in the higher 8 bits or lower bits in 16 bits output. Similarly, the configuration information in the 4th stage will further determine whether the information is mapped into the higher 4 bits or lower 4 bits in the selected 8bits output.

[0042] FIG. 3 is a basic implementation steps diagram of infection measures. The purpose of infection measures is to destroy the fault diffusion pattern that is hidden in the output cipher text. The design includes two identical block cipher modules, and selecting the output cipher text (ω, ω′) to generate XOR or the output Δ. Send the Δ into the infection function module to intitial the infection operation. Then make XOR of the infection operation output Δ and any one of the cipher text to get ω⊕I (Δ), then return it to the block cipher module, producing the ω⊕I (Δ) as cipher text. In particular, the two sets of output that obtained from the block cipher module can be cipher text or intermediate variables in the process of encryption. If the selected intermediate variables are cipher text, then it shall produce XOR of the infection results with the intermediate variables, and then the XOR results are used to replace the original intermediate variables, and the cryptographic algorithm is performed so that the final output can be obtained.

[0043] FIG. 4 is a 16 bits INS structure diagram, wherein in the INS network, there are N/4 OR enhanced switches of each stage from the 0-th stage to .sup.log, N−2 stage; the position is the upper half or lower half of the 0-th stage of the INS network and each of its sub-network. For example, in this figure, the OR enhanced switch is in the upper part of the 0-th stage of the 16-bit INS, two 8-bit sub-network, and four 4-bit sub-network. As opposed to the OR enhanced switches, the four-state switch is only present in the stage log.sub.2N−1 (intermediate stage of Benes networks) and the numbers of four-state switch is dynamically set based on the user demands.

[0044] FIG. 5 is a switches model diagram of a OR enhanced switch, and FIG. 6 is a switch model diagram of four-state switches, wherein C1 and C2 are respectively configuration bits of the switch. In an OR enhanced switch, the control switch or the configuration bit C2 of function is added to the original two-state switch (marked by a dashed box). When C2=0, the OR enhanced switch is the same as the two-input switch. Additionally, when C2=1, the OR enhanced switches may perform the OR function. For the four-state switch, the configuration bits of two multiplexers are separated to perform the function of upper broadcast and lower broadcast. When C1⊕C2=0, the function of four-state switch is same with two-state switch.

[0045] FIG. 7 is a schematic view of a balanced Hamming weight. During the process of the hamming weight balance process, Δ is input to the upper part of the INS that corresponds to the input of the 0-th stage OR enhanced switch. The 0-th stage corresponds to the other half input—specifically, the input of the two-state switch is set to 0. In the effect of configuration OR enhanced switch with OR function, it is assumed that Δ≠0 , then the input of log.sub.2 N−2 is “110011001100. . . ”. The Benes network structure is fully utilized so that a non-zero-bit data will finally affect the N/2 bit data. In the middle-stage, four-state switch can randomize the hamming weight to a certain extent (depending on the number of switches), which can further enhance the unpredictability. When the bit configuration of the four-state switch is a random number, the probability that the output equals “00,01,10 and 11” is 25%. In the processing for each data block, a four-state switch requires a two-bit random number. It should be noted that in order to support the replacement operation, the width (N) of the network is usually greater than or equal to Δ, and the power of Δ is typically 2. When the width of Δ and that of N is the same, it can add an additional 64 bit OR logic before the 0th stage and reduce the width of Δ to N/2.

[0046] FIG. 8 is implementation process of INS network-based infection operation. The Hamming weight balance process operation is initially implemented, and the hamming weight balance process OR enhanced switch performs the OR function, and the control bit C2 of the OR enhanced switch is set to 1, generating the output of log.sub.2 N−2, which is half of 1 and half of 0. Users set the numbers of the four-state switch of stage log.sub.2 N−1 according to their security requirements. The four-state switch can randomize the hamming weight to a certain extent (depending on the number of switches).

[0047] During the process of output confusion, the results after the hamming weight balance operation shall be randomized by replacement. At this time, all the switches are configured as the form of two-state switches. Throughout the 2log.sub.2 N−1 stage, randomly select a stage to achieve a control bits randomization. The selected stage-configuration bit is set as a random number to achieve the randomization operation of output confusion. The use of a single stage-based random replacement rather than a full random operation reduces the numbers of random number for infection. The required random number of randomly selected stage to make randomization operation is N/2 bits, while the required random number of full randomization operation is .sup.N log.sub.2 N−N/2. The Infection results I (Δ) width is 2 Δ after the INS input confusion, which must take out half of the data I (Δ)/2 of the infection output as output to generate XOR with the original cipher text or intermediate variable value to get the final cipher text. If the selected intermediate is not cipher text, then the infection results here should generate XOR with the selected intermediate variables, and the XOR results are used to replace the original intermediate variables; and the cryptographic algorithm is used to generate the final output. It should be noted that the proposed method of this patent encompasses all randomizing switches scheme according to the designer security requirements at the output confusion stage. However, this arrangement will increase the random number expenditure of each infection operation, and the random number is generated by a true random number generator (TRNG). Even the existing True Random Number Generator (TRNG) speed is very high, but the required TRNG throughput rate of full randomization (for example, 823-bit random number is needed for 128 bits INS of each infection) still presents a challenge for the TRNG design under the conditions of high speed of encryption. Additionally, single-stage randomization operation does not significantly decrease their safety.

[0048] While this invention has been described with reference to illustrative: embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is, therefore, intended that the appended claims encompass any such modifications or embodiments.