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Fast-Transient Switching Converter with Type III Compensation

20170358984 · 2017-12-14

    Inventors

    Cpc classification

    International classification

    Abstract

    A circuit configured for improving the large signal response of a control stage circuit of a switch mode DC/DC power converter by increasing the differential input range of an error amplifier by segmenting and adding an offset to the error amplifier input and output. When a transient is detected, the feedback voltage is offset in multiple segments by multiple offset voltage sources to prevent saturation of the control stage circuit. Counteracting offset voltages are added to an output of an error amplifier to prevent overshoot or undershoot. A feed-forward compensation signal is generated with the amplitude of the signal being clamped to fixed voltage levels between a minimum and a maximum amplitude of the feed-forward compensation signal. The feed-forward compensation signal is added to the output of the error amplifier to produce an output error signal of the control stage circuit configured for controlling the modulating of the switch mode DC/DC power converter.

    Claims

    1. A control stage circuit within a switch mode DC/DC power converter comprising: a control loop monitor configured for monitoring a difference between an feedback voltage developed from the output voltage of the switch mode DC/DC power converter and a reference voltage; a programmable feedback voltage offset generator configured for providing an offset voltage to the feedback voltage to generate an offset feedback voltage when the control loop monitor detects a large differential between the feedback voltage and the reference voltage; an error amplifier current offset generator configured for generating offset current to be added to the output of the error amplifier; and a feed-forward compensation circuit configured for increasing the input range the feed-forward amplifier output and the error amplifier output.

    2. The control stage circuit of claim 1 wherein the control loop monitor comprising: a first offset reference source comprising: a negative terminal connected for receiving a first reference signal; a second offset reference source comprising: a positive terminal connected for receiving the first reference signal; a first comparator comprising: a non-inverting input terminal connected for receiving the feedback signal, an inverting input terminal connected to a positive terminal of the first offset reference source, a first comparing circuit configured for determining when the feedback signal is greater than the magnitude of the additive combination of the feedback signal and the magnitude of the first reference source for generating a first transient detection signal of a first logic state; a second comparator comprising: a non-inverting input terminal connected for receiving the feedback signal, an inverting input terminal connected to a negative terminal of the second offset reference source, a second comparing circuit configured for determining when the feedback signal is greater than the magnitude of the subtractive combination of the feedback signal and the magnitude of the second reference source for generating a second transient detection signal of a first logic state; and a transient control circuit in communication with the first and second comparing circuits configured for receiving the first and second transient detection signals, configured for determining if any line and/or load transient signal is a large increase or a large decrease in magnitude, and configured for generating output control signals for activating the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit.

    3. The control stage circuit of claim 2 wherein when a large line and/or load transient occurs at the input voltage terminal or the output terminal of the switch mode DC/DC power converter, one of the first or second comparators will be activated and the output terminal of the activated comparator will have a signal level of a first logic state and the output terminal of the deactivated comparator will have a signal level of a second logic level.

    4. The control stage circuit of claim 3 wherein the output signal levels of the first and second comparators are decoded by a transient control circuit that determines if any line and/or load transient is a large increase or a large decrease.

    5. The control stage circuit of claim 4 wherein the control loop monitor logic circuit generates output control signals for generating more or less offset voltage to change the offset of the feedback voltage.

    6. The control stage circuit of claim 5 wherein the output control signals will modify the offset current of the error amplifier of the control stage circuit.

    7. The control stage circuit of claim 2 wherein the programmable feedback offset generator comprises: a resistive voltage divider comprising: a first input terminal receiving the feedback signal, a second input terminal connected to the ground reference voltage source, a plurality of serially connected resistors wherein a first resistor of the plurality of serially connected resistors is connected to the first input terminal and a last resistor of the plurality of serially connected resistors is connected to the second input terminal, a first adjustable current source for selectively providing a first current to the resistive voltage divider for generating the offset feedback voltage of a first polarity comprising a first terminal connected to a power supply voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the first current from the first adjustable current source; a first offset control switch comprising: a first terminal connected to a second terminal of first adjustable current source, a second terminal connected to a third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the first adjustable current source to the third terminal of the resistive divider for selectively providing the first current to the resistive divider for generating the offset feedback voltage; a second adjustable current source for selectively providing a second current to the resistive voltage divider for generating the offset feedback voltage of a second polarity comprising a first terminal connected to a ground reference voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the second current from the second adjustable current source; a second offset control switch comprising: a first terminal connected to a second terminal of second adjustable current source, a second terminal connected to third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the second adjustable current source to the third terminal of the resistive divider for selectively providing the second current to the resistive divider for generating the offset feedback voltage; an output terminal for connecting to a junction of two resistors of the plurality of the serially connected resistors and to a non-inverting input of an error amplifier of the switch mode DC/DC power converter.

    8. The control stage circuit of claim 2 wherein the programmable feedback offset generator comprises a plurality of switched offsetting current sources connected within the error amplifier wherein each of the plurality of offsetting current sources has a control terminal that permits a selected offsetting current source to be activated to modify a threshold value of the error amplifier to generate the offset feedback voltage to be generated.

    9. The control stage circuit of claim 2 wherein the programmable feedback offset generator comprises: an operational amplifier comprising: an inverting terminal connected for receiving the feedback voltage, a non-inverting terminal connected for receiving a reference voltage, and a differential amplifier for generating a difference signal from the feedback voltage and the reference voltage; a transistor of a first conductivity type comprising: a gate connected to an output terminal of the operational amplifier for receiving the difference signal, and a source connected to the power supply voltage source; a resistive voltage divider comprising: a first input terminal connected to a drain of the transistor of the first conductivity type for receiving a difference current generated by the transistor of the first conductivity type from the difference signal, a second input terminal connected to the ground reference voltage source, a plurality of serially connected resistors wherein a first resistor of the plurality of serially connected resistors is connected to the first input terminal and a last resistor of the plurality of serially connected resistors is connected to the second input terminal, a first adjustable current source for selectively providing a first current to the resistive voltage divider for generating the offset feedback voltage of a first polarity comprising a first terminal connected to a power supply voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the first current from the first adjustable current source; a first offset control switch comprising: a first terminal connected to a second terminal of first adjustable current source, a second terminal connected to a third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the first adjustable current source to the third terminal of the resistive divider for selectively providing the first current to the resistive divider for generating the offset feedback voltage; a second adjustable current source for selectively providing a second current to the resistive voltage divider for generating the offset feedback voltage of a second polarity comprising, a first terminal connected to a ground reference voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the second current from the second adjustable current source; a second offset control switch comprising: a first terminal connected to a second terminal of second adjustable current source, a second terminal connected to third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the second adjustable current source to the third terminal of the resistive divider for selectively providing the second current to the resistive divider for generating the offset feedback voltage; an output terminal for connecting to a junction of two resistors of the plurality of the serially connected resistors and to a non-inverting input of an error amplifier.

    10. The control stage circuit of claim 2 wherein the programmable feedback offset generator comprises: a first plurality of current sources, wherein each current source of the first plurality of current sources comprises: a first terminal connected to a power supply voltage source; a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of each current source of the first plurality of current sources; a first plurality of control switches, wherein each control switch of the plurality of control switches comprises: a first terminal connected to a second terminal of one of the first plurality of current sources, a second terminal connected to the second terminal of one of the second plurality of control switches, a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal to the second terminal; a second plurality of current sources, wherein each current source of the second plurality of current sources comprises: a first terminal connected to a ground reference voltage source; a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of each current source of the second plurality of current sources; a second plurality of control switches, wherein each control switch of the plurality of control switches comprises: a first terminal connected to a second terminal of one of the first plurality of current sources, a second terminal connected to the second terminal of one of the first plurality of control switches a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal to the second terminal; a serially connected plurality of resistors wherein a first terminal of a first resistor of the serially connected plurality of resistors is connected to the reference voltage source or to the feedback voltage and a second terminal of a last resistor of the multiple serially connected resistors is connected to one input of the error amplifier, and wherein second terminal of one control switch of the first plurality of control switches and a second terminal of one control switch of the second plurality of control switches is connected to the common connection of two resistors of the serially connected plurality of resistors and a control terminal of each of the first plurality of control switches and the control terminal of the second plurality of control switches permit a selected current source to be activated to offset the voltage level of the feedback voltage or the reference voltage.

    11. The control stage circuit of claim 2 wherein the feed-forward compensation circuit comprises: a plurality of feed-forward capacitors connected in parallel with a first terminal of each of the parallel connected plurality of feed-forward capacitors connected to an output of the control stage circuit and the output of a the error amplifier with in the control stage circuit; a feed-forward finite gain amplifier having a non-inverter terminal receiving the reference voltage and an inverting terminal receiving the feedback signal; a feed-forward compensation control circuit connected between the feed-forward amplifier and the plurality of feed-forward capacitors, wherein the feed-forward control circuit comprises: a plurality of voltage sources comprising a first terminal and a second terminal connected to the ground reference voltage source, wherein a first voltage source of the plurality of voltage sources provides a maximum voltage that is equal to a maximum voltage level of an output of the feed-forward amplifier, a last voltage source that provides a minimum voltage level that is equal to a minimum voltage level of the output of the feed-forward amplifier, and the remaining voltage sources provide voltages provide middle voltage levels between the maximum voltage and the minimum voltage; a first plurality of feed-forward switches, each of the of feed-forward switches comprising: a first terminal connected to the output of the feed-forward operational amplifier, a second terminal connect to the second terminal of one feed-forward capacitor of the plurality of feed-forward capacitors, a control terminal connected to an output of the transient control circuit configured for selectively connecting the output of the feed-forward amplifier to one feed-forward capacitor of the plurality of feed-forward capacitors, a second plurality of feed-forward switches, each of the of feed-forward switches comprising: a first terminal connected to the first terminal of one of the voltage sources, a second terminal connect to the second terminal of one feed-forward capacitor of the plurality of feed-forward capacitors, a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal of the one of the voltage source to one feed-forward capacitor of the plurality of feed-forward capacitors,

    12. The control stage circuit of claim 11 wherein the last voltage source is the ground reference voltage source.

    13. A switch mode DC/DC power converter comprising a control stage circuit within a switch mode DC/DC power converter comprising: a control loop monitor for configured monitoring a difference between a feedback voltage developed from the output voltage of the switch mode DC/DC power converter and a reference voltage; a programmable feedback voltage offset generator configured for providing an offset voltage to the feedback voltage to generate an offset feedback voltage when the control loop monitor detects a large differential between the feedback voltage and the reference voltage; an error amplifier current offset generator configured for generating offset current to be added to the output of the error amplifier; and a feed-forward compensation circuit configured for increasing the input range of the feed-forward amplifier output and the error amplifier output.

    14. The switch mode DC/DC power converter of claim 13 wherein the control loop monitor comprising: a first offset reference source comprising: a negative terminal connected for receiving a first reference signal; a second offset reference source comprising: a positive terminal connected for receiving the first reference signal; a first comparator comprising: a non-inverting input terminal connected for receiving the feedback signal, an inverting input terminal connected to a positive terminal of the first offset reference source, a first comparing circuit configured for determining when the feedback signal is greater than the magnitude of the additive combination of the feedback signal and the magnitude of the first reference source for generating a first transient detection signal of a first logic state; a second comparator comprising: a non-inverting input terminal connected for receiving the feedback signal, an inverting input terminal connected to a negative terminal of the second offset reference source, a second comparing circuit configured for determining when the feedback signal is greater than the magnitude of the subtractive combination of the feedback signal and the magnitude of the second reference source for generating a second transient detection signal of a first logic state; and a transient control circuit in communication with the first and second comparing circuits configured for receiving the first and second transient detection signals, configured for determining if any line and/or load transient signal is a large increase or a large decrease in magnitude, and configured for generating output control signals for activating the programmable feedback voltage offset generator, the error amplifier current offset generator, and the feed-forward compensation circuit.

    15. The switch mode DC/DC power converter of claim 14 wherein when a large line and/or load transient occurs at the input voltage terminal or the output terminal of the switch mode DC/DC power converter, one of the first or second comparators will be activated and the output terminal of the activated comparator will have a signal level of a first logic state and the output terminal of the deactivated comparator will have a signal level of a second logic level.

    16. The switch mode DC/DC power converter of claim 15 wherein the output signal levels of the first and second comparators are decoded by a transient control logic circuit that determines if any line and/or load transient is a large increase or a large decrease.

    17. The switch mode DC/DC power converter of claim 16 wherein the control loop monitor logic circuit generates output control signals for generating more or less offset voltage to change the offset of the feedback voltage.

    18. The switch mode DC/DC power converter of claim 17 wherein the output control signals will modify the offset current of the error amplifier of the control stage circuit.

    19. The switch mode DC/DC power converter of claim 14 wherein the programmable feedback offset generator comprises: a resistive voltage divider comprising: a first input terminal receiving the feedback signal, a second input terminal connected to the ground reference voltage source, a plurality of serially connected resistors wherein a first resistor of the plurality of serially connected resistors is connected to the first input terminal and a last resistor of the plurality of serially connected resistors is connected to the second input terminal, a first adjustable current source for selectively providing a first current to the resistive voltage divider for generating the offset feedback voltage of a first polarity comprising a first terminal connected to a power supply voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the first current from the first adjustable current source; a first offset control switch comprising: a first terminal connected to a second terminal of first adjustable current source, a second terminal connected to a third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the first adjustable current source to the third terminal of the resistive divider for selectively providing the first current to the resistive divider for generating the offset feedback voltage; a second adjustable current source for selectively providing a second current to the resistive voltage divider for generating the offset feedback voltage of a second polarity comprising a first terminal connected to a ground reference voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the second current from the second adjustable current source; a second offset control switch comprising: a first terminal connected to a second terminal of second adjustable current source, a second terminal connected to third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the second adjustable current source to the third terminal of the resistive divider for selectively providing the second current to the resistive divider for generating the offset feedback voltage; an output terminal for connecting to a junction of two resistors of the plurality of the serially connected resistors and to a non-inverting input of an error amplifier.

    20. The switch mode DC/DC power converter of claim 14 wherein the programmable feedback offset generator comprises a plurality of switched offsetting current sources connected within the error amplifier wherein each of the plurality of offsetting current sources has a control terminal that permits a selected offsetting current source to be activated to modify a threshold value of the error amplifier to generate the offset feedback voltage to be generated.

    21. The switch mode DC/DC power converter of claim 14 wherein the programmable feedback offset generator comprises: an operational amplifier comprising: an inverting terminal connected for receiving the feedback voltage, a non-inverting terminal connected for receiving a reference voltage, and a differential amplifier for generating a difference signal from the feedback voltage and the reference voltage; a transistor of a first conductivity type comprising: a gate connected to an output terminal of the operational amplifier for receiving the difference signal, and a source connected to the power supply voltage source; a resistive voltage divider comprising: a first input terminal connected to a drain of the transistor of the first conductivity type for receiving a difference current generated by the transistor of the first conductivity type from the difference signal, a second input terminal connected to the ground reference voltage source, a plurality of serially connected resistors wherein a first resistor of the plurality of serially connected resistors is connected to the first input terminal and a last resistor of the plurality of serially connected resistors is connected to the second input terminal, a first adjustable current source for selectively providing a first current to the resistive voltage divider for generating the offset feedback voltage of a first polarity comprising a first terminal connected to a power supply voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the first current from the first adjustable current source; a first offset control switch comprising: a first terminal connected to a second terminal of first adjustable current source, a second terminal connected to a third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the first adjustable current source to the third terminal of the resistive divider for selectively providing the first current to the resistive divider for generating the offset feedback voltage; a second adjustable current source for selectively providing a second current to the resistive voltage divider for generating the offset feedback voltage of a second polarity comprising a first terminal connected to a ground reference voltage source, and a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of the second current from the second adjustable current source; a second offset control switch comprising: a first terminal connected to a second terminal of second adjustable current source, a second terminal connected to third terminal of the resistive divider, a control terminal connected to an output of the transient control circuit configured for selectively connecting the second terminal of the second adjustable current source to the third terminal of the resistive divider for selectively providing the second current to the resistive divider for generating the offset feedback voltage; an output terminal for connecting a junction of two resistors of the plurality of the serially connected resistors and to a non-inverting input of an error amplifier.

    22. The switch mode DC/DC power converter of claim 14 wherein the programmable feedback offset generator comprises: a first plurality of current sources, wherein each current source of the first plurality of current sources comprises: a first terminal connected to a power supply voltage source; a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of each current source of the first plurality of current sources; a first plurality of control switches, wherein each control switch of the plurality of control switches comprises: a first terminal connected to a second terminal of one of the first plurality of current sources, a second terminal connected to the second terminal of one of the second plurality of control switches, a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal to the second terminal; a second plurality of current sources, wherein each current source of the second plurality of current sources comprises: a first terminal connected to a ground reference voltage source; a control terminal connected to an output of the transient control circuit configured for adjusting the amplitude of each current source of the second plurality of current sources; a second plurality of control switches, wherein each control switch of the plurality of control switches comprises: a first terminal connected to a second terminal of one of the first plurality of current sources, a second terminal connected to the second terminal of one of the first plurality of control switches, a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal to the second terminal; a serially connected plurality of resistors wherein a first terminal of a first resistor of the serially connected plurality of resistors is connected to the reference voltage source or to the feedback voltage and a second terminal of a last resistor of the multiple serially connected resistors is connected to one input of the error amplifier, and wherein second terminal of one control switch of the first plurality of control switches and a second terminal of one control switch of the second plurality of control switches is connected to the common connection of two resistors of the serially connected plurality of resistors and a control terminal of each of the first plurality of control switches and the control terminal of the second plurality of control switches permit a selected current source to be activated to offset the voltage level of the feedback voltage or the reference voltage.

    23. The switch mode DC/DC power converter of claim 14 wherein the feed-forward compensation circuit comprises: a plurality of feed-forward capacitors connected in parallel with a first terminal of each of the parallel connected plurality of feed-forward capacitors connected to an output of the control stage circuit and the output of a the error amplifier with in the control stage circuit; a feed-forward amplifier having a non-inverting terminal receiving the reference voltage and an inverting terminal receiving the feedback signal; a feed-forward compensation control circuit connected between the feed-forward amplifier and the plurality of feed-forward capacitors, wherein the feed-forward control circuit comprises: a plurality of voltage sources comprising a first terminal and a second terminal connected to the ground reference voltage source, wherein a first voltage source of the plurality of voltage sources provides a maximum voltage that is equal to a maximum voltage level of an output of the feed-forward amplifier, a last voltage source that provides a minimum voltage level that is equal to a minimum voltage level of the output of the feed-forward amplifier, and the remaining voltage sources provide voltages provide middle voltage levels between the maximum voltage and the minimum voltage; a first plurality of feed-forward switches, each of the of feed-forward switches comprising: a first terminal connected to the output of the feed-forward amplifier, a second terminal connect to the second terminal of one feed-forward capacitor of the plurality of feed-forward capacitors, a control terminal connected to an output of the transient control circuit configured for selectively connecting the output of the feed-forward amplifier to one feed-forward capacitor of the plurality of feed-forward capacitors, a second plurality of feed-forward switches, each of the of feed-forward switches comprising: a first terminal connected to the first terminal of one of the voltage sources, a second terminal connect to the second terminal of one feed-forward capacitor of the plurality of feed-forward capacitors, a control terminal connected to an output of the transient control circuit configured for selectively connecting the first terminal of the one of the voltage source to one feed-forward capacitor of the plurality of feed-forward capacitors,

    24. The switch mode DC/DC power converter of claim 23 wherein the last voltage source is the ground reference voltage source.

    25. A method for improving the large signal response of control stage circuit of a switch mode DC/DC power converter comprises the steps of: increasing the differential input range of an error amplifier of the control stage circuit by the steps of: segmenting a feedback signal developed from an output of the switch mode DC/DC power converter; and adding an offset to the error amplifier input and output.

    26. The method of claim 25 wherein the segmenting and adding an offset comprises the steps of: monitoring a control loop of the switch mode DC/DC power converter to determine a difference between a feedback voltage developed from the output voltage of the switch mode DC/DC power converter and a reference voltage. determining that a transient has occurred at the input terminal or output terminal of the switch mode DC/DC power converter from the difference of the between a feedback voltage developed from the output voltage and the reference voltage; offsetting the feedback voltage developed from the output voltage into multiple segments by multiple offset voltages to prevent saturation of the control stage circuit when a large transient signal is received; adding counteracting offset voltages to an output of an error amplifier of the control stage circuit configured for maintaining the output voltage of the error amplifier to prevent overshoot or undershoot; generating a feed-forward compensation signal with the amplitude of the signal being clamped to at least one fixed voltage level between a minimum and a maximum amplitude of the feed-forward compensation signal; and adding the feed-forward compensation signal to the output of the error amplifier to produce an output error signal of the control stage circuit configured for controlling the modulating of the input power voltage of the switch mode DC/DC power converter.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0027] FIG. 1a is a block diagram of a switch mode DC/DC power converter.

    [0028] FIG. 1b is a schematic diagram of a control stage circuit of the related art of the switch mode DC/DC power converter of FIG. 1a.

    [0029] FIG. 1c is a plot of gain and phase vs. frequency of the control stage circuit control stage circuit of the related art of the switch mode DC/DC power converter of FIG. 1a.

    [0030] FIG. 2 is a plot of the large signal response of the error amplifier and output voltage of the switch mode DC/DC power converter FIG. 1a employing the control stage circuit of the related art.

    [0031] FIG. 3 is a schematic diagram of control stage circuit as implemented for a switch mode DC/DC power converter of the present disclosure as shown in FIG. 1a.

    [0032] FIG. 4a is a plot of the transfer function of the error amplifier of the control stage circuit of the related art of the switch mode DC/DC power converter of FIG. 1a.

    [0033] FIG. 4b is a plot of the transfer function of the transconductance amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0034] FIG. 4c is plot of the transfer function of the transconductance amplifier and offset current source of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0035] FIG. 4d is plot of the transfer function of the feed-forward amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0036] FIG. 4e is plot of the transfer function of the error amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0037] FIGS. 5a, 5b, 5c, 5d-1 and 5d-2 are schematic diagrams of embodiments of input offset generators as implemented for the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0038] FIGS. 6a and 6b are schematic diagrams of embodiments of the feed-forward capacitor control circuit as implemented for the control stage circuit as implemented for a switch mode DC/DC power converter of the present disclosure.

    [0039] FIGS. 7a and 7b are plots of the output voltage versus time of the feed-forward amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0040] FIG. 8 is a plot of the behaviour of the control stage circuit of the present disclosure of FIG. 3 of the switch mode DC/DC power converter of FIG. 1a.

    [0041] FIG. 9 is a plot of the load transient (1 mA to 0.8 A) with and without the control stage circuit of the present disclosure of FIG. 3.

    [0042] FIG. 10 is a flowchart of a method for operating a switch mode DC/DC power converter of the present disclosure.

    DETAILED DESCRIPTION

    [0043] To improve the large signal response, the control stage circuit as implemented for a switch mode DC/DC power converter of the present disclosure increases the differential input range of an error amplifier within the control stage circuit by segmenting and adding an offset to the error amplifier input and output.

    [0044] FIG. 3 is a schematic diagram of control stage circuit 105 as implemented for a switch mode DC/DC power converter of the present disclosure showing the segmenting, the adding an offset to the error amplifier 115 input and output, and the adding of additional feed-forward-capacitors Cff.sub.1 and Cff.sub.2 to the compensator circuit 120. The control stage circuit is structured similarly to that of the control stage circuit of the related art of FIG. 1b.

    [0045] The control stage circuit 5 has an error amplifier 115 that includes a transconductance amplifier 117. The transconductance amplifier 117 receives the offset feedback signal V.sub.FB′ at its inverting terminal (−) from the terminal 125 and the reference voltage V.sub.REF at its non-inverting terminal (+) from the terminal 130. The output of the transconductance amplifier 117 is connected to a first terminal of the feed-forward resistor R.sub.ff and the first terminal of the compensation capacitor C.sub.c. The second terminal of the compensation capacitor C.sub.c is connected to the ground reference voltage. The second terminal of feed forward resistor R.sub.ff is connected to the summation node 116. The summation node 116 is a single connection for combining the output signal V.sub.OEA of the error amplifier 115 with the output signal V.sub.COMP of the compensator 120. The summation of the output signal V.sub.OEA of the error amplifier 115 and the output signal V.sub.COMP of the compensator 120 provides the difference output voltage V.sub.DIF to terminal 7 for transmission the power stage 10. Since the summation node 116 is simple connection with not physical circuitry, it is not described further hereinafter.

    [0046] The compensator 120 adds feed-forward compensation that increases the phase margin, defined as the difference between the unity-gain phase shift and −180°, which is the point where the loop becomes unstable.

    [0047] The feed-forward finite gain amplifier 122 receives the offset feedback signal V.sub.FB′ at its inverting terminal (−) and the reference voltage V.sub.REF at its non-inverting terminal (+). The output of the feed-forward finite gain amplifier 122 is connected to the first terminal of the multiple feed-forward capacitors Cff.sub.1 and Cff.sub.2 through the switches SW1 and SW2. The second terminal of each of the feed-forward capacitors Cff.sub.1 and Cff.sub.2 is connected to the second terminal of the feed forward resistor R.sub.ff and connected to the output terminal 7 of the error amplifier 115 for providing the error amplifier voltage V.sub.OEA to the power stage 10.

    [0048] The terminal 125 is connected to a first terminal (+) of the adjustable offset voltage source 114, such that the adjustable offset voltage source 114 receives the feedback signal V.sub.FB. The adjustable offset voltage source 114 provides an adjustment voltage V.sub.ADJ that is added to the feedback signal V.sub.FB to create the offset feedback signal V.sub.FB′. The second terminal (−) of the offset voltage source 114 is connected 135 to the input of the control stage circuit 105 to provide the offset feedback signal V.sub.FB′ to the inputs of the error amplifier 115 and the compensator 120. The terminal 130 is connected to the input of the control stage circuit 105 to provide the reference voltage V.sub.REF to the inputs of the error amplifier 115 and the compensator 120.

    [0049] The control loop monitor 100 receives the offset feedback signal V.sub.FB′ and the reference voltage V.sub.REF. The control loop monitor 100 is configured for determining that a large transient has occurred at the line and/or the load of the switch mode DC/DC power converter. The control loop monitor 100 has a first offset voltage source 102 and a second offset voltage source 104. A negative terminal of the first offset voltage source 102 is connected to receive the reference voltage V.sub.REF and the positive terminal of the first offset voltage source 102 is connected to an inverting terminal of a first comparator circuit 106. A positive terminal of the second offset voltage source 104 is connected to receive the reference voltage V.sub.REF and the negative terminal of the second offset voltage source 104 is connected to an inverting terminal of a second comparator circuit 108. The first and second offset voltage sources 102 and 104 to set positive voltage boundary V.sub.OFF1 and negative voltage boundary V.sub.OFF2 for the feedback signal V.sub.FB. The offset feedback signal V.sub.FB′ is applied to the non-inverting terminals of the first and second comparators 106 and 108. When a large line and/or load transient occurs at the input voltage terminal V.sub.IN or the output terminal V.sub.OUT of the switch mode DC/DC power converter as shown in FIG. 1a, one of the first or second comparators 106 and 108 will be activated and the output terminal of the activated comparator will have a signal level of a first logic state and the output terminal of the deactivated comparator will have a signal level of a second logic level. The output signal levels of the first and second comparators 106 and 108 are decoded by a control loop monitor logic circuit 110 that determines if any line and/or load transient is a large increase or a large decrease.

    [0050] The output 112 of the control loop monitor logic circuit 110 is a program/select line. The program/select line 112 is at least one connection applied to the adjustable offset voltage source 114 for controlling the offset voltage of the segments applied to the feedback signal V.sub.FB for determining the offset feedback signal V.sub.FB′. The program/select line 112 is at least one connection applied to the switches SW1 and SW2 for controlling the feed-forward compensation during an occurrence of the large line and/or load transient at the input voltage terminal V.sub.IN or the output terminal V.sub.OUT of the switch mode DC/DC power converter.

    [0051] The transconductance amplifier 117 receives the offset feedback signal V.sub.FB′ requires an equivalent but with opposing polarity offset voltages at the output terminal 118 of the transconductance amplifier 117 to generate a corrected output signal V.sub.OGM. An offset current source 119 is connected to the transconductance amplifier 117 for generating the output offset current that develops the offset voltage across the feed-forward resistor Rff.

    [0052] FIG. 4a is a plot of the transfer function of the error amplifier of the control stage circuit of the related art of the switch mode DC/DC power converter of FIG. 1a. FIG. 4b is a plot of the transfer function of the transconductance amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a. FIG. 4c is plot of the transfer function of the transconductance amplifier and offset current source of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a. FIG. 4d is plot of the transfer function of the feed-forward amplifier of the control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a. FIG. 4e is plot of the transfer function of the error amplifier of the control stage circuit control stage circuit of the present disclosure of the switch mode DC/DC power converter of FIG. 1a.

    [0053] In FIG. 4a, the horizontal axis 205 is the amplitude of the feedback signal V.sub.FB and the vertical axis 200 is the amplitude of the output signal V.sub.OEA of the error amplifier 15 of the related art as shown in FIG. 1b. The line 210 represents an idealized transfer characteristic of the feedback signal V.sub.FB versus the output signal V.sub.OEA. The line 215 represents the actual transfer characteristic of the feedback signal V.sub.FB versus the output signal V.sub.OEA for FIGS. 4a-4e. As the amplitude of the feedback signal V.sub.FB becomes very large, the output signal V.sub.OEA begins flatten as the amplifier begins to saturate.

    [0054] Referring to FIGS. 3 and 4b, the horizontal axis 205 is the amplitude of the feedback signal V.sub.FB and the vertical axis 220 is the amplitude of the output signal V.sub.OEA of the error amplifier 115. The line 210 represents an idealized transfer characteristic of the feedback signal V.sub.FB versus the transconductance amplifier output signal V.sub.oGm. The magnitude of the feedback signal V.sub.FB is now segmented as shown with line 225, once the magnitude of the feedback signal V.sub.FB has reach a relatively large level and the output signal V.sub.OGM is approaching the saturation level. The segmentation of the feedback signal V.sub.FB is accomplished by adding voltage offsets 230 and 235 to the feedback signal V.sub.FB.

    [0055] Referring to FIGS. 3 and 4c, the horizontal axis 205 is the amplitude of the feedback signal V.sub.FB and the vertical axis 240 is the amplitude of the output signal V.sub.OGM of the transconductance amplifier 117 plus the offset current source 119. The line 212 represents an idealized transfer characteristic of the feedback signal V.sub.FB versus the output signal V.sub.OGM of the transconductance amplifier 117. The transconductance amplifier 117 receives the offset feedback signal V.sub.FB′ as shown in line 225 and therefore requires equivalent but with opposing polarity offset voltages 270 and 275 at the output voltage terminal of the transconductance amplifier 117 to generate a corrected output signal V.sub.OEA.

    [0056] Referring to FIGS. 3 and 4d, the impact of the offset voltage level in the feed-forward path is not important to the compensation circuit 120, so the counter offset voltage is not applied to the feed-forward output signal V.sub.ff. The selection of the feed-forward-capacitors and the addition of the feed-forward voltage sources are described hereinafter.

    [0057] Referring to FIG. 3 and FIG. 4e, the horizontal axis 207 is the amplitude of the differential voltage between the feedback signal V.sub.FB and the reference voltage V.sub.REF. The vertical axis 220 is the amplitude of the output signal V.sub.OEA of the error amplifier 115. The input range, as shown, is the difference between the actual transfer characteristic of the feedback signal V.sub.FB versus the output signal V.sub.OEA and the increased transfer characteristic 285 and 290 of the compensator of the 120. The input range of the compensator 120 can be increased by increasing the number of segments of the offset voltages applied to the feedback signal V.sub.FB.

    [0058] FIGS. 5a, 5b, 5c, 5d-1 and 5d-2 are schematic diagrams of embodiments of input offset generators as implemented for the control stage circuit of the present disclosure. Referring to FIG. 5a, the feedback signal V.sub.FB is connected to a first terminal of a voltage divider 140. A second terminal of the voltage divider 140 is connected to the ground reference voltage source. The voltage divider is formed of multiple series connected resistors. In the implementation of FIG. 5a, there are three series connected resistors R.sub.1, R.sub.2, and R.sub.3. A third terminal 135 is formed at a junction of the second resistor R.sub.2 and the third resistor R.sub.3 to provide the offset feedback signal V.sub.FB′ to the control stage circuit 105.

    [0059] A first adjustable current source I.sub.1 has a first terminal connected to a power supply voltage source VDD and a second terminal connected to a first terminal of a third switch SW3. A second terminal of the third switch SW3 is connected to the fourth terminal of the voltage divider 140 that is connected to a junction of the first resistor R.sub.1 and the second resistor R.sub.2. A second adjustable current source I.sub.2 has a first terminal connected to a first terminal of a fourth switch SW4 and a second terminal of the fourth switch SW4 is connected to the junction of the second terminal of the third switch SW3 and the fourth terminal of the voltage divider 140. The second terminal of the second adjustable current source I.sub.2 is connected to the ground reference voltage.

    [0060] The control terminals of the first adjustable current source I.sub.1 and second adjustable current source I.sub.2 are connected to the program line 112b. The program line 112b is at least one connection applied to the first adjustable current source I.sub.1 and second adjustable current source I.sub.2 for programming the current levels and thus the offset voltage of the offset feedback voltage V.sub.FB′. The control terminals of the switches SW3 and SW4 are connected to the select line 112a. The select line 112a is at least one connection applied to the switches SW3 and SW4 for activating the first adjustable current source I.sub.1 and second adjustable current source I.sub.2 and thus set the polarity of the offset feedback voltage V.sub.FB′.

    [0061] Referring to FIG. 5b, the offset feedback voltage V.sub.FB′ is generated within the transconductance amplifier 117. The differential pair of PMOS transistors MP1 and MP2 forms the transconductance amplifier. The feedback signal V.sub.FB is applied to the gate of the PMOS transistor MP1 and the reference voltage V.sub.REF is applied to the gate of the PMOS transistor MP2. The load current mirror is formed of the NMOS transistors MN1 and MN2. The NMOS transistor MN1 has is drain and gate connected together and connected to the drain of the PMOS transistor MP1 to form the inverting output V.sub.O−. The diode connected transistor MN1 forms the reference leg of the load current mirror and the NMOS transistor MN2 forms the mirror leg of the load current mirror. The gate of the NMOS transistor MN2 is connected to the drain and gate of the NMOS transistor MN1. The sources of the NMOS transistors MN1 and MN2 are connected to the ground reference voltage source. The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP2 to form the non-inverting output V.sub.O+.

    [0062] In a traditional transconductance amplifier, the sources of the PMOS transistors MP1 and MP2 are connected together and to a single current source I.sub.4. To provide the necessary offset voltage to the feedback signal V.sub.FB, the source of the PMOS transistors MP1 is connected to a first terminal of the resistor R.sub.4 and the source of the PMOS transistors MP2 is connected to a first terminal of the resistor R.sub.5. The second terminals of the resistors R.sub.4 and R.sub.5 are connected together. The effective offset voltage is selectively generated by the adjustable current sources I.sub.3, I.sub.5, I.sub.6, and I.sub.7. The common connection of the source of the PMOS transistors MP1 and the first terminal of the resistor R.sub.4 is connected to the first terminal of a switch SW5. The second terminal of a switch SW5 is connected to a first terminal of the current source I.sub.3 and the second terminal of the current source I.sub.3 is connected to the power supply voltage source VDD. The common connection of the source of the PMOS transistors MP1 and the first terminal of the resistor R.sub.4 is also connected to the first terminal of a switch SW7. The second terminal of a switch SW7 is connected to a first terminal of the current source I.sub.6 and the second terminal of the current source I.sub.6 is connected to the ground reference voltage source. The commonly connected second terminals of the resistors R.sub.4 and R.sub.5 are connected to a first terminal of the current source I.sub.4. The second terminal of the current source I.sub.4 is connected to the power supply voltage source VDD. The common connection of the source of the PMOS transistors MP2 and the first terminal of the resistor R.sub.5 is connected to the first terminal of a switch SW6. The second terminal of a switch SW6 is connected to a first terminal of the current source I.sub.5 and the second terminal of the current source I.sub.5 is connected to the power supply voltage source VDD. The common connection of the source of the PMOS transistors MP2 and the first terminal of the resistor R.sub.5 is also connected to the first terminal of a switch SW8. The second terminal of a switch SW8 is connected to a first terminal of the current source I.sub.7 and the second terminal of the current source I.sub.7 is connected to the ground reference voltage source.

    [0063] The control terminals of the switches SW5, SW6, SW7, and SW8 are connected to the select line 112a. The select line 112a is at least one connection applied to the switches SW5, SW6, SW7, and SW8 for selectively activating the adjustable current sources I.sub.3, I.sub.5, I.sub.6, and I.sub.7 and thus set the polarity of the offset of the reference voltage V.sub.FB. When SW5 and SW8 are activated, a negative offset voltage (R.sub.4+R.sub.5)×I.sub.3 where I.sub.3=I.sub.7 is given to the feedback signal V.sub.FB. When SW6 and SW7 are activated, a positive offset voltage (R.sub.4+R.sub.5)×I.sub.5 where I.sub.5=I.sub.6 is given to the feedback signal V.sub.FB. The control terminals of the adjustable current sources I.sub.3, I.sub.5, I.sub.6, and I.sub.7 are connected to the program line 112b. The program line 112b is at least one connection applied to the adjustable current sources I.sub.3, I.sub.5, I.sub.6, and I.sub.7 for programming the current levels and thus the offset voltage level applied to the feedback voltage V.sub.FB.

    [0064] Referring to FIG. 5c, the offset generator utilizes a resistive divider 155 from a digital-to-analog converter employed in the circuitry for generating the reference voltage V.sub.REF. The voltage divider is formed of multiple series connected resistors R.sub.11, R.sub.12, . . . , R.sub.n. A first terminal of the voltage divider 155 connects a first terminal of the first resistor R.sub.11 of the voltage divider 155 to a drain of a PMOS transistor MP3. A second terminal of the voltage divider 155 connects a first terminal of the last resistor R.sub.n of the voltage divider 155 to the ground reference voltage level. A third terminal 160 is formed at a junction of two of the serially connected resistors R.sub.11, R.sub.12, . . . , R.sub.n of the voltage divider 155 to provide the offset reference voltage V.sub.REF′ to the control stage circuit 105.

    [0065] The terminal 130 applies the reference voltage V.sub.REF to an inverting input of an operational amplifier 150. The non-inverting input of the operational amplifier 150 is connected to one junction of two of the resistors of the resistive divider 155 to provide feedback from the resistive divider 155 to the operational amplifier 150. The output of the operational amplifier 150 is connected to the gate of the PMOS transistor MP3. The output signal of the operational amplifier 150 provides a biasing voltage for the PMOS transistor MP3 to control the current through the resistive divider 155.

    [0066] A first terminal of an adjustable current source I.sub.8 is connected to the power supply voltage source VDD and a second terminal of the adjustable current source I.sub.8 is connected to a first terminal of the switch SW9. A second terminal of the switch SW9 is connected to a first terminal of the switch SW10. The second terminal of the switch SW10 is connected to a first terminal of the adjustable current source I.sub.9 and the second terminal of the adjustable current source I.sub.9 is connected to the ground reference voltage source. The common junction of the second terminal of the switch SW9 and the first terminal of the switch SW10 is connected to a junction of one pair of resistors of the resistive divider 155 for selectively providing a current to the resistive divider 155 for creating the necessary offset to the reference voltage V.sub.REF. The control terminals of the current source I.sub.8 and current source I.sub.9 are connected to the program line 112b. The program line 112b is at least one connection applied to the adjustable current source I.sub.8 and adjustable current source I.sub.9 for programming the current levels and thus the offset voltage of the offset reference voltage V.sub.REF′. The control terminals of the switches SW9 and SW10 are connected to the select line 112a. The select line 112a is at least one connection applied to the switches SW9 and SW10 for activating the adjustable current source I.sub.8 and adjustable current source I.sub.9 and thus set the polarity of the offset reference voltage V.sub.REF′.

    [0067] Referring to FIG. 5d-1 for a generalization of an offset generator providing multiple offsets to the offset feedback signal V.sub.FB′ to generate multiple segments to the output V.sub.OEA, of the control stage circuit 105. Multiple resistors R.sub.13, . . . , R.sub.1n are connected serially together. The first terminal of the first resistor R.sub.13 is connected to the terminal 130 for receiving the feedback signal V.sub.FB. The second terminal of the resistor R.sub.1n is connected to the terminal 160 to provide the offset feedback signal V.sub.FB to the control stage circuit 105. The first terminals of the adjustable current sources I.sub.10, I.sub.11, . . . , and I.sub.1m are connected to the power supply voltage source VDD. The second terminals of the adjustable current sources I.sub.10, I.sub.11, . . . , and I.sub.1m are connected to the first terminals of the switches SW11, SW12, . . . , SW1m and the second terminals of the switches SW11, SW12, . . . , SW1m are connected to the first terminals of the switches SW13, SW14, . . . , SW1n. The second terminals of the switches SW13, SW14, . . . , SW1n are connected to the first terminals of the adjustable current sources I.sub.12, I.sub.13, . . . , and I.sub.1n and the second terminals of the adjustable current sources I.sub.12, I.sub.13, . . . , and I.sub.1n are connected to the ground reference voltage source.

    [0068] The junction of the second terminal of the switch SW11 and first terminal of the switch SW13 is connected to the first terminal of the resistor R.sub.13. Similarly, the junctions of the second terminal of the switches SW12, . . . , and first terminals of the switches SW14, . . . , are connected to the junctions of the multiple resistors R.sub.13, . . . , R.sub.1n. Finally, the junction of the second terminal of the switch SW1m and first terminal of the switch SW1n is connected to the second terminal of the resistor R.sub.1n and the output terminal 160 for providing the offset feedback voltage V.sub.FB′. The control terminals of the switches SW11, SW12, . . . , SW1m and switches SW13, SW14, . . . , SW1n are connected to the select line 112a. The select line 112a is at least one connection applied to the switches SW11, SW12, . . . , SW1m and switches SW13, SW14, . . . , SW1n for activating the adjustable current sources I.sub.10, I.sub.11, . . . , and I.sub.1m and adjustable current sources I.sub.12, I.sub.13, . . . , and I.sub.1n to thus set the polarity of the offset feedback signal V.sub.FB′. The control terminals of the adjustable current sources I.sub.10, I.sub.11, . . . , and I.sub.1m and adjustable current sources I.sub.12, I.sub.13, . . . , and I.sub.1n are connected to the program line 112b to thus set the amplitude of the offset voltage for the offset feedback signal V.sub.FB′.

    [0069] It should be noted that the terminal 130 applies the feedback signal V.sub.FB to the first terminal of the first resistor R.sub.13. However, if the reference voltage V.sub.REF is applied to the first terminal of the first resistor R.sub.13, the output voltage is the offset reference voltage V.sub.REF′ and generates the segments for increasing the differential input range of the control stage circuit 105.

    [0070] Referring to FIG. 5d-2, the offset generator 114 is a simplified version of the offset generator 114 of FIG. 5d-1. In this case there is one single resistor R.sub.13 with its first terminal connected to the terminal 130 to receive the feedback signal V.sub.FB. The second terminal of the resistor R.sub.13 is connected to the terminal 160 to transfer the offset feedback signal V.sub.FB′ to the control stage circuit 105. The first terminals of the adjustable current sources I.sub.10, and I.sub.11 are connected to the power supply voltage source VDD. The second terminals of the adjustable current sources I.sub.10 and I.sub.11 are respectively connected to the first terminals of the switches SW11 and SW12 and the second terminals of the switches SW11 and SW12 are respectively connected to the first terminals of the switches SW13 and SW14. The second terminals of the switches SW13 and SW14 are respectively connected to the first terminals of the adjustable current sources I.sub.12 and I.sub.13 and the second terminals of the adjustable current sources I.sub.12 and I.sub.13 are connected to the ground reference voltage source.

    [0071] The junction of the second terminal of the switch SW11 and first terminal of the switch SW13 is connected to the first terminal of the resistor R.sub.13. Similarly, the junctions of the second terminal of the switches SW12 and first terminal of the switch SW14 are connected to the second terminal of the resistor R.sub.13 and the output terminal 160 for providing the offset feedback voltage V.sub.FB′.

    [0072] The select line 112a is at least one connection applied to the switches SW11 and SW12 and switches SW13 and SW14 for activating the adjustable current sources I.sub.10 and I.sub.11 and adjustable current sources I.sub.12 and I.sub.13 to thus set the polarity of the offset feedback signal V.sub.FB′. The control terminals of the adjustable current sources I.sub.10 and I.sub.11 and adjustable current sources I.sub.12 and I.sub.13 are connected to the program line 112b to thus set the amplitude of the offset voltage for the offset feedback signal V.sub.FB′.

    [0073] FIGS. 6a and 6b are schematic diagrams of embodiments of the feed-forward capacitor control circuit of the control stage circuit as implemented for a switch mode DC/DC power converter of the present disclosure. Referring to FIG. 6a for a generalization of the feed-forward capacitor control circuit of the control stage circuit of the present disclosure. The output of the feed-forward amplifier 122 of the compensator 120 is connected to the first terminals of the switches SW21, SW22, . . . , SW2n and the second terminals of the switches SW21, SW22, . . . , SW2n are connected to the first terminals of the capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n. The first terminals (+) of the voltage sources 175a, 175b, . . . , 175n-1, 175n are connected to the first terminals of the switches SW31, SW32, SW3n. The second terminals (−) of the voltage sources 175a, 175b, . . . , 175n-1, 175n are connected to the ground reference voltage source. The second terminals of the switches SW31, SW32, SW3n are connected to the first terminals of the capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n. The second terminals of the capacitors CM, Cff.sub.2, . . . , Cff.sub.n are commonly connected together and to the output of the error amplifier 115 that is connected to the terminal 7 that provides the control stage circuit difference output voltage V.sub.DIF to the input of the power stage 10 of FIG. 1a. The select line 112a is connected to the control terminal of the switches SW21, SW22, . . . , SW2n and the switches SW31, SW32, . . . , SW3n for selecting which of the capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n are connected to the feed-forward operational amplifier 122 and which of the voltage sources 175a, 175b, . . . , 175n-1, 175n are connected to the capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n. The number of capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n is determined by the number of desired segments for increasing the input range of the control stage circuit 105 of FIG. 3.

    [0074] Referring to FIG. 6b for an implementation of the feed-forward capacitor control circuit of the control stage circuit of the present disclosure. The number of capacitors Cff.sub.1, Cff.sub.2, . . . , Cff.sub.n being one less than the desired number of stages. In this instance, the requirement is for three segments in the transfer curve and therefore two feed-foreword capacitors Cff.sub.1 and Cff.sub.2. The minimum voltage is determined to be zero volts or the level of the ground reference voltage source. Therefore, the voltage source 175n is set to zero volts or eliminated and the first terminal of the switch SW31 is connected to the ground reference voltage source. The mid-level feed-forward voltage source V.sub.ff.sub._.sub.MID has its first terminal connected to the first terminal of the switch SW20. The second terminal of the switch SW20 is connected to the first terminal of the feed-forward capacitor CFF.sub.1. The output of the feed-forward amplifier 122 is connected to the first terminal of the switch SW21. The second terminal of the switch SW21 is connected to the first terminal of the feed-forward capacitor CFF.sub.1. The first terminal of the switch SW22 is connected to the output of the feed-forward amplifier 122. The first terminal of the voltage source 180 is connected to the first terminal of the switch SW30. The second terminal of the voltage source 180 is connected to the ground reference voltage source. The second terminals of the switches as SW22, SW30, and SW31 are connected to the first terminal of the capacitor CFF.sub.2. The second terminals of the capacitor CFF.sub.1 and CFF.sub.2 are commonly connected and connected to the output 7 of the control stage circuit 105 for transfer of the difference output voltage V.sub.DIF to the power stage 10 of FIG. 1a.

    [0075] The select line 112a is connected to the control terminals of the switches SW21, SW22, SW30, and SW31 for selecting which of the capacitors Cff.sub.1 and Cff.sub.2, are connected to the feed-forward amplifier 122 and which of the voltage sources 175a and 175b are connected to the capacitors Cff.sub.1 and Cff.sub.2. The two capacitors Cff.sub.1 and Cff.sub.2 indicate that there are two segments for increasing the input range of the control stage circuit 105 of FIG. 3.

    [0076] FIGS. 7a and 7b are plots of the output voltage versus time of the feed-forward compensator circuit 120 of the control stage circuit 105 of the switch mode DC/DC power converter of the present disclosure. Prior to the occurrence of the large positive transient voltage at the time τ.sub.0, the differential input of the error amplifier 115 is small and the feed-forward capacitor Cff.sub.2 is connected to the output of the feed-forward amplifier 122 through the switch SW22. The switch SW20 is activated to connect the mid-level voltage source 175a with first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.C1 is thus set to the voltage level V.sub.FF.sub._.sub.MID of the mid-level voltage source 175a. The voltage level V.sub.FF.sub._.sub.MID of the mid-level voltage source 175a is equal to the amplitude of the output of the feed-forward amplifier 122 when the difference in amplitude between the feedback signal V.sub.FB and the reference voltage V.sub.REF is zero (0).

    [0077] In FIG. 7a, the control loop monitor 100 detects that a large positive transient has occurred at the output of the switch mode DC/DC power converter at the time τ.sub.1. The switch SW22 is deactivated and the switch SW30 is activated to connect the first terminal of the maximum level voltage source 175b to the first terminal of the feed-forward capacitor Cff.sub.2. The voltage level V.sub.ff.sub._.sub.MAX of the maximum level voltage source 175b is the maximum amplitude of the output of the feed-forward amplifier 122. The switch SW20 is deactivated and the switch SW21 is activated to connect the output of the feed-forward amplifier 122 to the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP of the compensator 120 starts to rise toward the maximum voltage of the output of the feed-forward amplifier 122, when the control loop monitor 100 detects that a large positive transient at the time τ.sub.1. The voltage level V.sub.COMP then falls to the level of the voltage level V.sub.C1 at the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP then rises to the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2 that is set to the voltage level V.sub.ff.sub._.sub.MAX of the maximum level voltage source 175b.

    [0078] In FIG. 7b, the control loop monitor 100 detects that a large negative transient has occurred at the output of the switch mode DC/DC power converter at the time τ.sub.1. The switch SW22 is deactivated and the switch SW31 is activated to connect the ground reference voltage source to the first terminal of the feed-forward capacitor Cff.sub.2. The ground reference voltage source is the minimum amplitude of the output of the feed-forward amplifier 122. The switch SW20 is deactivated and the switch SW21 is activated to connect the output of the feed-forward amplifier 122 to the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP of the compensator 120 starts to fall toward the ground reference voltage source, when the control loop monitor 100 detects that the large negative transient at the time τ.sub.1. The voltage level V.sub.COMP then rises to the level of the voltage level V.sub.C1 at the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP then falls to the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2 that is set to the voltage level V.sub.ff.sub._.sub.MIN or the voltage level of the ground reference voltage source. The segmentation minimizes the disturbances caused by transients to the error amplifier output by transients to the feedback signal V.sub.FB is minimized with the segment transitions.

    [0079] FIG. 8 is a plot of the behaviour of the control stage circuit of the present disclosure of FIG. 3. Prior to the time τ.sub.0, the output of the feed-forward amplifier 122 and the output of the transconductance amplifier 117 are set to the voltage level V.sub.FF.sub._.sub.MID. At the time τ.sub.0, the feedback signal V.sub.FB begins to decrease from being essentially equal to the value of the reference voltage V.sub.REF. The output signal V.sub.COMP from the output of the compensator circuit 120 begins to rise relatively rapidly. The corrected output signal V.sub.OEA from the output of the error amplifier 115 begins to rise much more slowly. The two signals are combined at the output of the control stage circuit 105 to generate the difference output circuit V.sub.DIF. At the time τ.sub.1, the feedback signal V.sub.FB exceeds the negative voltage boundary V.sub.OFF2. The control loop monitor 100 activates the select line 112a to initiate the adjustable offset voltage source 114 and connect the output voltage of the feed-forward amplifier to the first terminal of the feed-forward capacitor Cff.sub.1 where the voltage is mid-level V.sub.FF.sub._.sub.MID, thus setting the output signal V.sub.COMP to the voltage level V.sub.FF.sub._.sub.MID. The output voltage of the compensator circuit 120 begins to rise until the time τ.sub.2. At the time τ.sub.2, the feedback signal V.sub.FB stops decreasing and starts increasing and the output voltage of the compensator circuit 120 begins to fall until the time τ.sub.3. At the time τ.sub.3, the feedback signal V.sub.FB exceeds the positive voltage boundary V.sub.OFF1. The control loop monitor 100 deactivates the select line 112a to remove the offset voltage and connect the output voltage of the feed-forward amplifier to the first terminal of the feed-forward capacitor Cff.sub.2 where the voltage is maximum level V.sub.FF.sub._.sub.MAX, thus setting the output signal V.sub.COMP to the voltage level V.sub.FF.sub._.sub.MAX. The output voltage of the compensator circuit V.sub.COMP fall to approximately the voltage level V.sub.FF.sub._.sub.MID when the feedback signal V.sub.FB the value of the reference voltage V.sub.REF. The output voltage V.sub.DIF of the control stage circuit 105 is the additive combination of the output voltage V.sub.COMP of the compensator and the output voltage V.sub.OEA of the error amplifier 115. Without the second segment of the voltage compensation, the output of the control stage circuit 105 would have had a lower voltage level V.sub.DIF. This minimizes the disturbance to the output of the error amplifier 120 by segment transitions.

    [0080] FIG. 9 is a set of plots of the effects of a load transient (1 mA to 0.8 A) to the switch mode DC/DC power converter of FIG. 1a with and without the control stage circuit of the present disclosure of FIG. 3. The first set of plots 320 illustrates the output voltage V.sub.OUT of the switch mode DC/DC power converter FIG. 1a. The prior art plot 300a employs the control stage circuit of FIG. 1b and has the largest disturbance of the output voltage V.sub.OUT. The plot 305a is of the switch mode DC/DC power converter the control stage circuit of the related patent application included herein by reference. The amplitude of the transient disturbance of the output voltage V.sub.OUT is less than the transient disturbance of the output voltage V.sub.OUT of the prior art shown in the plot 300a. The plot 310a is of the switch mode DC/DC power converter that employs the control stage circuit of the present disclosure of FIG. 3. The amplitude of the transient disturbance of the output voltage V.sub.OUT is less than the transient disturbance of the output voltage V.sub.OUT of the prior art shown in the plot 300a and the output voltage V.sub.OUT of the related patent application.

    [0081] The second set of plots 325 illustrates the inductor current I.sub.L of the switch mode DC/DC power converter FIG. 1a. The prior art plot 300b employs the control stage circuit of FIG. 1b and has the largest disturbance of the inductor current I.sub.L. The plot 305b is of the switch mode DC/DC power converter the control stage circuit of the related patent application included herein by reference. The amplitude of the transient disturbance of the inductor current I.sub.L is less than the transient disturbance of the inductor current I.sub.L of the prior art shown in the plot 300b. The plot 310b is of the switch mode DC/DC power converter that employs the control stage circuit of the present disclosure of FIG. 3. The amplitude of the transient disturbance of the inductor current I.sub.L is less than the transient disturbance of the inductor current I.sub.L of the prior art shown in the plot 300b and the inductor current I.sub.L of the related patent application shown in the plot 305b.

    [0082] The third set of plots 330 illustrates the output voltage V.sub.DIF of the control stage circuit 105 of FIG. 3 of the switch mode DC/DC power converter FIG. 1a. The prior art plot 300c employs the control stage circuit of FIG. 1b and has the largest disturbance of the output voltage V.sub.DIF. The plot 305c is of the switch mode DC/DC power converter the control stage circuit of the related patent application included herein by reference. The amplitude of the transient disturbance of the output voltage V.sub.DIF is less than the transient disturbance of the output voltage V.sub.DIF of the prior art shown in the plot 300b. The plot 310c is of the switch mode DC/DC power converter that employs the control stage circuit 105 of the present disclosure of FIG. 3. The amplitude of the transient disturbance of the output voltage V.sub.DIF is less than the transient disturbance of the output voltage V.sub.DIF of the prior art shown in the plot 300c and the output voltage V.sub.DIF of the related patent application shown in the plot 305c.

    [0083] Referring to FIG. 3, a method for improving the large signal response of control stage circuit 105 of a switch mode DC/DC power converter by increasing the differential input range of the error amplifier 115 of the control stage circuit 105 by segmenting and adding an offset to the error amplifier 115 input and output by adjusting the offset voltage source 114. The control stage circuit 105 includes monitoring the control loop 100 of the switch mode DC/DC power converter to determine a difference between a feedback voltage V.sub.FB developed from the output voltage V.sub.OUT of the switch mode DC/DC power converter and a reference voltage V.sub.REF. From the difference of the difference between a feedback voltage V.sub.FB and the reference voltage V.sub.REF, determining that a transient has occurred at the input terminal or output terminal of the switch mode DC/DC power converter. The feedback voltage V.sub.FB is offset in multiple segments by multiple offset voltages to prevent saturation of the control stage circuit 105 when a large transient signal is received. Counteracting offset voltages are added by the offset current source 119 to an output of an error amplifier 115 of the control stage circuit 105 for maintaining the output voltage V.sub.oEA of the error amplifier 115 to prevent overshoot or undershoot. A feed-forward compensation signal V.sub.COMP is generated with the amplitude of the signal being clamped to at least one fixed voltage level between a minimum and a maximum amplitude of the feed-forward compensation signal V.sub.COMP. The feed-forward compensation signal V.sub.COMP is added to the output V.sub.OEA of the error amplifier 115 to produce an output error signal V.sub.DIF of the control stage circuit 105 for controlling the modulating of the input power voltage of the switch mode DC/DC power converter.

    [0084] FIG. 10 is a flowchart of a method for operating a switch mode DC/DC power converter of the present disclosure for improving the large signal response of the error amplifier 115 within a control stage 105 of the switch mode DC/DC power converter. Referring to FIGS. 3 and 10, the control loop monitor 100 monitors (Box 400) a feedback signal V.sub.FB and generates transient detection signals. The transient detection signals are examined (Box 405) to determine if a positive load transient and/or a negative line transient has occurred.

    [0085] If the control loop monitor 100 detects that a positive load transient and/or a negative line transient has occurred, a positive offset voltage V.sub.ADJ is added (Box 410) to the feedback signal V.sub.FB by activating the offset voltage generator 114 and the offset current I.sub.OFF from the current source 119. The voltage level V.sub.COMP then falls (Box 415) to the level of the voltage level V.sub.C1 at the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP then rises to the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2 that is set to the voltage level V.sub.ff.sub._.sub.MAX of the maximum level voltage source 175b.

    [0086] The control loop monitor 100 compares (Box 420) the feedback signal V.sub.FB with the first offset voltage V.sub.OFF1 from the first offset voltage source 102. If the feedback signal V.sub.FB is not greater than the first offset voltage V.sub.OFF1, the comparison (Box 420) continues until the feedback signal V.sub.FB is greater than the first offset voltage V.sub.OFF1. When the feedback signal V.sub.FB is greater than the first offset voltage V.sub.OFF1, the positive offset voltage V.sub.ADJ is removed from the feedback signal V.sub.FB by deactivating the offset voltage generator 114 and the offset current I.sub.OFF removed by deactivating the current source 119. The voltage level V.sub.COMP then raises from the level of the voltage level V.sub.C1 at the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP then falls to the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2 that is set to the voltage level V.sub.ff.sub._.sub.MID′ of the middle level voltage source 175a.

    [0087] The control loop monitor 100 monitors (Box 400) the feedback signal V.sub.FB and to detect transient signals. If the control loop monitor 100 does not detect that a positive load transient and/or a negative line transient has occurred, the transient detection signals are examined (Box 435) to determine if a negative load transient and/or a positive line transient has occurred. If the control loop monitor 100 detects that a negative load transient and/or a positive line transient has occurred, a negative offset voltage V.sub.ADJ is added (Box 440) to the feedback signal V.sub.FB by activating the offset voltage generator 114 and the offset current I.sub.OFF from the current source 119. The voltage level V.sub.COMP then raises (Box 445) to the level of the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2. The voltage level V.sub.COMP then falls to the voltage level V.sub.C1 at the first terminal of the feed-forward capacitor Cff.sub.1 that is set to the voltage level V.sub.ff.sub._.sub.MIN′ of the minimum level voltage source 175a.

    [0088] The control loop monitor 100 compares (Box 450) the feedback signal V.sub.FB with the second offset voltage V.sub.OFF2 from the second offset voltage source 104. If the feedback signal V.sub.FB is not greater than the first offset voltage V.sub.OFF1, the comparison (Box 420) continues until the feedback signal V.sub.FB is greater than the second offset voltage V.sub.OFF2. When the feedback signal V.sub.FB is greater than the second offset voltage V.sub.OFF2, the negative offset voltage V.sub.ADJ is removed from the feedback signal V.sub.FB by deactivating the offset voltage generator 114 and the offset current I.sub.OFF removed by deactivating the current source 119. The voltage level V.sub.COMP then falls from the level of the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.1. The voltage level V.sub.COMP then raises to the voltage level V.sub.C2 at the first terminal of the feed-forward capacitor Cff.sub.2 that is set to the voltage level V.sub.ff.sub._.sub.MID′ of the middle level voltage source 175a. The control loop monitor 100 then resumes monitoring (Box 400) the feedback signal V.sub.FB and to detect transient signals.

    [0089] While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.