Variation-Tolerant Voltage Reference

Abstract

A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from −40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.

Claims

1. A voltage reference circuit, comprising: a first metal-oxide semiconductor field-effect transistor (MOSFET) having a source terminal, a drain terminal, a gate terminal and a body terminal, where the gate terminal of the first MOSFET is coupled to the source terminal of the first MOSFET and the body terminal of the first MOSFET is biased with a voltage that is different than the voltage at the source terminal and the voltage at the drain terminal; and a second MOSFET having same type of charge carrier as the first MOSFET and configured in a stacked arrangement with the first MOSFET such that a reference voltage is generated at a node interconnecting the first MOSFET to the second MOSFET, where threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and the gate terminal of the second MOSFET is coupled to the drain terminal of the second MOSFET.

2. The voltage reference circuit of claim 1 wherein the first MOSFET is forward biased and the second MOSFET is an off state.

3. The voltage reference circuit of claim 1 wherein one of the source terminal and the drain terminal of the first MOSFET is coupled to a first supply voltage, and the other of the source terminal and the drain terminal of the first MOSFET is coupled to one of the source terminal and the drain terminal of the second MOSFET, and the other of the source terminal and the drain terminal of the second MOSFET is coupled to a second supply voltage, such that the first supply voltage is greater than the second supply voltage.

4. The voltage reference circuit of claim 1 wherein the first MOSFET and the second MOSFET are p-type such that the drain terminal of the first MOSFET is electrically coupled at the node to the source terminal of the second MOSFET.

5. The voltage reference circuit of claim 1 wherein the first MOSFET and the second MOSFET are n-type such that the source terminal of the first MOSFET is electrically coupled at the node to the drain terminal of the second MOSFET.

6. The voltage reference circuit of claim 1 further comprises a bias circuit comprised of transistors only having same type of charge carrier as the first MOSFET and configured to output the voltage that biases the body terminal of the first MOSFET.

7. The voltage reference circuit of claim 6 wherein the bias circuit includes a third MOSFET in a stacked arrangement with a fourth MOSFET, such that a drain terminal of the third MOSFET is electrically coupled at an output node to a source terminal of the fourth MOSFET.

8. The voltage reference circuit of claim 2 wherein the voltage that biases the body terminal of the first MOSFET is different that the first supply voltage and the second supply voltage.

9. A voltage reference circuit, comprising: a first metal-oxide semiconductor field-effect transistor (MOSFET) having a source terminal, a drain terminal, a gate terminal and a body terminal, where the gate terminal of the first MOSFET is coupled to the source terminal of the first MOSFET; a second MOSFET having same type of charge carrier as the first MOSFET and configured in a stacked arrangement with the first MOSFET such that a reference voltage is generated at a node interconnecting the first MOSFET to the second MOSFET, wherein threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and the gate terminal of the second MOSFET is coupled to the drain terminal of the second MOSFET; and a bias circuit configured to bias the body terminal of the first MOSFET with a bias voltage that changes with temperature changes so that the reference voltage is temperature independent.

10. The voltage reference circuit of claim 9 wherein the first MOSFET is forward biased and the second MOSFET is an off state.

11. The voltage reference circuit of claim 9 wherein the bias voltage changes linearly with changes in temperature.

12. The voltage reference circuit of claim 9 wherein one of the source terminal and the drain terminal of the first MOSFET is coupled to a first supply voltage, and the other of the source terminal and the drain terminal of the first MOSFET is coupled to one of the source terminal and the drain terminal of the second MOSFET, and the other of the source terminal and the drain terminal of the second MOSFET is coupled to a second supply voltage, such that the first supply voltage is greater than the second supply voltage.

13. The voltage reference circuit of claim 9 wherein the first MOSFET and the second MOSFET are p-type such that the drain terminal of the first MOSFET is electrically coupled at the node to the source terminal of the second MOSFET.

14. The voltage reference circuit of claim 9 wherein the first MOSFET and the second MOSFET are n-type such that the source terminal of the first MOSFET is electrically coupled at the node to the drain terminal of the second MOSFET.

15. The voltage reference circuit of claim 9 wherein the bias circuit is comprised of transistors only having same type of charge carrier as the first MOSFET.

16. The voltage reference circuit of claim 9 wherein the bias circuit includes a third MOSFET in a stacked arrangement with a fourth MOSFET, such that a drain terminal of the third MOSFET is electrically coupled at an output node to a source terminal of the fourth MOSFET.

17. The voltage reference circuit of claim 12 wherein the voltage that biases the body terminal of the first MOSFET is different that the first supply voltage and the second supply voltage.

Description

DRAWINGS

[0013] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0014] FIG. 1 shows a simplified circuit of proposed voltage reference circuit;

[0015] FIG. 2 is a graph showing how V.sub.body tracks V.sub.dd change and creates constant V.sub.BS for the first MOSFET;

[0016] FIG. 3 is a schematic of the proposed voltage reference circuit with stacked PMOS diodes;

[0017] FIG. 4 is a schematic of a variant of the voltage reference circuit implemented with n-type transistors;

[0018] FIG. 5 is a graph showing a comparison of V.sub.ref simulation at all corners among the proposed design;

[0019] FIG. 6 is a graph showing the measured V.sub.ref across temperature for 3 wafers in 3 different corners;

[0020] FIG. 7 is a graph showing the distribution of V.sub.ref on three different wafers;

[0021] FIG. 8 is a graph showing the measured line sensitivity;

[0022] FIG. 9 is a graph showing the measured temperature coefficients at different V.sub.dd; and

[0023] FIG. 10 is a graph showing the measured PSRR; and

[0024] FIGS. 11A and 11B are graphs showing the measured power across V.sub.dd and temperature, respectively.

[0025] Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0027] FIG. 1 shows a simplified structure of the proposed voltage reference circuit 10. The proposed voltage reference circuit is comprised of two metal-oxide semiconductor field-effect transistors (MOSFETs) M1, M2 in a stacked arrangement and a bias circuit 12. In the stacked arrangement, the two MOSFETs M1, M2 are configured with one of the source terminal and the drain terminal of the first MOSFET M1 coupled to a first supply voltage VDD, and the other of the source terminal and the drain terminal of the first MOSFET is coupled to one of the source terminal and the drain terminal of the second MOSFET M2. The other of the source terminal and the drain terminal of the second MOSFET M2 is coupled to a second supply voltage (e.g., ground). The first MOSFET M1 and the second MOSFET M2 have the same type of charge carrier and the particular terminal connections will depend upon the type of charge carrier as further described below.

[0028] Additionally, the gate terminal of the first MOSFET M1 is coupled to the source terminal of the first MOSFET M1 and the gate terminal of the second MOSFET M2 is coupled to the drain terminal of the second MOSFET M2. Of note, the body terminal of the first MOSFET M1 is biased with a voltage that is different than the voltage at either the source terminal or the drain terminal of the first MOSFET M1. It is also noted that the threshold voltage V.sub.th1 of the first MOSFET M1 and threshold voltage V.sub.th2 of the second MOSFET M2 are designed and manufactured to be the same.

[0029] In a first example embodiment, the first MOSFET M1 and second MOSFET M2 are p-type as seen in FIG. 1. In the stacked arrangement, source terminal of the first MOSFET M1 is electrically coupled to the upper supply voltage (V.sub.dd) while the drain terminal of the first MOSFET M1 is electrically coupled to the source terminal of the second MOSFET M2 and the drain terminal of the second MOSFET M2 is electrically coupled to the lower supply voltage (e.g., ground). The reference voltage V.sub.ref is generated at an output node interconnecting the first MOSFET M1 to the second MOSFET M2.

[0030] In operation, the first MOSFET M1 is forward-biased and provides sub-threshold current flowing through the second MOSFET (i.e., bottom PMOS diode) M2. The second MOSFET M2 is in an off state. The current equations of M1 and M2 are expressed as in equation (1). By solving equation (1), V.sub.ref can be expressed as equation (3). As M1 and M2 are the same type of charge carrier (i.e, PMOS), the difference between V.sub.th1 and V.sub.th2 comes solely from the body bias effect of M1. Random V.sub.th mismatch is kept negligible by upsizing (e.g., >20 μm.sup.2) of all 4 devices in this reference circuit.

[00001]$\begin{array}{c}.Math.\left(1\right).Math..Math.I_R=u_p.Math.C_{\mathrm{ox}}.Math.\frac{W_1}{L_1}.Math.{\mathrm{nV}}_T^2.Math.\exp \left(\frac{0-V_{\mathrm{th}.Math..Math.1}}{{\mathrm{mV}}_T}\right)=u_p.Math.C_{\mathrm{ox}}.Math.\frac{W_2}{L_2}.Math.{\mathrm{nV}}_T^2.Math.\exp \left(\frac{0-V_{\mathrm{ref}}-V_{\mathrm{th}.Math..Math.2}}{{\mathrm{mV}}_T}\right).Math..Math..Math.\left(2\right)\\ I_L=u_p.Math.C_{\mathrm{ox}}.Math.\frac{W_3}{L_3}.Math.{\mathrm{nV}}_T^2.Math.\exp \left(\frac{V_{\mathrm{body}}-V_{\mathrm{dd}}-V_{\mathrm{th}.Math..Math.3}}{{\mathrm{mV}}_T}\right)=u_p.Math.C_{\mathrm{ox}}.Math.\frac{W_4}{L_4}.Math.{\mathrm{nV}}_T^2.Math.\exp \left(\frac{0-V_{\mathrm{th}.Math..Math.4}}{{\mathrm{mV}}_T}\right)\\ \begin{array}{cc}{V}_{\mathrm{ref}}=.Math.V_{\mathrm{th}.Math..Math.1}-V_{\mathrm{th}.Math..Math.2}+{\mathrm{mV}}_T.Math.\ln .Math.\frac{W_1.Math.L_2}{W_2.Math.L_1}& \mathrm{ }.Math.\left(3\right)\\ =.Math.\gamma \left(\sqrt{2.Math.{\phi }_b-{\mathrm{mV}}_T.Math.\ln .Math.\frac{W_4.Math.L_3}{W_3.Math.L_4}}-\sqrt{2.Math.{\phi }_b}\right)+{\mathrm{mV}}_T.Math.\ln .Math.\frac{W_1.Math.L_2}{W_2.Math.L_1}& .Math.\left(4\right)\end{array}\end{array}$

[0031] The bias circuit 12 is configured to output the voltage that biases the body terminal of the first MOSFET M1. In the example embodiment, the bias circuit 12 is comprised of transistors having the same type of charge carrier as the first MOSFET M1 and the second MOSFET M2. That is, the third MOSFET M3 and the fourth MOSFET M4 are p-type as well. More specifically, the third MOSFET M3 and the fourth MOSFET M4 are in a stacked arrangement, such that the drain terminal of the third MOSFET M3 is electrically coupled at a bias node to the source terminal of the fourth MOSFET M4. The bias node is also electrically coupled to the body terminal of the first MOSFET to supply the bias voltage thereto.

[0032] In operation, the third MOSFET M3 and the fourth MOSFET M4 generate the required body bias for first MOSFET M1. More specifically, the fourth MOSFET M4 is an off-state PMOS; whereas, the third MOSFET is a PMOS diode. The current equations of M3 and M4 are expressed above in equation (2). As the third MOSFET and the fourth MOSFET M3 and M4 are also the same type of PMOS, V.sub.th3 and V.sub.th4 are essentially identical. The combination of the third MOSFET M3 and the fourth MOSFET M4 provides a body-bias voltage V.sub.body that tracks V.sub.dd and creates a constant V.sub.BS (V.sub.body−V.sub.dd) for first MOSFET M1 as shown in FIG. 2. If the current through third MOSFET M3 (I.sub.L) is much larger than the parasitic diode current (I.sub.dio) from the source to the N-well of M1, V.sub.ref can be expressed by equation (4). The left term of Equation (4) is complementary to temperature; whereas, the right term is proportional to temperature. With proper sizing of the four transistors, the first-order temperature dependency can be cancelled out. That is, the bias is circuit can be configured to bias the body terminal of the first MOSFET with a bias voltage that changes with temperature changes so that the reference voltage is temperature independent. Moreover, the threshold voltage V.sub.th does not play a role in equation (4) because each pair (M1/M2 and M3/M4) uses the same type of PMOS, thus significantly reducing process variation. Since I.sub.dio is not well modeled, I.sub.L is designed to be three orders of magnitude larger than I.sub.dio to minimize the effect of I.sub.dio. Proper sizing of these transistors can be determined using a global optimization tool.

[0033] Variants of this proposed design are contemplated by this disclosure. Referring to FIG. 3, two or more stacked diodes can replace the second MOSFET M2 and the third MOSFET M3 to generate a higher reference voltage. Multiple voltage reference levels can be generated in this manner. In FIG. 3, three stages of PMOS diodes are used in the design to realize an approximately 1V output reference voltage. MIM capacitors C0 and C1 (both set to 1.78 pF) are used to isolate the reference voltage from high-frequency power supply noise. Except with respect to the differences discussed herein, the voltage reference circuit 30 may be substantially the same voltage reference circuit 10 described above.

[0034] FIG. 4 depicts a variant of the voltage reference circuit 40 employing n-type transistors. In this variant, the drain terminal of the first MOSFET M1 is electrically coupled to the upper supply voltage while the source terminal of the first MOSFET M1 is electrically coupled to the drain terminal of the second MOSFET M2. The source terminal of the second MOSFET M2 is electrically coupled to the lower supply voltage, where magnitude of the upper supply voltage is larger than the lower supply voltage. Except with respect to the differences discussed herein, the voltage reference circuit 40 may be substantially the same voltage reference circuit 10 described above.

[0035] With continued reference to the voltage reference circuit 10 in FIG. 1, FIG. 5 compares simulated reference voltage distributions across corners for the proposed reference circuit 10 to designs presented by M. Seok et al. in JSSC, 2012 [3] and by I. Lee et al. in VLSI, 2014 [4]. The proposed design achieves <4% inaccuracy across all corners; whereas, the other designs vary up to 10% and 19%, respectively.

[0036] For verification, sixty chips from 3 different wafers in 180 nm CMOS were tested. One wafer was in a typical corner with thin top-metal, another was found to be at a slow corner with ultra-thick top-metal, and the third was at a fast corner with ultra-thick top-metal. All measurements are reported without trimming.

[0037] FIG. 6 shows the measured reference voltage across temperature for all 60 chips. From −40° C. to 85° C., the temperature coefficient of the typical wafer ranges from 48 ppm/° C. to 104 ppm/° C., and those of the fast and slow wafers are 55.2-124 ppm/° C. and 56.1-117 ppm/° C., respectively. The reference voltage distributions at 25° C. of the 3 different wafers are shown in FIG. 7. Without trimming, the typical wafer shows a mean value of 986.2 mV and standard deviation of 2.6 mV. The average voltage difference between the fast and slow wafers is 3.6% (1.9% σ/μ), matching simulation and providing sufficient accuracy for many key circuit applications within nW systems.

[0038] FIG. 8 shows the measured sensitivity of reference voltage to power supply voltage. Line sensitivity is 0.38% N from 1.2V to 2.2V. FIG. 9 shows the measured temperature coefficients at different supply voltages. FIG. 10 shows the measured power supply rejection ratio (PSRR) from 10 Hz to 10 MHz. High-frequency PSRR is −56 dB, which can be further improved with larger loading caps C0 and C1.

[0039] FIGS. 11A and 11B show the measured power consumption across supply voltage and temperature, respectively. The output reference voltage is approximately 1V with 3 stages of stacked PMOS diodes. The power supply can be reduced to 1.2V while maintaining this approximately 1V reference voltage. To lower the minimum power supply, fewer stages of PMOS diodes can be used, but the output reference voltage will be lowered as well. At 25° C. and 1.2V, the power consumption is 114 pW, which is suitable for low-power sensor and IoT applications.

[0040] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.