GALVANICALLY ISOLATED DC-DC CONVERTER WITH BIDIRECTIONAL DATA TRANSMISSION

Abstract

A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.

Claims

1. A galvanic isolation system, comprising: a first galvanically isolated link configured to transfer power from a first circuit to a second circuit across a galvanic barrier; and a second galvanically isolated link comprising a first transformer, wherein the first transformer is configured to feed back an error signal from the second circuit to the first circuit across the galvanic barrier for use in regulating the power transfer and wherein the first transformer is further configured to support bidirectional data communication between the first and second circuits across the galvanic barrier.

2. The system of claim 1, wherein the first galvanically isolated link comprises: a first oscillator of the first circuit; and a second transformer having a primary winding coupled to outputs of the first oscillator and a secondary winding coupled to the second circuit.

3. The system of claim 2, wherein the second circuit comprises a rectifier circuit coupled to the secondary winding of the second transformer and configured to convert the power transfer to a DC output voltage.

4. The system of claim 3, wherein the second circuit further comprises an error amplifier configured to determine a difference between the DC output voltage and a reference voltage and generate said error signal in response thereto.

5. The system of claim 4, wherein said second galvanically isolated link comprises: a second oscillator of the second circuit configured for operation responsive to said error signal; wherein said first transformer has a primary winding coupled to outputs of the second oscillator and a secondary winding coupled to the first circuit.

6. The system of claim 5, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator.

7. The system of claim 6, wherein the first circuit comprises: a detector circuit coupled to the secondary winding of the first transformer and configured to detect said peak amplitude and to generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.

8. The system of claim 7, wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.

9. The system of claim 5, wherein the first circuit comprises: a detector circuit coupled to the secondary winding of the first transformer and configured to detect said error signal and generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.

10. The system of claim 9, wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.

11. The system of claim 5, further comprising: a data modulator circuit having outputs coupled to the primary winding of the first transformer, wherein said data modulator modulates data onto a signal at the primary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the secondary winding of the first transformer, wherein said data demodulator demodulates the data from a signal at the secondary winding of the first transformer.

12. The system of claim 11, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.

13. The system of claim 5, further comprising: a data modulator circuit having outputs coupled to the secondary winding of the first transformer, wherein said data modulator modulates data onto a signal at the secondary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the primary winding of the first transformer, wherein said data demodulator demodulates the data from a signal at the primary winding of the first transformer.

14. The system of claim 13, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.

15. The system of claim 2, wherein said second galvanically isolated link comprises: a second oscillator of the second circuit configured for operation responsive to said error signal; wherein said first transformer has a primary winding coupled to outputs of the second oscillator and a secondary winding coupled to the first circuit.

16. The system of claim 15, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator.

17. The system of claim 15, wherein the first circuit comprises: a detector circuit coupled to the secondary winding of the first transformer and configured to detect said error signal and generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.

18. The system of claim 17, wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the first oscillator.

19. The system of claim 15, further comprising: a data modulator circuit having outputs coupled to the primary winding of the first transformer, wherein said data modulator modulates data onto a signal at the primary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the secondary winding of the first transformer, wherein said data demodulator demodulates the data from a signal at the secondary winding of the first transformer.

20. The system of claim 19, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.

21. The system of claim 15, further comprising: a data modulator circuit having outputs coupled to the secondary winding of the first transformer, wherein said data modulator modulates data onto a signal at the secondary winding of the first transformer for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the primary winding of the first transformer, wherein said data demodulator demodulates the data from a signal at the primary winding of the first transformer.

22. The system of claim 21, wherein said error signal changes a peak amplitude of an oscillator signal generated by said second oscillator at the primary winding of the first transformer.

23. The system of claim 1, wherein said first galvanically isolated link comprises a power very high frequency (VHF) oscillator circuit and said second galvanically isolated link comprises a radio frequency (RF) oscillator circuit.

24. The system of claim 23, wherein the first circuit comprises a first control circuit configured to control on and off actuation of the power VHF oscillator circuit in response to the error signal, and wherein the second circuit comprises a second control circuit configured to control a peak amplitude of the RF oscillator circuit to communicate the error signal across the galvanic barrier.

25. The system of claim 24, further comprising: a data modulator circuit having outputs coupled to the RF oscillator circuit on a second circuit side of the galvanic barrier, wherein said data modulator modulates data onto a signal at the second circuit side for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the RF oscillator circuit on a first circuit side of the galvanic barrier, wherein said data demodulator demodulates the data from a signal at the first circuit side.

26. The system of claim 24, further comprising: a data modulator circuit having outputs coupled to the RF oscillator circuit on a first circuit side of the galvanic barrier, wherein said data modulator modulates data onto a signal at the first circuit side for communication across the galvanic barrier; and a data demodulator circuit having inputs coupled to the RF oscillator circuit on a second circuit side of the galvanic barrier, wherein said data demodulator demodulates the data from a signal at the second circuit side.

27. The system of claim 1, wherein the first circuit and the first and first transformers are provided on a first integrated circuit chip and the second circuit is provided on a second integrated circuit chip, and further including bonding wires configured for electrically connecting the first and second integrated circuit chips.

28. A galvanic isolation system, comprising: a first galvanically isolated link configured to transfer power from a first circuit to a second circuit across a galvanic barrier; and a second galvanically isolated link configured to feed back an error signal from the second circuit to the first circuit across the galvanic barrier for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic barrier, said second galvanically isolated link comprising: a first oscillator of the second circuit providing a radio frequency (RF) control signal modulated by said error signal; a first transformer having a primary winding coupled to outputs of said first oscillator and a secondary winding coupled to the first circuit; at least one first electronic switch coupled in series with at least one capacitor coupled to the secondary winding of the first transformer and configured to modify an impedance of the secondary winding to modulate the RF control signal with first data communicated from the first circuit to the second circuit; and at least one second electronic switch coupled in series with at least one capacitor coupled to the primary winding of the first transformer and configured to modify an impedance of the primary winding to modulate the said RF control signal with second data communicated from the second circuit to the first circuit.

29. The system of claim 28, wherein the first galvanically isolated link comprises: a second oscillator of the first circuit; and a second transformer having a primary winding coupled to outputs of the first oscillator and a secondary winding coupled to the second circuit.

30. The system of claim 29, wherein the second circuit comprises a rectifier circuit coupled to the secondary winding of the second transformer and configured to convert the power transfer to a DC output voltage.

31. The system of claim 30, wherein the second circuit further comprises an error amplifier configured to determine a difference between the DC output voltage and a reference voltage and generate said error signal in response thereto.

32. The system of claim 31, wherein said error signal changes a peak amplitude of an oscillator signal generated by said first oscillator.

33. The system of claim 32, wherein the first circuit comprises: a detector circuit coupled to the secondary winding of the first transformer and configured to detect said peak amplitude to generate a control signal; and a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.

34. The system of claim 33, wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the second oscillator.

35. The system of claim 28, wherein the primary of the first transformer comprises two end taps and a center tap, the center tap being coupled to a common node of the second circuit.

36. The system of claim 35, wherein the at least one second electronic switch comprises two electronic switches, each electronic switch coupled to an end tap of the primary of the first transformer and coupled through a series capacitor to said common node of the second circuit.

37. The system of claim 36, wherein each electronic switch is controlled separately by the second encoder.

38. The system of claim 28, wherein the secondary of the first transformer comprises two end taps and a center tap, the center tap being coupled to a common node of the first circuit.

39. The system of claim 38, wherein the at least one first electronic switch comprises two electronic switches, each electronic switch coupled to an end tap of the secondary of the first transformer and coupled through a series capacitor to the common node of the first circuit.

40. The system of claim 39, wherein each electronic switch is controlled separately by the first encoder.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0035] FIG. 1 generally illustrates an application for transfer of power and data through a galvanic isolation barrier;

[0036] FIG. 2 illustrates an architecture for an isolated dc-dc converter;

[0037] FIG. 3 is a circuit diagram for an isolated dc-dc converter;

[0038] FIG. 4 illustrates an architecture for a galvanically isolated dc-dc converter with bidirectional data transmission; and

[0039] FIGS. 5-6 are diagrams showing a galvanically isolated dc-dc converter with bidirectional data transmission using an isolated link to transfer power with high efficiency and a feedback link to control the output dc voltage and further support a bidirectional half duplex communication.

DETAILED DESCRIPTION

[0040] Given the state of the art of dc-dc converters with data communication, it is clear that reducing the number of required isolated links would represent an important advance in terms of size and cost. Of course, this has to be implemented without significantly affecting the overall performance of the converter.

[0041] The present disclosure concerns an architecture for a galvanically isolated dc-dc converter with bidirectional data transmission. The architecture adopts an isolated link to transfer power with high efficiency, while a feedback link is used to control the output dc voltage and is further exploited to implement a bidirectional half duplex communication by means of a proper modulation of the control signal (i.e., ASK, FSK, or any other modulation which preserves the peak control signal containing the control information).

[0042] An example architecture for a galvanically isolated dc-dc converter with bidirectional data transmission is shown in FIG. 4. This solution uses one isolated channel for power and data. A first chip (Chip A) includes an oscillator circuit formed by transistors M1, M2, M3 and M4 with primary transformer windings LP1, LP2, LP3 and LP4 of the primary side of the galvanic isolation barrier. Windings LP1 and LP2 are coupled in series at a first node, and windings LP3 and LP4 are coupled in series at a second node. The first and second nodes are shorted to each other. A capacitor network cross-couples the gates and drains of transistors MP1 and MP2, and a resistor network biases the gates of transistors MP1 and MP2. The gates and drains of transistors M3 and M4 are cross-coupled. A first data modulator circuit (for example, of the low speed (LS) amplitude shift keying (ASK) type) is coupled to the source terminals of the transistors M1 and M2. This first data modulator circuit includes an LS encoder (ENC) controlling a switch that selectively shorts across a resistor RM coupling the source terminals of transistors M1 and M2 to a first ground reference terminal. A first data demodulator circuit (for example, of the high speed (HS) ASK type) is coupled to the drain terminals of the transistors M1 and M2. The first data demodulator circuit includes a demodulator and detector (DET) circuit and a clock and data recovery (CDR) circuit. The secondary side of the transformer includes secondary transformer windings LS1 and LS2 coupled in series, with the winding LS1 magnetically coupled to LP1 and LP3 and the winding LS2 magnetically coupled to LP2 and LP4. A second chip (Chip B) includes a rectifier circuit formed by transistors M5, M6, M7 and M8 coupled to nodes Vrect1 and Vrect2 at the terminals of the secondary winding and configured to generate an output voltage Vout from the power transferred across the galvanic isolation. The gates and sources of the transistors M5 and M7 are cross-coupled with the drain nodes tied to a second ground reference, and the transistors M6 and M8 are configured as diode devices coupled to the voltage output node. A second data modulator circuit (for example of the HS ASK type) is coupled to the series coupled secondary windings at nodes Vrect1 and Vrect2. The second data modulator circuit includes an HS encoder (ENC) controlling switches that selectively connect the ends of the series coupled secondary windings LS1 and LS2 at nodes Vrect1 and Vrect2 through capacitors CM1 and CM2 to a second ground reference terminal. A second data demodulator (for example, of the LS ASK type) is also coupled to the series coupled secondary windings at nodes Vrect1 and Vrect2. The second data demodulator circuit includes a demodulator detector (DET) circuit and clock and data recovery (CDR) circuit. Reference is now made to FIG. 5 showing a general implementation of a galvanically isolated dc-dc converter with bidirectional data transmission using an isolated link to transfer power with high efficiency and a feedback link to control the output dc voltage and further support a bidirectional half duplex communication.

[0043] A first integrated circuit chip (Chip A; also referred to as a circuit or interface) includes an oscillator 102 powered from a first supply voltage VDD referenced to a first ground voltage GND1. The output terminals of the oscillator 102 are coupled to the terminals of a primary winding 104 of a first transformer 106. A power very high frequency (VHF) oscillator 100 is formed by the oscillator 102 and first transformer 106. The first transformer 106 further includes a secondary winding 108 whose terminals are coupled to bonding pads of the first chip. The VHF frequency range for the oscillator signal output from the oscillator 100 may, for example, be 100-500 MHz according to the design tradeoff for the building block efficiency (i.e., oscillator, transformer, rectifier).

[0044] The first chip A further includes a second transformer 116 having a center-tapped secondary winding 114 formed by windings 114a and 114b that are series coupled at a node connected to the first ground voltage or V.sub.DD. The second transformer 116 further includes a center-tapped primary winding 118 formed by windings 118a and 118b that are series coupled at a node with the terminals of winding 118 and the center tap node coupled to bonding pads of the first chip.

[0045] The transformers 106 and 116 form the galvanic barrier and support first and second galvanically isolated links, respectively, between the first and second chips.

[0046] A peak detector (PD) circuit 120 is coupled to the terminals of the secondary winding 114. The PD circuit 120 functions to detect the peak voltage of an oscillating signal present at the secondary winding 114. An output signal 122 from the PD circuit 120 indicative of that detected peak voltage is coupled to an input of a pulse width modulation (PWM) control circuit (CTRL) 128. The PWM CTRL circuit 128 includes a further input 132 configured to receive a PWM reference signal in the form of an oscillating square wave signal with a frequency of a few tens of kilohertz to a few hundreds of kilohertz. The PWM CTRL circuit 128 responds to the difference between the output signal 122 and the PWM reference voltage to generate a PWM control signal 134 that is applied to control actuation (on/off) of the oscillator 102.

[0047] The first chip A further includes a low speed (LS) modulator circuit 140 configured to receive a data signal (Data.sub.1,LS) and a clock signal (CK.sub.1,LS). Outputs of the LS modulator circuit 140 are coupled to the terminals of the secondary winding 114 (i.e., coupled to the chip A side of the galvanic barrier for the second galvanically isolated link). A high speed (HS) demodulator circuit 142 includes inputs also coupled to the terminals of the secondary winding 114. The HS demodulator outputs a data signal (Data.sub.O,HS) and a clock signal (CK.sub.O,HS).

[0048] A second integrated circuit chip (Chip B; also referred to as a circuit or interface) includes a rectifier circuit 150 having inputs coupled to bonding pads of the second chip. These bonding pads are coupled by bonding wires 148 to the bonding pads on the first chip associated with the terminals of the secondary winding 108 of the first transformer 106. An output voltage V.sub.DC is generated by the rectifier circuit 150. That output voltage is stored/filtered by an output capacitor 152 coupled to a second ground voltage (GND2).

[0049] A differential amplifier circuit 154 includes a first input coupled to receive the output voltage V.sub.DC and a second input coupled to receive a reference voltage V.sub.REF. The circuit 154 operates to determine a difference between the output voltage V.sub.DC and reference voltage V.sub.REF, and generate a control signal (I.sub.BIAS) in a feedback path. The control signal (I.sub.BIAS) is an error signal indicative of the error between the output voltage V.sub.DC and reference voltage V.sub.REF. This error is fed back to the first chip A for use in controlling PWM actuation of the oscillator 102 to achieve regulation of the output voltage V.sub.DC relative to the reference voltage V.sub.REF by controlling power transfer from chip A to chip B.

[0050] The second chip B further includes an oscillator 160 including first, second and third output terminals coupled to bonding pads of the second chip. These bonding pads are coupled by bonding wires 164 to the bonding pads on the first chip associated with the terminals and center tap node of the primary winding 118 of the second transformer 116.

[0051] A control data RF oscillator 162 is accordingly formed by the oscillator 160 the second transformer 116. This control data radio frequency (RF) oscillator 162 is used to transmit the feedback error across the galvanic isolation to the first chip A with control signal (I.sub.BIAS) causing a peak amplitude variation of the oscillation signal generated by the oscillator 160. The RF frequency range of the oscillator signal output by the oscillator 162 may, for example, be in the order of a few gigahertz.

[0052] The second chip B further includes a high speed (HS) modulator circuit 170 configured to receive a data signal (Data.sub.I,HS) and a clock signal (CK.sub.I,HS). Outputs of the HS modulator circuit 170 are coupled to the first and third terminals of the oscillator 160 and corresponding terminals of the primary winding 118 (i.e., coupled to the chip B side of the galvanic barrier for the second galvanically isolated link). A low speed (LS) demodulator circuit 172 includes inputs also coupled to the terminals of the primary winding 118. The LS demodulator outputs a data signal (Data.sub.O,LS) and a clock signal (CK.sub.O,LS).

[0053] FIG. 6 shows a more detailed implementation of the galvanically isolated dc-dc converter with bidirectional data transmission. FIG. 6 specifically shows the circuitry of the modulators and demodulators for implementation of half-duplex data transmission using amplitude shift keying (ASK) modulation techniques.

[0054] The low speed (LS) modulator circuit 140 includes an encoder (ENC) circuit configured to receive the data signal (Data.sub.I,LS) and clock signal (CK.sub.I,LS). The encoder circuit generates control signals for controlling actuation of switching circuits 144 (such as, for example, transistor switches) that are coupled between the terminals of the secondary winding 114 and the first ground voltage. Capacitors 146 are coupled between the terminals of the secondary winding 114 and switching circuits 144. The LS modulator circuit 140 is accordingly coupled to the chip A side of the galvanic barrier for the second galvanically isolated link.

[0055] The high speed (HS) demodulator circuit 142 includes a demodulation detector (DET) circuit coupled to the terminals of the secondary winding 114. The output of the DET circuit is processed by clock and data recovery (CDR) circuit that outputs a data signal (Data.sub.O,HS) and a clock signal (CK.sub.O,HS). The HS demodulator circuit 142 is accordingly coupled to the chip A side of the galvanic barrier for the second galvanically isolated link.

[0056] The high speed (HS) modulator circuit 170 includes an encoder (ENC) circuit configured to receive the data signal (Data.sub.I,HS) and clock signal (CK.sub.I,HS). The encoder circuit generates control signals for controlling actuation of switching circuits 174 (such as, for example, transistor switches) that are coupled between the first and third terminals of the oscillator 160 (the terminals of the primary winding 114) and the second ground voltage. Capacitors 176 are coupled between the first and third terminals of the oscillator 160 (the terminals of the primary winding 114) and switching circuits 174. The HS modulator circuit 170 is accordingly coupled to the chip B side of the galvanic barrier for the second galvanically isolated link.

[0057] The low speed (LS) demodulator circuit 172 includes a demodulation detector (DET) circuit coupled to the first and third terminals of the oscillator 160 (the terminals of the primary winding 114). The output of the DET circuit is processed by clock and data recovery (CDR) circuit that outputs a data signal (Data.sub.O,LS) and a clock signal (CK.sub.O,LS). The LS demodulator circuit 172 is accordingly coupled to the chip B side of the galvanic barrier for the second galvanically isolated link.

[0058] The galvanically isolated dc-dc converter with bidirectional data transmission as shown in FIGS. 5 and 6 operates as follows. The output voltage V.sub.DC is delivered from the first chip A to second chip B by power transfer across the galvanic barrier using a power link i.e., the first galvanically isolated link) formed by the power VHF oscillator 100 that uses the first (isolation) transformer 106 as a resonant load and the rectifier circuit 150. The output voltage V.sub.DC is controlled in regulation by a feedback signal delivered from second chip B to first chip A across the galvanic barrier using a feedback isolated link (i.e., the second galvanically isolated link) formed by the CTRL RF oscillator 162 that uses the second (isolation) transformer 116 as a resonant load and the peak detector circuit 120. The control information of the feedback signal is generated by the differential amplifier 154 and is contained in the modulated amplitude of the RF control signal generated by the oscillator 160. This amplitude is easily detected by the peak detector circuit to generate the output signal 122 which drives the PWM CTRL circuit 128. The PWM control signal 134 turns the power oscillator 102 on and off with a frequency of a few hundreds of kilohertz, thus implementing a typical PWM modulation to vary the level of power transferred across the galvanic barrier for the first galvanically isolated link at maximum efficiency.

[0059] The feedback isolated link is further exploited to support a half-duplex data communication between chips A and B. By use of a desired modulation (for example, ASK as shown in FIG. 6) of the control signal at each winding of the isolation transformer 116, low speed (LS) data communication from chip A to chip B and high speed (HS) data communication from chip B to chip A may be accomplished by means of impedance mismatch at the transformer windings on one or the other side of the galvanic barrier through capacitors (references 146 and 176) and switch resistances (references 144 and 174). It is important that the adopted modulation (for example, amplitude shift keying ASK) preserve the peak of the RF signal which contains the control information. Typically, the maximum data rate from chip A to chip B is lower than the maximum data rate from chip B to chip A, hence the notations for low speed (LS) and high speed (HS). Each data channel includes a coding block (the encoder ENC) which encodes the data signal, a detector (DET) which demodulates the data signal and a clock/data recovery circuit (CDR). It will be noted that traditional coding schemes such as PWM or Manchester can be used.

[0060] In an embodiment, both isolation transformers 106 and 116 for the power link and the CTR/DATA link, respectively, are built within the first chip A. This can be implemented by the use of a thick oxide technology module as taught by United States Patent Application Publication No. 2015/0364249 (incorporated by reference) for data and power transfer applications. This means that the second chip B can be fabricated in a standard process (i.e., without any thick oxide module).

[0061] As far as the common mode transient (CMT) immunity is concerned, the differential center-tapped CTRL/DATA isolation transformer 116 provides low impedance paths for common mode currents for both transformer windings. Further CMT suppression circuitries can be also included in the demodulator (DET) circuits.

[0062] The architecture of FIGS. 5-6 presents the following advantages with respect known prior art solutions: [0063] a) It increases the level of integration, thus reducing the silicon area and system costs by exploiting the power control isolated channel (already available) to provide also bidirectional data communication: For integrated isolated dc-dc converters the silicon area consumed by the isolation transformers can be as high as 50% of the overall area. [0064] b) It requires similar area with respect to a simple power link with PWM feedback control loop without data communication: It is possible to implement data communication on a traditional isolated dc-dc converter without significantly affecting area or overall efficiency performance. [0065] c) CMT immunity and power efficiency do not require to be traded-off since two different isolation transformers operating at different frequencies (i.e., VHF and RF) are exploited: Since the VHF power link has a dedicated transformer, it can be as large as necessary to optimize both power and efficiency, while CMT immunity is mainly determined by the parasitic primary to secondary winding capacitance of the CTRL/DATA transformer. This transformer is much smaller since is typically operated at RF frequencies and therefore parasitic capacitances are low.

[0066] d) It is suitable to data rate of tens of Mbit/s: The data rate is not limited by the power signal frequency since data communication is implemented on the control link.

[0067] e) The output power can be several hundreds of milliwatts. The level of the delivered output power is not limited by the architecture since it is an almost free design parameter.

[0068] The architecture can be easily applied also to a reinforced isolated system as taught by: “Surging across the barrier: Digital isolators set the standard for reinforced insulation,” Analog Devices, Inc., Tech. article, 2012, MS-2341 (incorporated by reference); Kamath, et al., “High-voltage reinforced isolation: Definitions and test methodologies,” Texas Instruments, Tech. article, November 2014, SLYY063 (incorporated by reference); and Cantrell, “Reinforced isolation in data couplers,” Analog Devices, Inc., Tech. article, 2011, MS-2242 (incorporated by reference). To this aim, both chips A and B use the thick-oxide technology module and series isolation capacitors are added in the power and CTRL/DATA links, while exploiting an LC resonance to minimize losses (as taught by U.S. application patent Ser. No. 15/163,430 filed May 24, 2016, the disclosure of which is incorporated by reference).

[0069] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been disclosed by way of example only, without departing from the extent of protection.

[0070] The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.