APPARATUS FOR MITIGATING NONLINEARITY-INDUCED SPURS AND NOISE IN A FRACTIONAL-N FREQUENCY SYNTHESIZER

Abstract

An apparatus for mitigating nonlinearity-induced spurs and noise in a fractional-N frequency synthesizer

A digital delta-sigma modulator (DDSM) is disclosed with an input signal x[n], an output signal y[n], a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by

Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z)

wherein Y(z), X(z), D(z) andE(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF (z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form:

[00001]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

where A , Q and K are constants, coefficients c.sub.i are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of

[00002]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

satisfies z.sub.j≠+1 for j=1, 2, . . . , K

Claims

1. A digital delta-sigma modulator (DDSM) with an input signal x[n], an output signal y[n] ,a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by
Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z) wherein Y(z), X(z), D(z) and E (z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF(z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form: $\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ where A , Q and K are constants, coefficients c, are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of $\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ satisfies z.sub.j≠+1 for j=1, 2, . . . , K.

2. The digital delta-sigma modulator of claim 1, wherein the coefficients c.sub.i are equal to −1, 0 or 1.

3. The digital delta-sigma modulator of claim 1, wherein R of the coefficients c.sub.i are equal to −1, (R-1) of the coefficients c, are equal to +1 and the other (K−2R+1) of the coefficients c, are equal to zero, with $R\le \frac{K+1}{2}.$

4. The digital delta-sigma modulator of claim 1 wherein the z-domain equation is implemented with a multi-bit single-quantizer DDSM architecture.

5. The digital delta-sigma modulator of claim 1, wherein the z-domain equation is implemented with a multistage noise shaping cascaded DDSM architecture comprising an error cancellation network and L≥2 error feedback modulator (EFM) stages, wherein an error output e.sub.j of stage j is applied as an input to stage (j+1) and wherein outputs y.sub.j of the L stages are combined in the error cancellation network to provide the output y.

6. The digital delta-sigma modulator of claim 5, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages and the second portion comprises the Lth error feedback modulator stage, wherein the first portion and the error cancellation network implement the noise transfer function
NTF.sub.A(z)=A.sub.Az.sup.−Q.sup.A(1−z.sup.−1).sup.s wherein A.sub.A, Q.sub.A are constants and S is equal to Σ.sub.i=1.sup.L-1s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=A.sub.jz.sup.−Q.sup.i(1−z.sup.−1).sup.s.sup.i where A.sub.i and Q.sub.i are constants with i=1, 2, . . . L−1, and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=A_B{z^{-Q_B}\left(1-z^{-1}\right)}^{\left(1-S\right)}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ wherein A.sub.B, Q.sub.B are constants.

7. The digital delta-sigma modulator of claim 5, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages and the second portion comprises the Lth error feedback modulator stage, wherein the first portion and the error cancellation network implement the noise transfer function $NT{F}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$ wherein S is equal to Σ.sub.i=1.sup.L-1s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=M.sup.−1(1−z.sup.−1).sup.s.sup.i with i=1, 2, . . . L−1, and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{\left(1-S\right)}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

8. The digital delta-sigma modulator of claim 5, wherein L=3.

9. The digital delta-sigma modulator of claim 1, wherein the z-domain equation is implemented with an error cancellation network and a nested cascaded structure comprising a plurality of error feedback modulator (EFM) stages connected in a plurality of levels.

10. The digital delta-sigma modulator of claim 9, wherein the nested cascaded structure comprises T levels of L error feedback modulator (EFM) stages comprising a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level, wherein the first portion and the error cancellation network implement the noise transfer function
NTF.sub.A(z)=A.sub.Az.sup.−Q.sup.A(1−z.sup.−1).sup.s where A.sub.A, Q.sub.A are constants and S is equal to Σ.sub.j=1.sup.L-1s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=A.sub.i,jz.sup.−Q.sup.i,j(1−z.sup.−1).sup.s.sup.j where A.sub.i,j and Q.sub.i,j are constants with i=1, 2, . . . T and j=1, 2, . . . L−1, and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=A_B{z^{-Q_B}\left(1-z^{-1}\right)}^{\left(1-S\right)}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ wherein A.sub.B, Q.sub.B are constants.

11. The digital delta-sigma modulator of claim 9, wherein the nested cascaded structure comprises T levels of L error feedback modulator (EFM) stages comprising a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level, wherein the first portion and the error cancellation network implement the noise transfer function $NT{F}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$ where S is equal to Σ.sub.j=1.sup.L−1s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=M.sub.i.sup.−1(1−z.sup.−1).sup.s.sup.j with i=1, 2, . . . T and j=1, 2, ... L−1, and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{\left(1-S\right)}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

12. The digital delta-sigma modulator of claim 1, wherein the coefficients c.sub.i are valued such that the noise transfer function can be represented in the form: $\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1+\underset{i=1}{\overset{K+1}{.Math.}}{d}_i{z}^{-i}\right)$ wherein coefficients d.sub.i are equal to −1, 0 or 1, and $\underset{i=1}{\overset{K+1}{.Math.}}.Math.d_i.Math.\le -1+2\underset{i=1}{\overset{K}{.Math.}}.Math.c_i.Math.$

13. The digital delta-sigma modulator of claim 12, wherein the coefficients c.sub.i are equal to −1, 0 or 1.

14. A fractional-N PLL device, comprising: a voltage controlled oscillator, a phase-locked loop comprising a multimodulus divider, wherein the phase-locked loop generates an output frequency from the voltage controlled oscillator; and the digital delta-sigma modulator of claim 1 for providing a sequence of integers to control the multimodulus divider to settle to a desired fraction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The present disclosure will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

[0056] FIG. 1 shows a block diagram of a conventional fractional-N frequency synthesizer;

[0057] FIG. 2(a) shows the block diagram of a conventional divider controller based on a single quantizer digital delta-sigma modulator with shaped additive dither;

[0058] FIG. 2(b) shows the linearized model of the conventional divider controller of FIG. 2(a);

[0059] FIG. 3 shows a block diagram of a conventional divider controller based on a Multi stAge noise SHaping (MASH) digital delta-sigma modulator with shaped additive dither;

[0060] FIG. 4(a) shows a block diagram of a conventional Error Feedback Modulator (EFM);

[0061] FIG. 4(b) shows an implementation of the conventional Error Feedback Modulator (EFM) of FIG. 4(a);

[0062] FIG. 5 shows a block diagram of a conventional divider controller based on a nested cascaded MASH digital delta-sigma modulator with shaped additive dither;

[0063] FIG. 6 shows a block diagram of a conventional additive LSB-dithered MASH 1 1 divider controller with first-order shaped additive dither;

[0064] FIG. 7 shows simulated spectra of the zero-mean shaped dither and shaped quantization noise introduced by the divider controller;

[0065] FIG. 8 shows a simplified phase domain model of a fractional-N frequency synthesizer;

[0066] FIG. 9(a) shows simulated contributions to the output phase noise spectrum of the synthesizer from the divider controller in FIG. 6 without nonlinear distortion;

[0067] FIG. 9(b) shows simulated contributions to the output phase noise spectrum of the synthesizer from the divider controller in FIG. 6 with nonlinear distortion;

[0068] FIG. 10 shows a block diagram of a conventional additive LSB-dithered MASH 1-1-1-1 divider controller with first-order shaped additive dither;

[0069] FIG. 11(a) shows simulated contributions to the output phase noise spectrum of the synthesizer from the dithered MASH 1-1-1 divider controller in FIG. 6 with third order nonlinear distortion;

[0070] FIG. 11(b) shows simulated contributions to the output phase noise spectrum of the synthesizer from the dithered MASH 1-1-1-1 divider controller in FIG. 10 with third order nonlinear distortion;

[0071] FIG. 12 shows a block diagram of an embodiment of a single quantizer low spur and noise divider controller in accordance with the present disclosure;

[0072] FIG. 13 shows a block diagram of an embodiment of an L-stage low spur and noise cascaded ENOP-DDSM divider controller in accordance with the present disclosure, where the first (L−1) stages and the error cancellation network are configured to implement a noise transfer function NT F.sub.A(z) and the Lth stage is an error feedback modulator with noise transfer function NTF.sub.B(z);

[0073] FIG. 14 shows a block diagram of an embodiment of the error feedback modulator in the Lth stage of the L-stage low spur and noise cascaded ENOP-DDSM divider controller in accordance with the present disclosure;

[0074] FIG. 15 shows a block diagram of an embodiment of a three-stage low spur and noise cascaded ENOP-DDSM divider controller in accordance with the present disclosure, where the first two stages are first-order error feedback modulators each with a noise transfer function M.sup.−1(1−z.sup.−1) and the third stage is an error feedback modulator with noise transfer function M.sup.−1(1−z.sup.−2−z.sup.−3);.

[0075] FIG. 16 shows a block diagram of an embodiment of a T-level and L-stage low spur and noise nested cascaded divider controller in accordance with the present disclosure, wherein each level comprises (L−1) cascaded stages that together and with the error cancellation network implement a noise transfer function NTF.sub.A(z) and the remaining stages, one for each level, are configured to implement a noise transfer function NTF.sub.B(z);

[0076] FIG. 17 shows a block diagram of an embodiment of a two-level, three-stage low spur and noise nested cascaded divider controller in accordance with the present disclosure, where for each level i the first two stages are first-order error feedback modulators, each with a noise transfer function M.sub.i.sup.−1(1−z.sup.−1) and the third stage is an error feedback modulator with noise transfer function M.sub.i.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5);.

[0077] FIG. 18 shows simulated spectra of the output phase noise of a fractional-N frequency synthesizer having a third-order polynomial nonlinearity with (a) a MASH 1-1-1 divider controller, (b) a MASH 1-1-1-1 divider controller, (c) the cascaded ENOP-DDSM with K=4, R=2 shown in FIG. 15 and (d) the nested cascaded ENOP-DDSM with K=6, R=3 shown in FIG. 17; and

[0078] FIG. 19 shows simulated spectra of the output phase noise of a fractional-N frequency synthesizer having a fifth-order polynomial nonlinearity with (a) a MASH 1 -1-1-1 divider controller, (b) a MASH 1-1-1 divider controller, (c) the cascaded ENOP-DDSM with K=4, R=2 shown in FIG. 15 and (d) the nested cascaded ENOP-DDSM with K=6, R=3 shown in FIG. 17.

DETAILED DESCRIPTION

[0079] The present disclosure provides a DDSM-based divider controller suitable for use with a PLL-based fractional-N frequency synthesizer which Enhances the Nonlinearity-induced noise Performance, denoted ENOP-DDSM. This modulator mitigates the spurs and minimizes the folded noise that arise when used with a synthesizer due to interaction between the quantization signal introduced by the divider controller and a memoryless polynomial nonlinearity in the PLL. The present disclosure will now be described in conjunction with FIG. 12 onwards.

[0080] The digital delta sigma modulator (DDSM) of the disclosure implements the z domain governing equation

Y(z)=STF(z) X(z)+DTF(z) D(z)−NTF(z)E(z),

[0081] where Y(z), X(z), D(z) and E(z) are the z transforms of the output, primary input, secondary (dither) input, and quantization error of the DDSM, and wherein STF(z), DTF(z) and NTF(z) are the transfer functions from the primary input, dither input and quantization error to the output and wherein NTF (z) is of the form:

[00018]$\mathrm{NTF}\left(z\right)=A{z}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

[0082] where A , Q and K are constants, all the coefficients c.sub.i are real valued and at least one of the zeroes z.sub.j of

[00019]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

[0083] satisfies z.sub.j≠+1 for j=1, 2, . . . , K.

[0084] Taking A z.sup.−Q to be equal to 1/M, the divider controller of the disclosure thus implements a Noise Transfer Function

[00020]$\mathrm{NTF}\left(z\right)=\frac{\left(1-z^{-1}\right)}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

[0085] In one embodiment, the coefficients c.sub.i are equal to −1, 0 or 1.

[0086] In one embodiment, R number of the coefficients c.sub.i are equal to −1, (R-1) number of the coefficients c.sub.i are equal to +1 and the other (K-2R+1) number of the coefficients c.sub.i are equal to zero, with

[00021]$R\le \frac{K+1}{2}.$

[0087] In one embodiment, the coefficients c, are valued such that the noise transfer function can be represented in the form:

[00022]$\mathrm{NTF}\left(z\right)=A{z}^{-Q}\left(1+\underset{i=1}{\overset{K+1}{.Math.}}{d}_i{z}^{-i}\right)$

[0088] wherein coefficients d, are equal to −1, 0 or 1, and

[00023]$\underset{i=1}{\overset{K+1}{.Math.}}.Math.d_i.Math.\le -1+2\underset{i=1}{\overset{K}{.Math.}}.Math.c_i.Math.$

[0089] FIG. 12 shows a first embodiment of the present disclosure where the divider controller comprises a single Error Feedback Modulator (EFM) stage that constitutes a single quantizer digital delta-sigma modulator.

[0090] FIG. 13 shows a second embodiment of the present disclosure where the divider controller comprises an error cancellation network and a cascade of L number single quantizer or Error Feedback Modulator (EFM) stages, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion. The first portion comprises (L−1) stages and the second portion comprises the Lth stage. The first portion, together with the error cancellation network, implements a Noise Transfer Function

[00024]${\mathrm{NTF}}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$

[0091] where S is equal to Σ.sub.i=1.sup.L-1s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=M.sup.−1(1−z.sup.−1).sup.s.sup.i with i=1, 2, . . . L−1. The second portion, comprising the Lth stage, is configured to implement a Noise Transfer Function

[00025]${\mathrm{NTF}}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{\left(1-S\right)}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right),$

[0092] so as to give the overall Noise Transfer Function for the modulator set out previously.

[0093] Each of the L stages may be implemented with pipelined combinatorial logic. The outputs of the L stages are combined in the error cancellation network to yield the output y.

[0094] Divider controllers with constant inputs are known to suffer from limit cycles. Therefore, a binary dither signal, denoted d[n], is added into the signal chain to prevent limit cycle behavior.

[0095] In one embodiment, R number of the coefficients c, are equal to −1, (R-1) number of the coefficients c, are equal to +1 and the other (K-2R+1) number of the coefficients c.sub.i are equal to zero, with

[00026]$R\le \frac{K+1}{2}.$

[0096] For example, with K =6 and R =3, the Noise Transfer Function

NTF(z)=M.sup.−1(1−z.sup.−1)(1−z.sup.−1+z.sup.−2−z.sup.−3−z.sup.−4+z.sup.−6),

[0097] can be implemented in the multistage cascaded structure of FIG. 13 by partitioning factors of the NTF between a number of different stages.

[0098] By choosing S=1, the NTF can be realized by a cascade of two stages wherein the NTF of one stage is

NTF(z)=M.sup.−1(1−z.sup.−1)

[0099] and the NTF of the other stage is

NTF(z)=M.sup.−1(1−z.sup.−1+z.sup.−2−z.sup.−3−z.sup.−4+z.sup.−6).

[0100] By choosing S=2, the NTF can be written

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2(1+z.sup.−2−z.sup.−4−z.sup.−5),

[0101] and implemented with a three-stage cascaded structure wherein two EFM stages have NTFs of

NTF(z)=M.sup.−1(1−z.sup.−1)

[0102] and the NTF of the remaining stage is

NTF(z)=M.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5).

[0103] Equivalently, with S=2, the NTF can also be implemented with a two-stage cascaded structure wherein one EFM stage has NTF of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2

[0104] and the NTF of the other stage is

NTF(z)=M.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5).

[0105] By choosing S=3, the NTF can be expressed as

NTF(z)=M.sup.−1(1−z.sup.−1).sup.3(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4),

[0106] and implemented with a four-stage cascaded structure wherein three identical EFM stages have NTFs of

NTF(z)=M.sup.−1(1−z.sup.−1)

[0107] and the NTF of the fourth stage is

NTF(z)=M.sup.−1(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4)

[0108] Moreover, the same NTF can be implemented with a three-stage cascaded structure wherein one stage has NTF of

NTF(z)=M.sup.−1(1−z.sup.−1),

[0109] another stage has NTF of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2

[0110] and the remaining stage has NTF of

NTF(z)=M.sup.−1(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4).

[0111] Lastly, also with S=3, the NTF can be implemented with a two-stage cascaded structure wherein one stage has NTF of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.3

[0112] and the remaining stage has NTF of

NTF(z)=M.sup.−1(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4).

[0113] It should be clear that a number of different, but equivalent, partitions of the NTF are possible. The spurious tone immunity derives from the structure of the NTF rather than any particular implementation.

[0114] FIG. 14 shows an implementation of the Lth stage of FIG. 13. The output Y(z) is defined by

Y(z)=STF(z) X(z)−NTF.sub.B(z) E(z)

[0115] FIG. 15 shows an implementation of the divider controller in FIG. 13 with L=3 and S=2. Here, the dither signal d[n] has been added after the first stage to implement first-order shaping.

[0116] In the embodiment of the three-stage cascade in FIG. 15, K=4 and R=2. In particular, the first two stages, EFM.sub.1 and EFM.sub.2, are first-order EFMs and have noise transfer functions

NTF.sub.1(z)=NTF.sub.2(z)=M.sup.−1(1−z.sup.−1)

[0117] and EFM.sub.3 has noise transfer function

NTF.sub.3(z)=M.sup.−1(1−z.sup.−2−z.sup.−3),

[0118] giving an overall Noise Transfer Function for the modulator of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2(1−z.sup.−2−z.sup.−3).

[0119] FIG. 16 shows a third embodiment of the present disclosure where the divider controller comprises an error cancellation network and T levels of L cascaded single quantizer stages comprising a first portion and a second portion. The first portion comprises (L−1) error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level. The first portion together with the error cancellation network, implement the Noise Transfer Function

[00027]$NT{F}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$

[0120] where S is equal to Σ.sub.j=1.sup.L-1s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=M.sub.i.sup.−1(1−z.sup.−1).sup.s.sup.j with i=1, 2, . . . T and j=1, 2, . . . L−1. The second portion implements the Noise Transfer Function

[00028]$NT{F}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{\left(1-S\right)}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right),$

[0121] so as to give the overall Noise Transfer Function for the modulator set out previously.

[0122] The outputs of the L stages of the first cascade are combined in the error cancellation network to yield the output y.

[0123] In one embodiment, R number of the coefficients c, are equal to −1, (R-1) number of the coefficients c.sub.i are equal to +1 and the other (K−2R+1) number of the coefficients c, are equal to zero, with

[00029]$R\le \frac{K+1}{2}.$

[0124] Once again, it should be clear that a number of different, but equivalent, partitions of the NTF over T levels are possible. The spurious tone immunity derives from the structure of the NTF rather than the particular implementation.

[0125] Divider controllers with constant inputs are known to suffer from limit cycles. Therefore, a binary dither signal, denoted d[n], is added into the signal chain to prevent limit cycle behavior.

[0126] FIG. 17 shows an implementation of the divider controller in FIG. 16 with T=2, L=3 and S=2. The 20-bit input word x[n] added to the filtered dither is partitioned into two smaller 10-bit words {circumflex over (x)}.sub.i[n]. The outputs of the stages of the second cascade are added to the inputs of the stages of the first cascade.

[0127] In the embodiment of the three-stage nested cascade in FIG. 17, K=6 and R=3. In particular, the first two stages of both levels are first-order EFMs and have noise transfer functions

NTF.sub.1,1(z)=NTF.sub.1,2(z)=M.sub.1.sup.−1(1−z.sup.−1)

NTF.sub.2,1(z)=NTF.sub.2,2(z)=M.sub.2.sup.−1(1−z.sup.−1)

[0128] and the remaining stages have noise transfer functions

NTF.sub.1,3(z)=M.sub.1.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5)

NTF.sub.2,3(z)=M.sub.2.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5).

[0129] giving an overall Noise Transfer Function for the modulator of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2(1+z.sup.−2−z.sup.−4z.sup.−5)

[0130] FIG. 18 shows a comparison of output phase noise spectra of a synthesizer with a third-order polynomial nonlinearity and four different divider controllers: (a) the MASH 1-1-1 of FIG. 6, (b) the MASH 1-1-1-1 of FIG. 10, (c) the cascaded ENOP-DDSM with K=4, R=2 shown in FIG. 15 and (d) the nested cascaded ENOP-DDSM with K=6, R=3 shown in FIG. 17.

[0131] In FIG. 18, x=127 and M=2.sup.20, and the third-order polynomial nonlinearity in the synthesizer is

(x)=x+0.02x.sup.2+0.01x.sup.3.

[0132] The spurs and folded noise caused by interaction between the output y of the divider controller and the nonlinearity ( . ) in the loop can be minimized by choosing NTF.sub.Z(z) and NTF.sub.B(z) as described.

[0133] By comparison with the MASH 1-1-1 and MASH 1-1-1-1 divider controllers, it can be seen from FIG. 18 that the use of ENOP-DDSMs results in the elimination of spurs and a lower folded noise floor in the phase noise spectrogram of the output signal.

[0134] FIG. 19 shows simulated spectrograms of the output phase noise of a fractional-N frequency synthesizer with three different divider controllers: (a) the MASH 1-1-1 of FIG. 6, (b) the MASH 1-1-1-1 of FIG. 10, (c) the cascaded ENOP-DDSM with K=4, R=2 shown in FIG. 15 and (d) the nested cascaded ENOP-DDSM with K=6, R=3 shown in FIG. 17.

[0135] In each case, the memoryless nonlinearity is a fifth-order polynomial

(x)=x+0.042x.sup.2+0.031x.sup.3−0.01x.sup.4−0.005x.sup.5

[0136] Furthermore, M=2.sup.20 and x=127,227,327 and 427 for the MASH 1-1-1, MASH 1-1-1-1, cascaded ENOP-DDSM and nested cascaded ENOP-DDSMs, respectively.

[0137] It can be seen from FIG. 19 that the use of the noise transfer function NTF(z)=M.sup.−1(1−z.sup.−1).sup.2(1+z.sup.−2−z.sup.−4−z.sup.−5) results in the elimination of spurs and a low folded noise floor in the phase noise spectrogram of the output signal.

[0138] When incorporated in a fractional-N frequency synthesizer with pth order polynomial distortion, the low spur and noise divider controller of the present disclosure with noise transfer function NTF(z)=M.sup.−1(1−z.sup.−1)(1+Σ.sub.i=1.sup.Kc.sub.iz.sup.−-i) which satisfies the conditions described above and with a given R does not exhibit spurs if

[00030]$R\ge \frac{p+1}{2}.$

Furthermore, the folded noise introduced by the low spur and noise divider controller is minimized.

[0139] Accordingly, the use of a DDSM based divider controller having the above described noise transfer function results in the generation of a signal that is characterised by an improved spur immunity performance when distorted by static polynomial nonlinearities. Thus, it will be appreciated that the divider controller of the present disclosure, when used with a fractional-N frequency synthesizer, provides a signal which is less prone to produce spurs and folded noise than a frequency synthesizer which uses a conventional dithered digital delta-sigma modulator. Through the minimization of nonlinearity-induced folded noise and the mitigation of spurs, it enables the frequency synthesizer to generate cleaner carriers for a range of applications including communications, radar and instrumentation.

[0140] In the specification the terms “comprise, comprises, comprised and comprising” or any variation thereof and the terms include, includes, included and including” or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

[0141] The present disclosure is not limited to the embodiments hereinbefore described but may be varied in both construction and detail