METHOD FOR CHANGING A BITWIDTH OF AN FPGA CONFIGURATION

Abstract

A method for changing a bitwidth of an FPGA configuration for an FPGA, the FPGA configuration having a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3, and the method having the step: when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present, replacing k least significant bits of the data signals in each case with a zero with kε and ≥2 during an execution of the FPGA configuration on the FPGA.

Claims

1. A method for changing a bitwidth of an FPGA configuration for an FPGA, the method comprising: providing the FPGA configuration with a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3; and replacing k least significant bits of the data signals in each case with a zero with kε and ≥2 during an execution of the FPGA configuration on the FPGA when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present.

2. The method according to claim 1, wherein the replacing comprises inserting at least one controller and at least one signal control block, which at least one signal control block is configured to replace the k least significant bits of the data signals with a zero, and wherein at least one controller is configured to control the at least one signal control block for replacing when the threshold of the current consumption and/or the temperature of the FPGA is exceeded and/or the replacement signal is present.

3. The method according to claim 1, further comprising: replacing the k least significant bits of all data signals in each case with a zero.

4. The method according to claim 1, further comprising: cutting out the k least significant bits of the data signals and inserting zeros as the k least significant bits of the data signals.

5. The method according to claim 1, further comprising: executing the FPGA configuration in only every m-th clock of the FPGA (2) with mε and ≥2.

6. The method according to claim 6, wherein m is changable during the execution.

7. A computer-implemented method for creating an FPGA configuration comprising a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3, the method comprising: inserting at least one signal control block into an FPGA model and/or netlist and/or an HDL code of the FPGA configuration, wherein the signal control block is configured to replace k least significant bits of the data signals in each case with a zero with kε and ≥2; inserting at least one controller into the FPGA model and/or the netlist and/or the HDL code of the FPGA configuration, which is designed to control the at least one signal control block for replacing when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present; and transferring the FPGA configuration with the at least one inserted signal control block and the at least one inserted controller to the FPGA.

8. The method according to claim 7, wherein the data signals comprise a bitwidth of 8, 16, 32, 64, or 80 bits and/or k≥2.sup.n-2.

9. The method according to claim 7, wherein n=6 and k=29.

10. An FPGA configuration comprising a bitstream which, when written to a configuration layer of an FPGA sets up the FPGA to execute a method according to claim 1.

11. An FPGA comprising a processor to execute the method according to claim 1.

12. The FPGA according to claim 11, comprising a current sensor and/or a temperature sensor configured to determine the current consumption and/or the temperature of the FPGA.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0033] FIG. 1 shows a schematic view of a controller and a signal control block for reducing the precision from double precision to single precision at runtime according to a preferred exemplary embodiment of the invention; and

[0034] FIGS. 2a and 2b show an example of dynamic bitwidth adjustment for the lower 29 bits of an FPGA configuration for reducing the precision from double precision to single precision according to the preferred exemplary embodiment of the invention.

DETAILED DESCRIPTION

[0035] FIG. 1 shows a schematic view of a controller 4 and a signal control block 1 for changing a bitwidth of an FPGA configuration for an FPGA 2, which is shown only schematically.

[0036] The FPGA configuration has a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3. In the proposed method, when a threshold of a current consumption and/or a temperature of FPGA 2 is exceeded and/or a replacement signal is present during an execution of the FPGA configuration on FPGA 2, the k least significant bits of the data signals are each replaced with a zero with kε and ≥2 by controller 4 and signal control block 1. For n=6 and k=29, therefore, for a 64 bit data signal, the method leads to a reduction in precision from double precision to single precision. FIGS. 2a and 2b show a corresponding example for dynamic bitwidth adjustment for the lower 29 bits of the FPGA configuration according to the preferred exemplary embodiment of the invention.

[0037] Specifically, the method includes the following steps:

[0038] First, an automatic modification of an FPGA model/netlist/VHDL code takes place as an FPGA configuration before an FPGA build in a temporary model/netlist/VHDL code in which controller 4 and signal control block 1 are inserted for adaptive dynamic bitwidth adjustment. The power consumption and/or the temperature of FPGA 2, which can be determined by means of a current sensor and/or temperature sensor 3 shown only schematically, serve as a reference variable.

[0039] Likewise, the reference variable can be specified externally by a user as a replacement signal, for example, if the power consumption is to be reduced even further below the threshold value. Controller 4 can further be equipped with a hysteresis function in the case of reducing and returning to full precision. Also optionally, the controller can be parameterized by FPGA 2 or an external processor. Thus, it can be provided that controller 4 receives an external replacement signal and thereupon activate the signal control block or blocks.

[0040] As already mentioned, the reference variables are the power consumption of FPGA 2, in particular as a short-term criterion, and/or the temperature of FPGA 2, in particular as a long-term criterion, and alternatively the replacement signal. Likewise, controller 4 can be provided for bitwidth adjustment already during modeling in the model and the user receives temperature and current as output signals of controller 4 to manually adjust the bitwidth. For this purpose, the “automatic system” can be deactivated in controller 4 via a replacement signal or replaced by an individually modeled specification for bitwidth reduction.

[0041] Subsequently, all possible model input blocks and calculation blocks are searched and the controller and signal control block 1 are inserted for all model input blocks that contain data signals. For floating point data signals, this can usually be clearly identified, whereas for fixed point data signals, a user may need to indicate whether a data signal contains data or bit masks/commands.

[0042] Alternatively, the blockset can automatically analyze whether the data signal is calculated in the model and is therefore a reducible data signal. Similarly, signal control block 1 is inserted for model calculation blocks which can optionally recover the zeroed least significant bits, for example, in a multiplexer. Finally, an output of controller 4 is connected to an input of signal control block 1.

[0043] As a result, the FPGA build of the model modified with the dynamic bitwidth adjustment is obtained, which can be executed as an FPGA configuration on the FPGA. If necessary, the FPGA configuration can be tested with reduced precision to verify that the controller does not become unstable as soon as the bitwidth is reduced.

[0044] With the specified switching from double precision to single precision, there is the possibility that 29 of the 64 bits can no longer be toggled. It has been shown experimentally that the power consumption is reduced by 45.3%. The power consumption can even be reduced by 65.6% in the case of half precision and by 79.7% in the case of quarter precision. An even further reduction in power consumption can be achieved if the FPGA configuration is performed with mε and ≥2 in only every m-th clock of the FPGA, therefore, for example, only in every third or fourth clock.

[0045] The described exemplary embodiments are merely examples that can be modified and/or supplemented in a variety of ways within the scope of the claims. Any feature described for a particular exemplary embodiment can be used independently or in combination with other features in any other exemplary embodiment. Any feature that has been described for an exemplary embodiment of a particular category can also be used in a corresponding manner in an exemplary embodiment of another category.

[0046] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.