Semiconductor device and fabrication method thereof and semiconductor structure

Abstract

A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Claims

1. A semiconductor device, comprising: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding in position to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein a portion of a top surface of the first conductive portion is exposed from the second conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, wherein the solder balls directly contact the second conductive portions and the connecting pads, and the second conductive portion, each of the solder balls, and each of the connecting pads are less in width than the first conductive portion.

2. The semiconductor device of claim 1, further comprising an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements and the solder balls.

3. A fabrication method of a semiconductor device, comprising the steps of: providing a substrate having a plurality of connecting pads and providing a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads; forming a metal layer on the bonding pads of the semiconductor component; forming a plurality of first conductive portions on the metal layer corresponding in position to the bonding pads; forming a second conductive portion on each of the first conductive portions, wherein a portion of a top surface of the first conductive portion is exposed from the second conductive portion; and forming a plurality of solder balls between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, wherein the solder balls directly contact the second conductive portions and the connecting pads, and each of the solder balls, each of the connecting pads, and the second conductive portion are less in width than the first conductive portion.

4. The fabrication method of claim 3, further comprising forming a passivation layer on the surface of the semiconductor component and the bonding pads, wherein the passivation layer has a plurality of first openings for exposing the bonding pads, and the metal layer is formed on the passivation layer and the bonding pads exposed from the first openings.

5. The fabrication method of claim 3, wherein the metal layer has a plurality of second openings formed on a surface thereof and the first conductive portions are formed on the surface of the metal layer and in the second openings.

6. The fabrication method of claim 3, wherein the width of the second conductive portion is 30 to 70 percent of the width of the first conductive portion.

7. The fabrication method of claim 3, wherein the second conductive portion is less in height than the first conductive portion.

8. The fabrication method of claim 7, wherein the height of the second conductive portion is 25 to 50 percent of the height of the first conductive portion.

9. The fabrication method of claim 3, wherein forming the first conductive portions on the metal layer comprises the steps of: forming a first photo resist layer on the metal layer, wherein the first photo resist layer has a plurality of openings corresponding in position to the bonding pads for exposing portions of the metal layer; forming the first conductive portions on the portions of the metal layer exposed from the openings of the first photo resist layer; and removing the first photo resist layer.

10. The fabrication method of claim 9, wherein forming the second conductive portions on the first conductive portions comprises the steps of: forming a second photo resist layer on the metal layer and the first conductive portions, wherein the second photo resist layer has a plurality of openings for exposing the first conductive portions and the openings of the second photo resist layer are less in width than the openings of the first photo resist layer; and forming the second conductive portions on the first conductive portions in the openings of the second photo resist layer.

11. The fabrication method of claim 10, wherein forming the solder balls comprises the steps of: forming a solder material on the second conductive portions in the openings of the second photo resist layer; heating the solder material to form the solder balls; and removing the second photo resist layer.

12. The fabrication method of claim 3, further comprising removing the metal layer outside peripheries of the first conductive portions so as to form a UBM layer.

13. The fabrication method of claim 3, further comprising forming an encapsulant between the substrate and the semiconductor component for encapsulating the first and second conductive portions and the solder balls.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1A and 1B are schematic cross-sectional views showing a semiconductor device and a fabrication method thereof according to the prior art;

(2) FIGS. 2A to 2N are schematic cross-sectional views showing a semiconductor device and a fabrication method thereof according to a first embodiment of the present invention; and

(3) FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(4) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(5) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(6) FIGS. 2A to 2N are schematic cross-sectional views showing a semiconductor device and a fabrication method thereof according to a first embodiment of the present invention.

(7) Referring to FIG. 2A, a semiconductor component 21 such as a semiconductor chip is provided. The semiconductor component 21 has at least two adjacent bonding pads 211 formed on a surface 210 thereof. Further, a passivation layer 212 is formed on the surface 210 and the bonding pads 211 and has a plurality of first openings 213 for exposing the bonding pads 211.

(8) Referring to FIG. 2B, a metal layer 22 is formed on the passivation layer 212 and the exposed bonding pads 211. The metal layer 22 has a plurality of second openings 222 formed on a surface 221 thereof.

(9) In other embodiments, the metal layer 22 can be directly formed on the surface 210 of the semiconductor component 21 and the bonding pads 211. Further, the second openings 222 can be omitted in other embodiments.

(10) Referring to FIG. 2C, a first photo resist layer 23 is formed on the surface 221 of the metal layer 22. The first photo resist layer 23 has a plurality of openings 231 corresponding in position to the bonding pads 211 for exposing portions of the surface 221 and the second openings 222 of the metal layer 22. The openings 231 of the first photo resist layer 23 have a width of W1.

(11) Referring to FIG. 2D, by performing such as an electroplating process, a plurality of first conductive portions 24 are formed on the exposed portions of the surface 221 and in the second openings 222 of the metal layer 22. The first conductive portions 24 have a width of W1 and a height of H1.

(12) Referring to FIG. 2E, the first photo resist layer 23 is removed.

(13) Referring to FIG. 2F, a second photo resist layer 25 is formed on the metal layer 22 and the first conductive portions 24, and has a plurality of openings 251 for exposing surfaces 241 of the first conductive portions 24. The openings 251 of the second photo resist layer 25 have a width W2 less than the width W1 of the openings 231 of the first photo resist layer 23.

(14) Referring to FIG. 2G, by performing such as an electroplating process, a plurality of second conductive portions 26 are formed on the first conductive portions 24 in the openings 251 of the second photo resist layer 25 so as to form a plurality of conductive elements 27 each having a first conductive portion 24 and a second conductive portion 26.

(15) The second conductive portion 26 has a width W2 less than the width W1 of the first conductive portion 24. Further, the second conductive portion 26 has a height H2 less than the height H1 of the first conductive portion 24. The first conductive portion 24 can have a T-shape, the second conductive portion 26 can have a straight line shape, and the conductive element 27 can have a cross shape.

(16) Referring to FIG. 2H, a solder material 28 is formed on the second conductive portions 26 in the openings 251 of the second photo resist layer 25.

(17) Referring to FIG. 2I, the second photo resist layer 25 is removed.

(18) Referring to FIG. 2J, an etching process is performed along lines S of FIG. 2I so as to remove the metal layer 22 outside peripheries of the first conductive portions 24, thereby forming a substantially U-shaped or V-shaped UBM layer 223.

(19) Referring to FIG. 2K, the solder material 28 is heated to form a plurality of solder balls 28′.

(20) Referring to FIG. 2L, the overall structure of FIG. 2K is turned upside down to cause the solder balls 28′ to correspond in position to connecting pads 201 of a substrate 20.

(21) The adjacent second conductive portions 26 of the present invention have a distance D1 that is greater than the distance D between the conventional adjacent copper pillars 12, thereby preventing solder bridging from occurring between the adjacent second conductive portions 26.

(22) Referring to FIG. 2M, the second conductive portions 26 are bonded to the connecting pads 201 through the solder balls 28′ to thereby electrically connect the semiconductor component 21 and the substrate 20.

(23) Referring to FIG. 2N, an encapsulant 29 is formed between the substrate 20 and the passivation layer 212 of the semiconductor component 21 for encapsulating the substrate 20, the connecting pads 201, the passivation layer 212, the UBM layer 223, the conductive elements 27 and the solder balls 28′.

(24) The present invention further provides a semiconductor structure having a semiconductor component 21 and a plurality of conductive elements 27.

(25) The semiconductor component 21 has at least two adjacent bonding pads 211 formed on a surface 210 thereof and a UBM layer 223 formed on the bonding pads 211. Each of the conductive elements 27 has a first conductive portion 24 and a second conductive portion 26 sequentially formed on the UBM layer 223. Therein, the width W2 of the second conductive portion 26 is less than the width W1 of the first conductive portion 24, and the height H2 of the second conductive portion 26 is less than the height H1 of the first conductive portion 24.

(26) The semiconductor structure can further have a solder material 28 formed on the second conductive portions 26.

(27) In the present embodiment, the width W2 of the second conductive portions 26 can be 30 to 70 percent of the width W1 of the first conductive portions 24. The height H2 of the second conductive portions 26 can be 25 to 50 percent of the height H1 of the first conductive portions 24. The first conductive portions 24 and the second conductive portions 26 can be integrally or separately formed and made of same or different materials. The first conductive portions 24 and the second conductive portions 26 can be made of copper or other conductive materials, and the conductive elements 27 can be such as copper pillars.

(28) The semiconductor component 21 can further have a passivation layer 212 formed on the surface 210 and the bonding pads 211. The passivation layer 212 has a plurality of first openings 213 exposing the bonding pads 211 such that the UBM layer 223 is formed on the bonding pads 211 exposed from the first openings 213 and portions of the passivation layer 212.

(29) The UBM layer 223 can have a plurality of second openings 222 formed on a surface 221 thereof and the first conductive portions 24 can be formed on the surface 221 of the UBM layer 223 and in the second openings 222.

(30) Referring to FIG. 2N, the present invention further provides a semiconductor device 2 having a substrate 20, a semiconductor component 21, a plurality of conductive elements 27 and a plurality of solder balls 28′.

(31) The substrate 20 has at least two adjacent connecting pads 201. The semiconductor component 21 has a plurality of bonding pads 211 formed on a surface 210 thereof and corresponding to the connecting pads 201 and a UBM layer 223 formed on the bonding pads 211.

(32) Each of the conductive elements 27 has a first conductive portion 24 and a second conductive portion 26 sequentially formed on the UBM layer 223, and the width W2 of the second conductive portion 26 is less than the width W1 of the first conductive portion 24. The solder balls 28′ are formed between the second conductive portions 26 and the connecting pads 201.

(33) In the present embodiment, the width W2 of the second conductive portions 26 can be 30 to 70 percent of the width W1 of the first conductive portions 24. The height H2 of the second conductive portions 26 can be 25 to 50 percent of the height H1 of the first conductive portions 24. The first conductive portions 24 and the second conductive portions 26 can be integrally or separately formed and made of same or different materials. The first conductive portions 24 and the second conductive portions 26 can be made of copper or other conductive materials, and the conductive elements 27 can be such as copper pillars.

(34) The semiconductor component 21 can further have a passivation layer 212 formed on the surface 210 and the bonding pads 211. The passivation layer 212 has a plurality of first openings 213 exposing the bonding pads 211 such that the UBM layer 223 is formed on the bonding pads 211 exposed from the first openings 213 and portions of the passivation layer 212.

(35) The UBM layer 223 can have a plurality of second openings 222 formed on a surface 221 thereof and the first conductive portions 24 can be formed on the surface 221 of the UBM layer 223 and in the second openings 222.

(36) The semiconductor device 2 can further have an encapsulant 29 formed between the substrate 20 and the passivation layer 212 of the semiconductor component 21 for encapsulating the substrate 20, the connecting pads 201, the passivation layer 212, the UBM layer 223, the conductive elements 27 and the solder balls 28′.

(37) FIG. 3 is a schematic cross-sectional view of a semiconductor device 2′ according to a second embodiment of the present invention. Different from the first embodiment, the second openings 222 of FIG. 2N are omitted in the present embodiment and each of the UBM layer 223, the first conductive portions 24 and the second conductive portions 26 has a straight line shape and each of the conductive elements 27 has a T-shape.

(38) Therefore, the present invention mainly involves sequentially forming a first conductive portion and a second conductive portion of a conductive element on a UBM layer of a semiconductor component and the second conductive portion is less in width and height that the first conductive portion.

(39) By dispensing with the insulating layer (shown in FIGS. 1A and 1B) as required in the prior art, the present invention reduces the fabrication cost of the semiconductor device and the semiconductor structure. Further, the width of the first conductive portions (for example, 50 um) can be greater than the width of the conventional copper pillars (for example, 40 um) so as to increase the contact area between the first conductive portions and the UBM layer, thereby reducing stresses therebetween. Furthermore, the width of the second conductive portions (for example, 30 um) can be less than the width of the conventional copper pillars (for example, 40 um) so as to increase the distance between adjacent second conductive portions, thus preventing solder bridging from occurring therebetween and increasing the produce yield.

(40) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.