Package structure and fabrication method thereof

Abstract

A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

Claims

1. A package structure, comprising: an encapsulant having opposite top and bottom surfaces; at least a semiconductor chip embedded in the encapsulant and having opposite active and inactive surfaces exposed from the encapsulant, wherein the inactive surface of the semiconductor chip is flush with the top surface of the encapsulant, and the active surface of the semiconductor chip is flush with the bottom surface of the encapsulant; and a patterned resist layer embedded in the encapsulant and having opposite first and second surfaces exposed from the encapsulant, wherein the second surface of the patterned resist layer is flush with the top surface of the encapsulant, and the patterned resist layer is a photoresist layer.

2. The structure of claim 1, further comprising: a plurality of conductive through holes formed in the patterned resist layer and penetrating the first and second surfaces of the patterned resist layer; a first redistribution layer formed on the active surface of the semiconductor chip, the first surface of the patterned resist layer and the encapsulant, wherein the first redistribution layer is electrically connected to the active surface of the semiconductor chip; and a second redistribution layer formed on the inactive surface of the semiconductor chip, the second surface of the patterned resist layer and the encapsulant, wherein the second redistribution layer is electrically connected to the first redistribution layer through the conductive through holes.

3. The structure of claim 1, further comprising a plurality of solder balls formed on the first redistribution layer.

4. The structure of claim 1, wherein the resist layer is a negative photoresist layer.

5. The structure of claim 1, wherein the encapsulant contains filler particles.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package of a PoP structure; and

(2) FIGS. 2A to 2K are schematic cross-sectional views showing a package structure and a fabrication method thereof according to the present invention, wherein FIG. 2E′ shows another embodiment of FIG. 2E.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(3) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(4) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(5) FIGS. 2A to 2K are schematic cross-sectional views showing a method for fabricating a package structure according to the present invention.

(6) Referring to FIG. 2A, a first carrier 20a having a first release layer 200a formed thereon is provided. At least a semiconductor chip 21 is disposed on the first release layer 200a of the first carrier 20a. The semiconductor chip 21 has opposite active and inactive surfaces 21a, 21b and is disposed on the first release layer 200a via the active surface 21a thereof. In other words, the active surface 21a of the semiconductor chip 21 faces the first carrier 20a. The first release layer 200a is used to facilitate later removal of the first carrier 20a from the semiconductor chip 21.

(7) Referring to FIGS. 2B and 2C, a resist layer 27 made of such as a photoresist material is formed on and covers the first carrier 20a and the semiconductor chip 21. Then, the resist layer 27 is patterned to expose the semiconductor chip 21 and portions of the first release layer 200a. Preferably, the resist layer 27 is a negative photoresist layer.

(8) Referring to FIG. 2D, an encapsulant 22 is formed on the first carrier 20a to encapsulate the semiconductor chip 21 and the patterned resist layer 27. The encapsulant 22 contains filler particles. The size of the filler particles is large enough to provide sufficient structural strength.

(9) Referring to FIG. 2E, the encapsulant 22 is thinned by grinding or cutting to expose the inactive surface 21b of the semiconductor chip 21 and a second surface 272 of the patterned resist layer 27. The inactive surface 21b of the semiconductor chip 21 and the second surface 272 of the patterned resist layer 27 are flush with the surface of the encapsulant 22.

(10) Referring to FIG. 2E′, the first release layer 200a and the first carrier 20a are removed to expose the active surface 21a of the semiconductor chip 21, a first surface 271 of the patterned resist layer 27 and the encapsulant 22. As such, a package structure of the present invention is obtained.

(11) Therefore, the package structure of the present invention has: an encapsulant 22; at least a semiconductor chip 21 embedded in the encapsulant 22 and having opposite active and inactive surfaces 21a, 21b exposed from the encapsulant 22; and a patterned resist layer 27 embedded in the encapsulant 22 and having opposite first and second surfaces 271, 272 exposed from the encapsulant 22.

(12) In another embodiment, retelling to FIG. 2F, continued from FIG. 2E, a second carrier 20b having a second release layer 200b formed thereon is provided. The second carrier 20b is disposed on and covers the inactive surface 21b of the semiconductor chip 21, the second surface 272 of the patterned resist layer 27 and the encapsulant 22 through the second release layer 200b. Then, the first carrier 20a and the first release layer 200a are removed to expose the active surface 21a of the semiconductor chip 21, the first surface 271 of the patterned resist layer 27 and the encapsulant 22.

(13) Referring to FIG. 2G, a first redistribution layer 23 is formed on the active surface 21a of the semiconductor chip 21, the first surface 271 of the patterned resist layer 27 and the encapsulant 22. The first redistribution layer 23 is electrically connected to the active surface 21a of the semiconductor chip 21.

(14) Referring to FIG. 2H, a third carrier 20c having a third release layer 200c is provided. The third carrier 20c is disposed on and covers the first redistribution layer 23 through the third release layer 200c. Then, the second carrier 20b and the second release layer 200b are removed to expose the inactive surface 21b of the semiconductor chip 21, the second surface 272 of the patterned resist layer 27 and the encapsulant 22.

(15) Referring to FIG. 2I, a plurality of through holes 27a are formed in the patterned resist layer 27 by such as laser drilling so as to expose portions of the first redistribution layer 23.

(16) Referring to FIG. 2J, a second redistribution layer 26 is formed on the inactive surface 21b of the semiconductor chip 21, the second surface 272 of the patterned resist layer 27 and the encapsulant 22, and a plurality of conductive through holes 27b are formed in the through holes of the patterned resist layer 27. As such, the second redistribution layer 26 is electrically connected to the first redistribution layer 23 through the conductive through holes 27b.

(17) Referring to FIG. 2K, the third carrier 20c and the third release layer 200c are removed, and a plurality of solder balls 24 are formed on the first redistribution layer 23. As such, a package structure according to another embodiment of the present invention is obtained.

(18) Referring to FIG. 2K, the package structure according to another embodiment of the present invention has: an encapsulant 22; a semiconductor chip 21 embedded in the encapsulant 22 and having opposite active and inactive surfaces 21a, 21b exposed from the encapsulant 22; a patterned resist layer 27 embedded in the encapsulant 22 and having opposite first and second surfaces 271, 272 exposed from the encapsulant 22; a plurality of conductive through holes 27b formed in the patterned resist layer 27 and penetrating the first and second surfaces 271, 272 of the patterned resist layer 27; a first redistribution layer 23 formed on the active surface 21a of the semiconductor chip 21, the first surface 271 of the patterned resist layer 27 and the encapsulant 22, wherein the first redistribution layer 23 is electrically connected to the active surface 21a of the semiconductor chip 21; and a second redistribution layer 26 formed on the inactive surface 21b of the semiconductor chip 21, the second surface 272 of the patterned resist layer 27 and the encapsulant 22, wherein the second redistribution layer 26 is electrically connected to the first redistribution layer 23 through the conductive through holes 27b.

(19) Further, a plurality of solder balls 24 are formed on the first redistribution layer so as for the package structure to be stacked on and electrically connected to another package structure.

(20) According to the present invention, the patterned resist layer is formed to partially replace the encapsulant. As such, a plurality of through holes are formed by drilling the patterned resist layer instead of the encapsulant as in the prior art. Therefore, the present invention improves the drilling effect and overcomes the conventional drawback of surface roughness of the through holes caused by filler particles of the encapsulant, thereby facilitating a subsequent electroplating process for forming the conductive through holes in the through holes and improving the electrical reliability.

(21) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.