System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC

Abstract

A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

Claims

1. A current steering converter fabricated using a predetermined integrated circuit technology, comprising: a unary portion having one or more current sources; a binary portion including: a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length and M is an integer representing multiple number; and a reference source coupled to the devices, wherein the current from the reference source is split equally using a current divider.

2. The converter of claim 1, wherein the devices comprise NMOS current sources or PMOS current sources.

3. The converter of claim 1, wherein the dimensions of the device reaches a minimum size of the technology.

4. The converter of claim 1, wherein the least-significant-bit (LSB) comprises two devices coupled in series, each having a dimension of (W.sub.min/L)*M, and the most significant-bit (MSB) uses the dimension of a reference current source, and each bit in between uses half of the multiple number to cut the current by half, and where W.sub.min is the minimum width allowed in the technology design rule.

5. The converter of claim 1, comprising an LSB bit 0, bit 1 and bit 2, wherein bit 1 has the same device size as bit 2 and splits the current by two with two switches connecting to a bit 1 device with one switch is connected to the converter output, wherein bit 0 has the same device size as bit 2 and splits the current by four with four switches connecting to a bit 0 device with one switch is connected to the converter outputs.

6. The converter of claim 5, wherein the resistance of a resistor not connected to the converter output is trimmed to compensate for device fabrication mismatch.

7. The converter of claim 6, wherein the adjustable load element consists of a fixed value passive resistor and an active PMOS or NMOS transistor with controlled gate voltage.

8. A method for fabricating a current steering converter with a predetermined integrated circuit technology, comprising: forming a unary portion having one or more current sources; forming a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and specifying a layout for a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number; and generating a current from a reference source coupled to the devices, wherein the current from the reference source is split equally using a divider for the device dimension to reach a minimize size of the technology.

9. The method of claim 8, comprising forming an LSB bit 0, bit 1 and bit 2, wherein bit 1 has the same device size as bit 2 and splits the current by two with two switches connecting to a bit 1 device with one switch is connected to the converter output, wherein bit 0 has the same device size as bit 2 and splits the current by four with four switches connecting to a bit 0 device with one switch is connected to the converter output.

10. The method of claim 9, wherein the resistance of the resistor not connected to the converter output is trimmed to compensate for device fabrication mismatch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a basic architecture of 4-bit segmented current steering DAC.

(2) FIG. 2 shows an exemplary 5-bit binary portion of high resolution current steering DAC.

(3) FIG. 3 shows an exemplary 5-bit binary portion of low power current steering DAC.

(4) FIG. 4 shows an exemplary diagram of voltage divider.

(5) FIG. 5 shows an exemplary of current divider.

(6) FIG. 6 shows an exemplary circuit diagram of current source splitting by 2 and 4.

(7) FIG. 7 shows an exemplary circuit diagram of adjustable current source splitting.

(8) FIG. 8A-8B shows an exemplary diagram of resistive load to trim current sources.

DETAILED DESCRIPTION

(9) The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

(10) The terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

(11) Furthermore, it is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

(12) Similarly, it is to be noticed that the term “coupled” discloses both direct and indirect coupling and should not be interpreted as being restricted to direct connections only. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.

(13) FIG. 1 shows a basic 4-bit segmented current steering DAC. The DAC is segmented into 2-bit binary and 2-bit unary current sources that steer current to either the positive or negative terminals based on the input bits. A 2-to-3 decoder is needed to convert the two uppermost input bits into thermometer code. The two terminals are connected to resistor load to convert current into voltage.

(14) FIG. 2 shows a 13-bit DAC using 8 unary and 5 binary segmented architecture. The illustration only shows the binary part and the unary portion is not shown. Each NMOS device size is described as (W/L)*M, where W and L is the width and length of each device and M is a multiple number. The multiple number M for Bit0, Bit1, Bit2, Bit3 and Bit4 are 1, 2, 4, 8 and 16 respectively. The mismatch between the current sources created error in terms of current amount and the errors represent the nonlinearity of the DAC. The main mismatch sources between two MOS devices are threshold voltage mismatch A.sub.vt and conductance parameter mismatch A.sub.β. A.sub.vt and A.sub.β are given for one specific technology and both A.sub.vt and A.sub.β are inversely proportional to the square root of the device area.

(15) $\begin{array}{c}{\sigma }_{\mathrm{Vt}}=\frac{A_{\mathrm{Vt}}}{\sqrt{\mathrm{WL}}}\\ \frac{\sigma \left(\Delta \beta \right)}{\beta }=\frac{A_{\beta }}{\sqrt{\mathrm{WL}}}\end{array}$
where σ is the standard deviation of Gaussian distribution

(16) For 5-bit binary implementation, the total number of M is 31 which represents 31 current sources. The maximum differential non-linearity (DNL) happens at the mid-scale when input code 01111 switches to 10000, where 15 current sources from Bit0 to Bit3 turn off and 16 current sources of Bit4 turn on. For N-bit binary current steering DAC, assuming currents sources errors are not correlated, the maximum DNL can be described as the following equation:

(17) ${\sigma }_{\mathrm{DNL},max}=\sqrt{2^N-1}\frac{\sigma \left(I\right)}{I}\cong 2^{N/2}\frac{\sigma \left(I\right)}{I}$$\frac{\sigma \left(I\right)}{I}=\mathrm{unit}\mathrm{current}\mathrm{standard}\mathrm{deviation}$
unit current standard deviation
N is Total Number of Binary Bits

(18) To minimize the mismatch of the current sources, the circuit embodiment on FIG. 2 uses only one same dimension W/L for the 31 current sources, the difference between these 31 current source is the multiple number M. For the physical implementation or mask layout, using the exactly same dimension enable a very symmetrical floorplan which helps to minimize the mismatch of the physical layout implementation in addition to inherent device mismatch.

(19) However, for the applications require high resolution and very low power features, the current amount is reduced in such a way that the dimension of the device reaches the minimum size of the technology accordingly to MOSFET IV characteristic equation:

(20) $I_D=\frac{1}{2}{u}_n{C}_{\mathrm{ox}}\frac{W}{L}{\left(V_{\mathrm{GS}}-V_{\mathrm{TH}}\right)}^2$
I.sub.D is the current going through the device
u.sub.nC.sub.ox is the product of the electron mobility and the oxide layer capacitance
(V.sub.GS-V.sub.TH) is the difference between gate to source voltage and threshold voltage

(21) FIG. 3 illustrates the 5-bit binary current source of the low power current steering DAC. W.sub.min is the minimum width allowed in the technology design rule. In this case, Bit4 current source 310.2 uses the same dimension of the reference current source 310.1. Bit3 uses half of the multiple number to cut the current by half. Bit2 and Bit1 cut the device width by half and by a quarter respectively to further decrease the current. For Bit0, it has reaches the minimum width so two minimum size are stack up in series which effectively reduce the W/L ratio by half.

(22) Note that the mismatches of devices 310.4, 310.5, 310.6 and 310.7 are worse than 310.3 since different device widths are used. Once the physical dimension is different the threshold voltage will be different especially for advanced deep submicron technology which has very thin oxide thickness. Compared with FIG. 2 the maximum DNL of this 5-bit binary current sources in FIG. 3 is much worse due to the different physical dimension and decreased device size. For the applications that require monotonic DAC characteristic with very low power feature, the structure of FIG. 3 is very difficult to meet half LSB DNL specification.

(23) Instead of reducing the device size, the same device size can be used if the current can be split equally. FIG. 4 shows a diagram of voltage divider, Vo voltage is half of V.sub.IN when the value of R.sub.1 equals R.sub.2. The same concept can be applied to split the current into two half currents. According to an embodiment illustrated in FIG. 5, a reference circuit I.sub.B can be split into I.sub.1 and I.sub.2. The resistances R.sub.1 and R.sub.2 looking into 510 and 520 have to be the same to make I.sub.1 current has the same amount of I.sub.2.

(24) FIG. 6 illustrates a circuit diagram of current splitting scheme used on last 2 bits Bit 1 610 and Bit 0 620. As the diagram describes, Bit 2, Bit 1 and Bit 0 should have the 4I, 2I and 1I amount of current respectively by their binary representation. The device dimension of Bit 2 current source is (2*W/L). For Bit 1, it uses the same device size (2*W/L) and split the current into two halves. There are two switches 610.2 and 610.3 connecting to Bit 1 current source 610.1 but only switch 610.2 is controlled by input data D[1]. Only the current out of switch 610.2 is directed to output nodes OUTP/OUTN. The output of another switch 610.3 is connected to Load 2 640 which is not coupled with DAC outputs OUTP/OUTN. Note that only the current flowing to Load1 630 is associated with DAC's differential outputs OUTP/OUTN. The current flowing into Load2 640 doesn't contribute to differential voltage OUTP/OUTN. Similarly for LSB Bit 0, there are four switches 620.2, 620.3, 620.4 and 620.5 connecting to current source device 620.1 but only the output of switch 620.2 is connected to DAC's output node OUTP/OUTN. The outputs of other three switches are connected to Load 3 650 which is not coupled with DAC's outputs OUTP/OUTN. The currents that go to OUTP/OUTN are illustrated in solid line while the currents that don't connect to DAC outputs are illustrated in dash lines on FIG. 6.

(25) With this current splitting implementation, Bit 1 610 and Bit 0 620 use the exact same current source device dimension as Bit 2 to minimize the mismatch between these current sources. Using the exact same device dimension (W/L)*M with the same width, length and multiple number ensures these devices can be placed right next to each other during layout and they are surrounded in the same physical environment and pattern. Using the exact size dimension will minimize the difference between these current sources and a good matching characteristic can be achieved during IC fabrication.

(26) Instead of reducing the device size and introducing mismatch, current splitting method use the same device size and diverts the needed current amount to DAC's loading elements. The unneeded current is diverted to another load which is not coupled to DAC's outputs. The overhead of the current splitting structure is some extra current since the extra amount of current is produced but not used. However, the current amount of last few less significant bits are very small and is considered negligible compared with the total DAC's full scale current.

(27) As explained in FIG. 5 earlier, the electrical characteristic looking into load elements has to be the same to equally separate the current. The equivalent resistances looking into Load 1 630 and Load 2 640 need to be the same in order to split the current equally into 2 load elements. Similarly, the equivalent resistances looking into Load 2 640 and Load 3 650 need to be the same so that only one quarter of the current from current source 620.1 is sent to DAC's outputs OUTP/OUTN.

(28) Note that there is also mismatch between two load elements. This mismatch of the load elements exists regardless of using current splitting implementation or not. The mismatch of load elements is considered as one of the mismatch sources of DAC and should be minimized in such a way that the overall DAC linearity is limited by the current source mismatch. There are multiple sources of mismatch like threshold voltage mismatch A.sub.vt and conductance parameter mismatch A.sub.β for active MOS devices NFET or PFET which are used in the current sources. However, for passive resistor load element which most DAC's use, the source of mismatch is purely the dimension difference between these elements. Also the number of load elements is only two whereas the number of unit current sources can be 2.sup.N for N-bit current steering DAC. Thus the mismatch contribution of load elements to the overall DAC's mismatch is much smaller compared with the contribution of the current sources. Besides, since the load elements only occupy a very small percentage of the total DAC layout area, the size of the load element can be sized up with the same width/length ratio to reduce the mismatch while maintaining the same resistor value.

(29) Even a good design practice of using the same dimension, same rotation, same surrounding environment has been made to minimize the mismatch of current sources, there still exists a random mismatch between devices due to lithography variation, process variations and physical gradients from IC manufacturing. This random mismatch will change the equivalent resistance of the load elements from one silicon part to another silicon part. To achieve higher accuracy of current source, further trimming can be applied on the load elements to adjust the current amount. This load trimming method is illustrated on FIG. 7. DAC's load element Load 1 720 is a fixed value load while Load 2 720 and Load 3 730 are load elements that their equivalent resistance can be adjusted. Users adjust Load 2 720 and Load 3 730 equivalent resistance respectively to match DAC's Load 1 710. By adjusting the equivalent resistance of the load, the desired current amount can be accurately obtained to minimize the DAC nonlinearity after IC is fabricated. The trimming reduces the mismatch either the mismatch is the systematic mismatch due to design or the statistical random mismatch due to process variation.

(30) FIG. 8A and FIG. 8B illustrates possible trimming structures of the load element for current steering DAC. FIG. 8A is used for NFET current sources and FIG. 8B is used for PFET current sources. The load element consists of a fixed value resistor 810 and a gate controlled PFET device 820. The PFET device 820 is biased and operated at its linear region with the resistance value described below. The total equivalent resistance R.sub.T is the sum of the two resistance values.

(31) $\begin{array}{c}{R}_T=R_1+R_{\mathrm{ds}}=R_1+\frac{1}{u_n{C}_{\mathrm{ox}}\frac{W}{L}\left(V_C-V_{\mathrm{TH}}\right)}\\ R_{\mathrm{ds}}=\frac{1}{u_n{C}_{\mathrm{ox}}\frac{W}{L}\left(V_C-V_{\mathrm{TH}}\right)}\end{array}$
is the equivalent resistance of the NFET in linear region

(32) By changing the control voltage V.sub.c, the resistance of the load element can be adjusted to be the exact desired value such that the current amount from the current splitting switch is the right value to the DAC output nodes OUTP/OUTN. The trimming on current splitting load element produces the accurate current and minimize the nonlinearity of high-resolution low power current steering DAC.

(33) Although the operations of the method herein are shown and described in a particular order, the order of the operations of the method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.

(34) In addition, although specific embodiments of the invention that have been described or depicted include several components described or depicted herein, other embodiments of the invention may include fewer or more components to implement less or more feature.

(35) Furthermore, although specific embodiments of the invention have been described and depicted, the invention is not to be limited to the specific forms or arrangements of parts so described and depicted. The scope of the invention is to be defined by the claims appended hereto and their equivalents.