Electronic Memory Devices

Abstract

A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.

Claims

1. A memory cell for storing one or more bits of information, the memory cell comprising a control gate, a source terminal and a drain terminal, a semiconductor substrate between the source and drain terminals, and a floating gate disposed between the control gate and the semiconductor substrate, which is electrically isolated from the control gate by a charge trapping barrier, and which is electrically isolated from the semiconductor substrate by a charge blocking barrier, at least one of the charge trapping barrier and the charge blocking barrier comprising a III-V semiconductor material, wherein the charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.

2. A memory cell as claimed in claim 1, wherein the charge trapping barrier comprises at least one electric potential barrier that enables the selective passage of charge carriers between the control gate and the floating gate by controlling the energy of the charge carriers in the control gate and/or floating gate, and/or by controlling the shape and/or magnitude of the at least one electric potential barrier.

3. A memory cell as claimed in claim 1, wherein the charge trapping barrier comprises at least one electric potential barrier that has a resonant energy, less than the height of the potential barrier, at which passage of charge carriers between the control gate and the floating gate is enabled.

4. A memory cell as claimed in claim 1, wherein the passage of charge carriers between the control gate and the floating gate is by resonant tunnelling, the charge trapping barrier being a resonant tunnelling barrier.

5. A memory cell as claimed in claim 1, wherein the charge trapping barrier comprises at least one electric potential barrier that enables selective intra-band passage of electrons between the control gate and the floating gate in the conduction band.

6.-8. (canceled)

9. A memory cell as claimed in claim 1, wherein the charge trapping barrier has a thickness that is greater than the thickness of the charge blocking barrier.

10.-12. (canceled)

13. A memory cell as claimed in claim 1, wherein the selective passage of charge carriers between the control gate and the floating gate, in use, is controllable by controlling the energy of charge carriers in the control gate and/or the floating gate, and/or by controlling the shape and/or magnitude of one or more electric potential barriers of the charge trapping barrier.

14. A memory cell as claimed in claim 1, wherein the passage of charge carriers between the control gate and the floating gate is controllable by the application of an electric field across the charge trapping barrier.

15. (canceled)

16. A memory cell as claimed in claim 1, wherein the charge trapping barrier is adapted to provide a substantial alignment of resonant energies of electric potential barriers when a pre-determined electric field is applied across the charge trapping barrier.

17. A memory cell as claimed in claim 1, wherein the memory cell has at least one write voltage that, when applied between the control gate and the source, causes flow of charge carriers from the control gate, through the charge trapping barrier, into the floating gate, and the memory cell has at least one erase voltage that, when applied between the control gate and the source, causes flow of charge carriers from the floating gate, through the charge trapping barrier, into the control gate.

18. A memory cell as claimed in claim 17, wherein the charge trapping barrier is adapted to prevent charge carriers from entering the floating gate, in the absence of an applied write voltage, and the charge trapping barrier is adapted to prevent charge carriers from leaving the floating gate, in the absence of an applied erase voltage.

19. (canceled)

20. A memory cell as claimed in claim 1, wherein the charge blocking barrier comprises an electric potential barrier that is greater than an electric potential barrier of the charge trapping barrier adjacent to the floating gate.

21. A memory cell as claimed in claim 1, wherein a layer of material defining that part of the charge blocking barrier that is adjacent to the floating gate is a wider band gap material than a layer of semiconductor defining that part of the charge trapping barrier that is adjacent to the floating gate.

22.-24. (canceled)

25. A memory cell as claimed in claim 1, wherein the charge blocking barrier is adapted to prevent charge carriers passing between the floating gate and a conductive channel of the semiconductor substrate or, if charge carriers are able to pass between the floating gate and the conductive channel of the semiconductor substrate, this passage of charge carriers does not modify the one or more bits of information stored by the memory cell.

26. A memory cell as claimed in claim 1, wherein the charge blocking barrier is an electric potential barrier with a height that is significantly greater than the electric potential barriers of the charge trapping barrier.

27.-32. (canceled)

33. A memory cell as claimed in claim 1, wherein the semiconductor substrate comprises a conductive channel, and the channel is a depletion mode channel.

34.-38. (canceled)

39. A method of manufacturing a memory cell for storing one or more bits of information, the method comprising the steps of: (a) providing a control gate, a source terminal and a drain terminal, and a semiconductor substrate between the source and drain terminals, and (b) providing a floating gate disposed between the control gate and the semiconductor substrate, which is electrically isolated from the control gate by a charge trapping barrier, and which is electrically isolated from the semiconductor substrate by a charge blocking barrier, wherein the charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell, and at least one of the charge trapping barrier and the charge blocking barrier comprises a III-V semiconductor material.

40. A method of manufacturing a memory cell as claimed in claim 39, wherein at least the charge trapping barrier and the floating gate are formed epitaxially.

41. A method of manufacturing a memory cell as claimed in claim 39, wherein the memory cell comprises the features of the memory cell as claimed in any preceding claim.

42. A method of operating a memory cell, the method comprising the steps of: (a) providing a memory cell as claimed in claim 1; and (b) applying an electric field across the charge trapping barrier, such that charge carriers are selectively passed between the control gate and the floating gate, through the charge trapping barrier to modify the one or more bits of information stored by the memory cell.

43. A method of operating a memory cell as claimed in claim 42, wherein a potential difference is applied between the control gate and the source terminal and/or a base terminal of the memory cell to apply an electric field across the charge trapping barrier.

44. A method of operating a memory cell as claimed in claim 43, wherein a write voltage is applied between the control gate and the source to cause flow of charge carriers from the control gate, through the charge trapping barrier, into the floating gate, and an erase voltage is applied between the control gate and the source to cause a flow of charge carriers from the floating gate, through the charge trapping barrier, into the control gate.

45. A method of operating a memory cell as claimed in claim 43, wherein a first information state is achieved when there are charge carriers stored in the floating gate, and a second information state is achieved when there are less charge carriers, or no charge carriers, stored in the floating gate.

46. A method of operating a memory cell as claimed in claim 42, wherein a read voltage is applied to the control gate of the memory cell, the read voltage being between a first threshold voltage of the memory cell in a first information state, and a second, different, threshold voltage of the memory cell in a second information state.

47. A method of operating a memory cell as claimed in claim 46, wherein the application of the read voltage results in a first current at the source and/or drain when the memory cell is in a first information state, and either a second, different current, or no or negligible current, when the memory cell is in a second information state, and the current flow between the source and the drain of the memory cell is sensed or measured, such that the information state of the memory cell is determined.

Description

DETAILED DESCRIPTION OF THE DRAWINGS

[0073] FIG. 1 is a schematic cross-sectional view of a first embodiment of a memory cell according to the invention;

[0074] FIG. 2 is a schematic cross-sectional view of a second embodiment of a memory cell according to the invention;

[0075] FIG. 3 is a schematic conduction band energy level diagram of the first and second embodiments of a memory cell according to the invention;

[0076] FIG. 4 is a plot of energy levels of the first embodiment at 0V;

[0077] FIG. 5 is a plot of energy levels of the first embodiment at a write voltage;

[0078] FIG. 6 is a plot of the probability density function and of the percentages of total probability density function area of a pair of coupled energy levels of the first embodiment at the write voltage;

[0079] FIG. 7 is a plot of energy levels of the first embodiment at an erase voltage; and

[0080] FIG. 8 is a plot of the probability density function and of the percentages of total probability density function area of a pair of coupled energy levels of the first embodiment at the erase voltage.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0081] FIG. 1 shows a schematic cross section of a first embodiment of a memory cell according to the invention, which is generally designated 10. The memory cell 10 comprises source and drain terminals 12,14, a semiconductor substrate 16 between the source and drain terminals 12,14, a base terminal 15 at the base of the semiconductor substrate 16, and a control gate 24 for inducing a change in the conductivity of a channel 17 (see FIG. 3) in the semiconductor substrate 16 between the source and drain terminals 12,14. The memory cell also comprises a floating gate 26 disposed between the control gate 24 and the semiconductor substrate 16. The passivation elements 32 are located on an upper surface of the charge blocking barrier 28, and are typically formed of a metal oxide or semiconductor oxide, or polymer, thereby protecting the charge blocking barrier 28 from damage. These aspects of the memory cell 10 are constructed in a similar manner to conventional flash memory, save for the materials used, and this construction is well known in the art.

[0082] Nevertheless, unlike conventional flash memory, in the memory cell 10 according to the invention, the floating gate 26 is electrically isolated from the control gate 24 by a charge trapping barrier 30, and the floating gate 26 is electrically isolated from the semiconductor substrate 16 by a charge blocking barrier 28. The charge trapping barrier 30 is adapted to enable the selective passage of charge carriers between the control gate 24 and the floating gate 26, in use, to modify the one or more bits of information stored by the memory cell 10. In contrast, the charge blocking barrier 28 prevents the passage of charge carriers between the floating gate 26 and the conductive channel 17 in the semiconductor substrate 16.

[0083] The semiconductor substrate 16 is formed of n-type indium arsenide (InAs), and is disposed upon a base structure 18,20,22 that enables the use of lower cost materials, and may facilitate integration into silicon-based devices. In particular, the uppermost base layer 18 of the base structure 18,20,22 is formed of gallium antimonide (GaSb), and the semiconductor substrate 16 is grown upon the uppermost base layer 18 epitaxially, for example by molecular beam epitaxy (MBE) or any other appropriate process. The uppermost base layer 18 is disposed upon an intermediate base layer 20, which is formed of gallium arsenide (GaAs), and is grown upon this layer using the interface-misfit method (IMF). The intermediate base layer 20 is disposed upon the lowermost base layer 22, which is formed of silicon (Si).

[0084] FIG. 2 shows a schematic cross section of a memory cell according to a second aspect of the invention, which is generally designated 110. This memory cell 110 has an identical construction to the memory cell 10 of the first aspect of the invention (the same reference numerals are used for corresponding features of the two embodiments), save for the semiconductor substrate 16 having a greater thickness and being formed from indium arsenide (InAs) only. This embodiment may be more expensive to manufacture, but does not require any lattice matching with a base structure. Alternative embodiments have a semiconductor substrate formed of indium arsenide (InAs), and a base structure of either gallium antimonide (GaSb) only, or a base structure having an uppermost base layer of gallium antimonide (GaSb), and a lowermost base layer of gallium arsenide (GaAs). The following description applies equally to both embodiments.

[0085] The charge blocking barrier 28 is formed of aluminium antimonide (AlSb), and is disposed upon an upper surface of the semiconductor substrate 16. The charge blocking barrier 28 has a thickness that is substantially equal to the thickness of the charge trapping barrier 30. Furthermore, as shown in FIG. 3, the charge blocking barrier 28 has an electric potential barrier that is substantially equal to the electric potential barrier of the charge trapping barrier 30.

[0086] The floating gate 26 is disposed on an upper surface of the charge blocking barrier 28, and is formed of indium arsenide (InAs). The floating gate 26 is an electrically isolated quantum well, defined between the charge trapping barrier 30 and the charge blocking barrier 28, which is suitable for retaining a finite number of charge carriers in quantised energy levels.

[0087] Situated above the floating gate 26 is the charge trapping barrier 30, which is formed of alternating layers of indium arsenide (InAs) and aluminium gallium antimonide (AlGaSb). The layers of the charge trapping barrier 30 are substantially lattice matched and have a large conduction band offset.

[0088] The control gate 24 is formed of any suitable conductive material, and is located on an upper surface of the charge trapping barrier 30. The passivation elements 32 are located on an upper surface of the charge blocking barrier 28, and are typically formed of a metal oxide or semiconductor oxide, or polymer, thereby protecting the charge blocking barrier 28 from damage.

[0089] The charge trapping barrier 30, the floating gate 26, and the charge blocking barrier 28, may be formed on the semiconductor substrate 16 by any suitable method, for example by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or chemical vapour deposition (CVD), or the like.

[0090] As shown in FIG. 3, the charge trapping barrier 30 defines electric potential barriers, which define a series of quantum wells that enable resonant tunnelling. The electric potential barriers of the charge trapping barrier 30 have resonant energies, indicated by the dotted lines in FIG. 3, which enable the passage of charge carriers at, or substantially at, that those energies through the respective electric potential barrier. The charge trapping barrier 30 is modelled to provide a substantial alignment of resonant energies of the electric potential barriers when a pre-determined electric field is applied across the charge trapping barrier 30. The charge trapping barrier 30 has a thickness that is substantially equal to the thickness of the charge blocking barrier 28.

[0091] The memory cell 10 has a write voltage that, when applied between the control gate 24 and the source 12, causes flow of electrons from the control gate 24, through the charge trapping barrier 30, into the floating gate 26. The number of electrons retained within the floating gate 26 when the electric field is removed may be dependent on the form of the floating gate 26. The memory cell 10 also has an erase voltage that, when applied between the control gate 24 and the source 12, causes flow of electrons from the floating gate 26, through the charge trapping barrier 30, into the control gate 24. During storage, the electrons are retained in the floating gate 26, and no voltage is applied to the control gate relative to the source terminal, such that the memory cell stores the one or more bits of information provided by the presence or otherwise of electrons in the floating gate 26.

[0092] The threshold voltage (V.sub.th) of the memory cell 10 is the value of the control gate-source voltage, or the control gate-base terminal voltage, when the conductivity of the conducting channel connecting the source 12 and drain 14 of the memory cell 10 becomes depleted of charge, eg only allowing the inherent leakage current. The memory cell 10 is arranged to provide a change to the threshold voltage when one or more charge carriers, eg electrons, are retained by the floating gate 26.

[0093] The memory cell 10 achieves a State “1” when there are charge carriers stored in the floating gate 26, and a State “0” when there are less charge carriers, or no charge carriers, stored in the floating gate 26. In order to read the state of the memory cell 10, a read voltage (V.sub.read) is applied to the control gate 24, the read voltage (V.sub.read) being between the first threshold voltage (V.sub.th) of the memory cell 10 in State “1”, and the second, lower, threshold voltage (V.sub.th) of the memory cell 10 in State “0”. The applied read voltage (V.sub.read) results in a first current at the source 12 and/or drain 14 when the memory cell 10 is in State “1”, and no or negligible current when the memory cell 10 is in State “0”. The device into which the memory cell is incorporated therefore includes an arrangement for sensing or measuring the current flow between the source and the drain of the memory cell.

[0094] The construction and operation of the first embodiment of the memory cell 10 of the present invention is described in more detail below, with reference to FIGS. 2 and 3.

[0095] The memory cell 10 is a depletion-mode MOSFET-type device, which is suitable for use in a NAND configuration where memory cells are connected in series. In this embodiment of the cell 10, all operations (read, write, erase) may be performed with the application of less than 3V to the cell 10.

[0096] The memory cell 10 is made using III-V compound semiconductors. III-Vs are chosen because of the possibility of changing band parameters, such as the minimum of the conduction band, by varying the composition. GaSb is chosen as the starting point for the active device as Al can be substituted for Ga to produce AlSb, which has a very large band gap, and is almost lattice matched to InAs.

[0097] The substrate 16 on which the semiconductor material is grown, for example by solid-source molecular-beam epitaxy, is undoped GaSb. On top of this, a buffer layer of GaSb is grown with a thickness of 200 nm. This is followed by 50 nm of InAs. Since the minimum of the conduction band for InAs lies below the maximum of the valence band for GaSb electrons will flow from the GaSb into the InAs forming the conductive channel (17) for reading out the device.

[0098] The charge blocking barrier 28 is formed on top of the channel 17 by 15 nm of AlSb. On top of this, the floating gate 26 is formed by the growth of 11 nm of InAs. Next, the charge trapping barrier 30 is formed by the growth of a series of AlSb and InAs layers to generate two narrow quantum wells of different sizes (3 resonant tunnelling barriers), specifically 1.8 nm of AlSb, 2.4 nm of InAs, 1.2 nm of AlSb, 3.0 nm of InAs, 1.8 nm of AlSb and 7.3 nm of InAs. The quantum wells in the charge trapping barrier 30 are narrow to increase the energies of the lowest confined states, and are different so that these states are not aligned when no voltage is applied to the device.

[0099] The last layer to be grown is 200 nm of highly n-doped InAs to form the control gate 24.

[0100] After growth, the cell 10 is processed using standard semiconductor lithography techniques. Contacts are made to the source 12, drain 14, control gate 24 and base terminal 15 for the application of voltages and to allow the passage of current through the cell 10. The cell 10 is made sufficiently large (several microns) so that passivation of surface states is not required.

[0101] When the cell 10 is not being used, no voltages are applied. In this state the large potential barrier between the floating gate 26 and the channel 17 prevents the passage of charge between them. Similarly, no charge may flow between the floating gate 26 and the control gate 24 because the energies of the confined states in the two quantum wells in the charge trapping barrier 30 are high and are not coincident with each other.

[0102] In order to write to the cell 10, the source 12 is shorted to the base terminal 15 contact (ground), and a voltage of about −1.5 V is applied between the control gate 24 and the source 12. This aligns the lowest quantum confined states in the two quantum wells that form part of the charge trapping barrier 30, such that electrons may rapidly pass into (a higher energy state of) the floating gate 26 by the process of resonant tunnelling.

[0103] In order to erase the cell 10, the source 12 is shorted to the base terminal 15 (ground), and a voltage of about +2.5 V is applied between the control gate 24 and the source 12. This aligns the lowest confined states in the floating gate 26 and the adjacent quantum wells in the charge trapping barrier 30, such that electrons may rapidly pass out of the floating gate 26 by the process of resonant tunnelling into (a higher energy state of) the other quantum well in the charge trapping barrier 30 and thereafter into the control gate 24.

[0104] In order to read the cell 10 without applying a significant voltage between the control gate 24 and the floating gate 26, which are in close proximity, and thereby avoiding the flow of charge between them, the source is not shorted to the base terminal 15. Instead, a voltage of about −0.5 V is applied between the control gate 24 and the base terminal 15, such that in the absence of charge in the floating gate 26 the carriers in the conductive channel 17 are driven into the GaSb substrate 16 giving a reading of ‘0’, and that in the presence of charge in the floating gate 26, the conductive channel 17 is significantly more conductive giving a reading of ‘1’.

[0105] A model of the first embodiment of the memory cell 10 was created in COMSOL using the Coefficient Form PDE (Partial Differential Equation) module in order to describe the changes in the conduction band offset and the coefficient in the PDE due to varying semiconductors. The top half of the structure was modelled, and the conduction band was calculated.

[0106] The channel and substrate were removed from the model while write and erase were modelled, as they were not relevant. Energy levels were plotted by finding the domain which had the largest area under the probability density function inside it. This domain would then have a horizontal line plotted at that energy, creating an energy diagram of bound states. Quantum tunnelling is shown when two domains have similar probability density function areas. The percentage difference between the two areas is calculated. If it is less than the value of percentage difference stored in a parameter, both domains will have a horizontal line plotted. This is an easy way to see when resonant tunnelling is occurring. The percentage of probability density function in a given domain can also be plotted, in order to show that an inserted carrier would correctly tunnel through the structure.

[0107] Material parameters used by the model can be seen in Table 1.

TABLE-US-00001 TABLE 1 The material parameters used in the calculation of the COMSOL model, as given in Vurgaftman (Vurgaftman, J. R. Meyer, L. R. Ram-Mohan, Band parameters for III-V compound semiconductors and their alloys, J. Appl. Phys. 89, 5815 (2001)). Parameter InAs value AlSb value Lattice constant 0.60583 nm 0.61355 nm Effective electron mass 0.026 me 0.14 me Conduction band offset −0.236 eV 1.89 eV

[0108] The lines that zigzag up and down on each diagram are the conduction band structure, set with 0 to be the valence band offset, the highest point in the valence band of InSb. This leads to a conduction band offset of InAs by −0.236 eV, as seen in FIG. 4. Due to this definition, energies are sometimes negative. These lines are useful in determining where energy levels and wave functions are localised.

[0109] No energy states in the control gate channel (furthest on the left) are plotted. Nevertheless, they are still calculated and may have an effect on the leftmost quantum well. The lengths of the domains in the structure are all integer multiples of the lattice constants a.sub.InAs and a.sub.AlSb. From left to right, the lengths are seen in Table 2. Plots for the write and erase steps were taken at particular voltages, where they displayed characteristics which would enable writing or erasing the system.

TABLE-US-00002 TABLE 2 The dimensions of the device described. The values used for lattice constants were a.sub.InAs = 0.60583 nm and a.sub.AlSb = 0.61355 nm, as seen in Table 1. Domain Length Length (4 s.f.) name (lattice constants) (nm) Control gate channel 12 a.sub.InAs  7.270 Third resonant tunnelling barrier 3 a.sub.AlSb 1.841 Second potential well 5 a.sub.InAs 3.029 Second tunnelling barrier 2 a.sub.AlSb 1.227 First potential well 4 a.sub.InAs 2.423 First tunnelling barrier 3 a.sub.AlSb 1.841 Floating gate 19 a.sub.InAs  11.51 Charge blocking barrier 25 a.sub.AlSb  15.34

[0110] The first few eigenvalues have been calculated for each energy band graph, with the probability density function and percentage difference graphs referring only to the coupled energy.

[0111] FIG. 4 shows energy levels of the system at 0V (4a-4d), showing no resonant coupling. Carriers can only tunnel out of the floating gate if they have energies equal to or above the energy level 4b in the first quantum well.

[0112] FIG. 5 shows the energy levels at the write voltage of −1.5 V (5a-5f) and where they are localised. The x axis is the displacement into the structure, and the y axis is energy. The coupled energy bands of the system (5a and 5c) are seen to stretch between the two quantum wells. This is helped due to the thinness of the middle barrier. The coupled state energy is less than the voltage across the control gate, the end of the black line on the left. This means that carriers will have enough energy to tunnel through from the left, across the coupled probability density functions. FIG. 6 plots of the probability density function of the pair of coupled energy levels and the percentages of total probability density function area for the pair of coupled energy levels. The percentage area in the floating gate for the pair of coupled energy levels is 2.3%, so carriers may tunnel into the floating gate from states 5a and 5c. Since floating gate states 5d to 5f are at lower energies than 5a and 5c, carriers can relax to those lower energy states and will remain in the floating gate.

[0113] FIG. 7 shows the energy levels at the erase voltage of 2.5 V (7a-7d) and where they are localised. There is coupling between the floating gate (energy level 7c) and the first quantum well (energy level 7b), as seen in FIG. 7. This indicates that carriers will move from the floating gate into the first quantum well. As the coupling is taking place with the lowest energy level in the floating gate, all carriers can potentially be removed from the floating gate.

[0114] FIG. 8 is a plot of the probability density function of the coupled energy levels at the erase voltage and of the percentages of total probability density function area for the coupled energy levels at the erase voltage. It can be seen that a small part of the wavefunction of the coupled states 7b and 7c is present in the second quantum well, and that there is a lower energy state 7a for carriers to relax to, assuring efficient removal of charge from the floating gate.