INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING

Abstract

A technique for making high performance low noise amplifiers, low cost high performance RF, microwave circuits and other devices by using a minimum of costly high performance semiconductors is described. By combining a single discrete portion of an expensive semiconductor with a less expensive GaAs carrier, MMIC devices with improved performance over their discrete counterparts are achieved.

Claims

1. An integrated circuit module comprising: a first portion; and a second portion, the first portion having at least one first discrete component, the second portion having a carrier integrated circuit, in which the first portion is mounted on the second portion.

2. An integrated circuit module according to claim 1, in which the first portion comprises: first amplifier means, and the second portion comprises: second amplifier means, the first amplifier means having a small gate size and the second amplifier having means for second stage amplification.

3. An integrated circuit module according to claim 1, in which the first portion comprises: an FET having a first smaller size suitable for low noise amplification, and the second portion comprises: a GaAs MMIC carrier chip having optical gates of a second larger gate size.

4. An integrated circuit module according to claim 1, in which the first portion comprises: discrete PIN diodes, and the second portion comprises: a GaAs carrier chip having RF switching means.

5. A method of manufacturing an integrated circuit module, comprising: (a) manufacturing a first portion of the a semiconductor circuit of the integrated circuit; (b) manufacturing a second portion of the semiconductor circuit having a carrier integrated circuit; and (c) mounting the first portion on the second portion.

6. A method according to claim 5, in which the manufacturing step (b) comprises: manufacturing an amplifier with a first smaller gate size, and the manufacturing step (b) comprises: manufacturing a carrier chip having a second stage amplifier with a second gate size larger than that in the first portion.

7. A method according to claim 5, in which the manufacturing step (a) comprises: manufacturing at least one PIN diode, and the manufacturing step (b) comprises: manufacturing a carrier chip having a GaAs FET incorporated into a carrier MMIC.

8. An integrated circuit module according to claim 1, in which the first portion comprises: an InP or GaAs substrate, and the second portion comprises: a GaAs MMIC.

9. An integrated circuit module according to claim 2, in which the first portion comprises: an FET having a first smaller size suitable for low noise amplification, and the second portion comprises: a GaAs MMIC carrier chip having optical gates of a second larger gate size.

10. A method according to claim 5, in which the first portion comprises: an InP or GaAs substrate, and the second portion comprises: a GaAs MMIC.

Description

[0020] The invention will now be described with reference to the accompanying diagrammatic drawings in which:

[0021] FIG. 1 is a schematic diagram of a composite very low noise discrete (small size) FET mounted on a low cost GaAs carrier chip; and

[0022] FIG. 2 is a schematic diagram of an LNA/PIN diode based high power RF switch/microwave limiter protection circuit as a first portion mounted on a GaAs carrier circuit second portion.

[0023] As can be seen in FIG. 1, a discrete FET 1 is mounted on a larger carrier chip 2. The FET 1 may be a 0.1 um InP/GaAs FET and the carrier chip may be a 0.3 um GaAs low cost carrier chip. It will, however, be appreciated that any other suitable alternatives are envisaged. The carrier chip 2 provides match and bias circuitry and less critical 2nd stage amplification, and may include other components such as further FETs, plus passive components such as resistors, inductors and capacitors.

[0024] The FET 1 is manufactured from GaAs or InP and, in order to achieve low noise, the gate size needs to be very small which is achievable using these materials and high cost fabrication techniques. The substrate material and/or manufacturing process for this part of the module may be very complex in order to achieve the required circuit characteristics as, for example, in the case of 0.1 um gate InP, or low volume in the case of 0.07 um GaAs mHEMT.

[0025] The GaAs carrier chip 2 may be manufactured via lower cost or simpler GaAs processes, for example, and optical gates≧0.25 um may be fabricated on large volume 6″ wafers, for example WIN 25-20 pHEMT, RFMD FD30 pHEMT, TriQuint TQP 25.

[0026] For example only a simplified description of the manufacture of a GaAs MESFET is outlined below. It will be appreciated that this is for example only and should not be considered as the only method of manufacture.

[0027] Firstly an active layer is grown on a semi insulating wafer, the active layer being a Si doped conductive layer grown on an insulating substrate. Next an isolated mesa is formed for the active devices and ohmic contacts are added, for example FET source and drain and diode contacts. Next the gate channel is etched and the gate metal deposited then the metal bottom layer interconnect that forms, for example capacitor bottom plates and inductors. Then dielectric deposition is performed, for example using silicon nitride insulation, then a further metal layer is deposited that will form for example capacitor top plates and further inductors. Then die passivation in silicon nitride occurs and finally back face processing is undertaken including wafer thinning and adding vias by etching through the substrate.

[0028] The invention will now be described in relation to a second specific embodiment as shown in FIG. 2.

[0029] In this second embodiment of the invention an expensive existing ceramic hybrid module in an ESCAN radar was replaced with lower cost components whilst keeping to, or reducing, a predetermined module footprint. In this embodiment, reducing the footprint was key to achieving a reduced antenna element spacing required for wideband, high frequency operation.

[0030] The module includes a combined microwave limiter, low noise amplifier (LNA) and high power RF switch in a low cost package. In the present embodiment a 3-D microwave assembly married to GaAs technology and custom low cost packaging was utilised.

[0031] As shown in FIG. 2, a custom GaAs MMIC LNA is co-designed with a PIN diode based high power RF switch and microwave limiter protection circuit. Normally the RF switch and limiter would be realised on a ceramic substrate with discrete transmission lines, resistors, decoupling capacitors and bias circuits. However, in the present embodiment, the passive components including resistors, capacitors, and inductors for bias circuits are implemented directly on a GaAs carrier chip 20. The separately formed silicon limiter and switch PIN diodes are mounted conductively on and bonded to the GaAs IC 20 by gold wires 21.

[0032] The limiter/LNA/switch assembly may then be mounted in low cost LCP packaging with other GaAs ICs (HPA/LNA) with 50% of the PCB footprint and ˜30% of the cost of a conventional implementation.

[0033] Although a novel technology solution, the embodiment described above has been shown to generate significant a cost reductions in radar applications. For EW Array applications the approach also demonstrates size, weight power and cost advantages.

[0034] Advantageously, the semiconductor modules described above such as the LNA or “Front-end” circuit for an ESCAN radar system described above and the method of their manufacture make them compatible with low cost packaging schemes such as plastic or ceramic Quad Flatpack No-leads (QFN)—a style of plastic (or lower cost ceramic) packaging.

[0035] In this way, a semiconductor module may be produced that is low cost and of small size but has operating performance of the high cost custom manufactured semiconductor modules currently available.

[0036] It will be appreciated that the invention is not limited to the two embodiments described above. Any part of a semiconductor module, such as GaAs FETs, Si diodes (PIN, varactor, schottky etc), GaN FETs Silicon bipolar transistors that cannot be incorporated into a “carrier” MMIC, or where doing so would be expensive, can be “piggy backed” on top of the carrier chip if circuit performance advantage (and cost advantage) can be obtained by the combining of the two or more different elements.

[0037] Furthermore, the invention is not limited to limiters. Indium phosphide and GaAs mHEMT technology with 0.1 um gate geometry make superb low noise amplifiers with unbeatable noise figures currently but are very expensive processes to make in integrated circuits, while 0.3 um pHEMT is a low cost GaAs process made in high volume (6″ wafers) but having poorer noise figure. It is envisaged that the above technique would allow combination of the two in the form of a low noise InP or GaAs mHEMT discrete transistor for the amplifier 1st stage ‘piggy backed’ on a 0.3 um GaAs pHEMT carrier MMIC.

[0038] It will be appreciated that there are many further applications that the present invention anticipates and the embodiments only provide examples of a technique with wider applications.