THREE-TERMINAL ATOMIC SWITCHING DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M.sub.8XY.sub.6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M.sub.8XY.sub.6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.

Claims

1. A three-terminal atomic switching device, comprising: a stack structure comprising a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M.sub.8XY.sub.6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M.sub.8XY.sub.6 channel layer, and the control terminal fills the vertical trench.

2. The three-terminal atomic switching device according to claim 1, wherein in the stack structure comprising the source terminal and the drain terminal, the drain terminal is formed on the source terminal, and the source terminal is isolated from the drain terminal by a second insulating dielectric layer, and the drain terminal is further covered with a third insulating dielectric layer, and the source terminal is isolated from a substrate by a first insulating dielectric layer thereunder.

3. The three-terminal atomic switching device according to claim 2, wherein, the source terminal and the drain terminal are made of any conductive material selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO, or IZO, or an alloy of any two or more conductive materials selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO; the source terminal and the drain terminal are formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering with a thickness of 1 nm to 500 nm.

4. The three-terminal atomic switching device according to claim 2, wherein the vertical trench penetrates through the third insulating dielectric layer covering the drain terminal, the drain terminal, the second insulating dielectric layer between the source terminal and the drain terminal, and the source terminal in this order, wherein, the bottom of the vertical trench is formed in the first insulating dielectric layer below the source terminal.

5. The three-terminal atomic switching device according to claim 1, wherein in the M.sub.8XY.sub.6 channel layer formed on the inner wall and the bottom of the vertical trench, M is any one of Cu, Ag, Li, Ni or Zn, X is any one of Ge, Si, Sn, C or N, and Y is any one of Se, S, O, or Te.

6. The three-terminal atomic switching device according to claim 5, wherein the M.sub.8XY.sub.6 channel layer comprises a M.sub.8XY.sub.6 material, doped with one or more of N, P, Zn, Cu, Ag, Li, Ni, Zn, Ge, Si, Sn, C, N, Se, S, O, Te, Br, Cl, F, or I.

7. The three-terminal atomic switching device according to claim 1, wherein the M.sub.8XY.sub.6 channel layer is formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering with a thickness of 1 nm to 500 nm.

8. The three-terminal atomic switching device according to claim 1, wherein the control terminal is formed in the vertical trench with the inner wall thereof covered with the M.sub.8XY.sub.6 channel layer, and a top surface of the control terminal is flushed with a top surface of the third insulating dielectric layer covering the drain terminal.

9. The three-terminal atomic switching device according to claim 1, wherein, the control terminal is made of any conductive material selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO, or IZO, or an alloy of any two or more conductive materials selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO; the control terminal is formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering.

10. The three-terminal atomic switching device according to claim 1, further comprising one or more dielectric layers between the M.sub.8XY.sub.6 channel layer and the control terminal, which are formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering with a thickness of 0.5 nm to 50 nm.

11. The three-terminal atomic switching device according to claim 10, wherein the dielectric layer is made of any one selected from an inorganic material of CuS, AgS, AgGeSe, CuI.sub.xS.sub.y, ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, WO.sub.x, NiO, CuO.sub.x, ZnO, TaO.sub.x, CoO, Y.sub.2O.sub.3, Si, PCMO, SZO or STO, or any one selected from an organic material of TCNQ, PEDOT, P.sub.3HT, PCTBT, and the like.

12. A method of manufacturing a three-terminal atomic switching device, comprising: forming a stack structure comprising a source terminal and a drain terminal; etching the stack structure to form a vertical trench; forming an M.sub.8XY.sub.6 channel layer on an inner wall and a bottom of the vertical trench; and forming a control terminal on a surface of the M.sub.8XY.sub.6 channel layer, wherein the control terminal fills the vertical trench

13. The method according to claim 12, wherein the step of forming a stack structure comprising a source terminal and a drain terminal comprises forming firstly a first insulating dielectric layer on a substrate, and then, forming the source terminal on the first insulating dielectric layer, and then, forming a second insulating dielectric layer on the source terminal, and then, forming the drain terminal on the second insulating dielectric layer, and finally, forming a third insulating dielectric layer on the drain terminal, thus forming the stack structure comprising the source terminal and the drain terminal.

14. The method according to claim 13, wherein the source terminal and the drain terminal are formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering, and the first to third insulating dielectric layers are formed by chemical vapor deposition or sputtering.

15. The method according to claim 12, wherein the step of etching the stack structure to form a vertical trench comprises etching through the third insulating dielectric layer, the drain terminal, the second insulating dielectric layer, and the source terminal in the stack structure by photolithography and etching, and the etching stops in the first insulating dielectric layer below the source terminal.

16. The method according to claim 15, wherein the photolithography comprises conventional photolithography, electron beam exposure, or nano-imprinting, and the etching comprises dry etching or wet etching; a single step etching process is used to form the trench at one time, or alternatively a multi-step etching process is used to etch the insulating dielectric layers and the drain terminal separately.

17. The method according to claim 12, wherein the step of forming an M.sub.8XY.sub.6 channel layer on an inner wall and a bottom of the vertical trench comprises forming the M.sub.8XY.sub.6 channel layer by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.

18. The method according to claim 12, wherein the step of forming a control terminal on a surface of the M.sub.8XY.sub.6 channel layer comprises forming the control terminal in the vertical trench with the inner wall thereof covered with the M.sub.8XY.sub.6 channel layer by any one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.

19. The method according to claim 18, wherein the step of forming a control terminal 601 on a surface of the M.sub.8XY.sub.6 channel layer further comprises: planarizing the control terminal and the M.sub.8XY.sub.6 channel layer, forming a bit line for a vertical cross-array structure, thereby forming a three-terminal atomic switching device.

20. The method according to claim 19, wherein the planarizing comprises performing planarization process on the control terminal and the M.sub.8XY.sub.6 channel layer by chemical mechanical polishing to remove horizontal portions of the control terminal and the M.sub.8XY.sub.6 channel layer completely.

21. The method according to claim 12, wherein between the step of forming an M.sub.8XY.sub.6 channel layer on an inner wall and a bottom of the vertical trench and the step of forming a control terminal on a surface of the M.sub.8XY.sub.6 channel layer, the method further comprises: forming one or more dielectric layers on the surface of the M.sub.8XY.sub.6 channel layer by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering, with a thickness of 0.5 nm to 50 nm.

22. The method according to claim 21, wherein the planarizing comprises performing planarization process on the control terminal, the dielectric layer, and the M.sub.8XY.sub.6 channel layer by chemical mechanical polishing to remove horizontal portions of the control terminal, the dielectric layer, and the M.sub.8XY.sub.6 channel layer completely.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 is a schematic diagram showing a read crosstalk phenomenon in a passive cross-array structure;

[0035] FIG. 2 is a schematic structural view showing a three-terminal atomic switching device according to an embodiment of the present invention;

[0036] FIG. 3 is a flow chart showing a method of manufacturing a three-terminal atomic switching device according to an embodiment of the present invention;

[0037] FIGS. 4 to 7 are process flow charts for manufacturing a three-terminal atomic switching device according to an embodiment of the present invention;

[0038] FIG. 8 is a schematic diagram showing the relationship between a source-drain resistance and a control terminal voltage of a three-terminal atomic switching device according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0039] The invention will now be described more fully hereinafter with reference to embodiments thereof in conjunction to the accompanying drawings. The invention provides some embodiments, but should not be considered as being limited to the embodiments set forth herein. In the drawings, the thickness of layers and areas is enlarged for clarity, but those schematic diagrams should not be considered as reflecting the exact proportional relationship of the geometric size. The accompanying drawings illustrate idealized embodiments of the present invention, and the embodiments of the invention should not be considered as being limited to the specific shapes of the areas shown in the drawings, but rather comprise some shapes resulting therefrom. The drawings are illustrative, but should not be considered as limiting the scope of the invention.

[0040] The invention is based on a three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of a source-drain resistance with respect to a control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.

[0041] FIG. 2 is a schematic structural view showing a three-terminal atomic switching device according to an embodiment of the present invention. As shown in FIG. 2, the three-terminal atomic switching device comprises a stack structure including a source terminal 301 and a drain terminal 302, a vertical trench formed by etching the stack structure, an M.sub.8XY.sub.6 channel layer 501 formed on an inner wall and the bottom of the vertical trench, and a control terminal 601 formed on a surface of the M.sub.8XY.sub.6 channel layer 501. The control terminal 601 fills the vertical trench. The resistance of the source terminal 301 and the resistance of the drain terminal 302 are controlled by the control terminal 601.

[0042] In the stack structure including the source terminal 301 and the drain terminal 302, the drain terminal 302 is formed on the source terminal 301, the source terminal 301 is isolated from the drain terminal 302 by a second insulating dielectric layer 202, the drain terminal 302 is further covered with a third insulating dielectric layer 203, and the source terminal 301 is isolated from a substrate by a first insulating dielectric layer 201 thereunder.

[0043] The source terminal 301 and the drain terminal 302 are made of any conductive material selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO, or IZO, or an alloy of any two or more conductive materials selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO. The source terminal 301 and the drain terminal 302 are deposited by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering with a thickness of 1 nm to 500 nm.

[0044] The vertical trench penetrates through the third insulating dielectric layer 203 covering the drain terminal 302, the drain terminal 302, the second insulating dielectric layer 202 between the source terminal 301 and the drain terminal 302, and the source terminal 301 in this order. The bottom of the vertical trench is formed in the first insulating dielectric layer 201 below the source terminal 301.

[0045] In the M.sub.8XY.sub.6 channel layer 501 formed on the inner wall and the bottom of the vertical trench, M is any one of Cu, Ag, Li, Ni or Zn, X is any one of Ge, Si, Sn, C or N, and Y is any one of Se, S, O, or Te. The M.sub.8XY.sub.6 channel layer 501 can also comprise a M.sub.8XY.sub.6 material doped with one or more of N, P, Zn, Cu, Ag, Li, Ni, Zn, Ge, Si, Sn, C, N, Se, S, O, Te, Br, CI, F, or I. The M.sub.8XY.sub.6 channel layer 501 is deposited by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering with a thickness of 1 nm to 500 nm.

[0046] The control terminal 601 is formed in the vertical trench with the inner wall thereof covered with the M.sub.8XY.sub.6 channel layer 501, and has a top surface thereof flushed with a top surface of the third insulating dielectric layer 203 covering the drain terminal 302. The control terminal 601 is made of any conductive material selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO, or IZO, or an alloy of any two or more conductive materials selected from a metal material of W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni, or a metal compound of TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO. The control terminal 601 is formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering.

[0047] Further, as a preferred embodiment of the present invention, there may be one or more dielectric layers further included between the M.sub.8XY.sub.6 channel layer 501 and the control terminal 601. The dielectric layer(s) may be made of any one of an inorganic material of CuS, AgS, AgGeSe, CuI.sub.xS.sub.y, ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, WO.sub.x, NiO, CuO.sub.x, ZnO, TaO.sub.x, CoO, Y.sub.2O.sub.3, Si, PCMO, SZO or STO, or any one of an organic material of TCNQ, PEDOT, P.sub.3HT, PCTBT, and the like. The dielectric layer(s) may be deposited by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering with a thickness of 0.5 nm to 50 nm.

[0048] Based on the three-terminal atomic switching device shown in FIG. 2, the present invention also provides a method of manufacturing the three-terminal atomic switching device as shown in FIG. 3, which comprises the steps of:

[0049] Step 10: forming a stack structure comprising a source terminal 301 and a drain terminal 302;

[0050] This step comprises forming firstly a first insulating dielectric layer 201 on a substrate, and then, forming a source terminal 301 on the first insulating dielectric layer 201, and then, forming a second insulating dielectric layer 202 on the source terminal 301, and then, forming a drain terminal 302 on the second insulating dielectric layer 202, and finally, forming a third insulating dielectric layer 203 on the drain terminal 302, thus forming the stack structure including the source terminal 301 and the drain terminal 302. The source terminal 301 and the drain terminal 302 are deposited by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering, and the first to third insulating dielectric layers are formed by chemical vapor deposition or sputtering.

[0051] Step 20: etching the stack structure to form a vertical trench;

[0052] This step comprises etching through the third insulating dielectric layer 203, the drain terminal 302, the second insulating dielectric layer 202, and the source terminal 301 in the stack structure by using photolithography and etching. The etching stops in the first insulating dielectric layer 201 below the source terminal 301. The photolithography comprises conventional photolithography, electron beam exposure, or nano-imprinting, and the etching comprises dry etching or wet etching. A single step etching process can be used to form the trench at one time, or alternatively a multi-step etching process can be used to etch the insulating dielectric layers and the drain terminal separately.

[0053] Step 30: forming an M.sub.8XY.sub.6 channel layer 501 on an inner wall and the bottom of the vertical trench;

[0054] This step comprises depositing the M.sub.8XY.sub.6 channel layer 501 by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.

[0055] Step 40: forming a control terminal 601 on a surface of the M.sub.8XY.sub.6 channel layer 501 to fill up the vertical trench;

[0056] this step comprises forming the control terminal 601 in the vertical trench with the inner wall thereof covered with the M.sub.8XY.sub.6 channel layer by any of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.

[0057] Further, forming the control terminal 601 on the surface of the M.sub.8XY.sub.6 channel layer 501 further comprises planarizing the control terminal 601 and the M.sub.8XY.sub.6 channel layer 501, forming a bit line for a vertical cross-array structure, thereby forming a three-terminal atomic switching device. The planarizing comprises performing planarization process on the control terminal 601 and the M.sub.8XY.sub.6 channel layer 501 by chemical mechanical polishing to remove horizontal portions of the control terminal 601 and the M.sub.8XY.sub.6 channel layer 501 completely.

[0058] Further, between the step 30 and the step 40, the method further comprises forming one or more dielectric layers on the surface of the M.sub.8XY.sub.6 channel layer 501 by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering, with a thickness of 0.5 nm to 50 nm. The planarizing comprises performing planarization process on the control terminal 601, the dielectric layer, and the M.sub.8XY.sub.6 channel layer 501 by chemical mechanical polishing to remove horizontal portions of the control terminal 601, the dielectric layer, and the M.sub.8XY.sub.6 channel layer 501 completely.

[0059] As a preferred embodiment, the manufacture process of the three-terminal atomic switching device of the present invention will be described in detail with reference to FIGS. 4 to 7, which specifically includes the steps of:

[0060] Step 1: manufacturing a source terminal and a drain terminal.

[0061] As shown in FIG. 4, this step comprises forming a source terminal 301 and a drain terminal 302 in a stack structure on a Si substrate 100 in this order, and isolating, by insulating dielectrics, the Si substrate 100 from the source terminal 301 and also the source terminal 301 from the drain terminal 302. As a preferred embodiment, the Si substrate 100 and the source terminal 301 are isolated from each other by a first insulating dielectric layer 201, and the source terminal 301 and the drain terminal 302 are isolated from each other by a second insulating dielectric layer 202, and the drain terminal 302 is covered with a third Insulating dielectric layer 203.

[0062] The source terminal 301 and the drain terminal 302 may be formed by chemical plating or sputtering. As a preferred embodiment, the material used in the source terminal 301 and the drain terminal 302 in this embodiment is a conductive electrode of metal W, and is formed by sputtering with a thickness of 5 nm to 100 nm.

[0063] The first to third insulating dielectric layers 201, 202, 203 may be formed by chemical vapor deposition or sputtering, and the material used may comprise SiN, SiO, SiON, or SiO.sub.2, or SiO.sub.2 doped with C, P or F. As a preferred embodiment, the first to third insulating dielectric layers 201, 202, and 203 are formed of SiO.sub.2 by chemical vapor deposition with a thickness of 10 nm to 100 nm.

[0064] Step 2: etching a vertical trench.

[0065] As shown in FIG. 5, this step comprises etching the third insulating dielectric layer 203, the drain terminal 302, the second insulating dielectric layer 202, the source terminal 301 and the first insulating dielectric layer 201 by photolithography and etching, and the terminal 301 is etched through and the first insulating dielectric layer 201 is not etched through to form a vertical trench 401. In this step, the photolithography may comprise conventional photolithography, electron beam exposure, nano-imprinting or other pattern transfer technology. The etching may comprise dry etching or wet etching. For the etching of the multiple layers, a single step etching process can be used to form the trench at one time, or alternatively a multi-step etching process can be used to etch the insulating dielectric layers and the drain terminal separately.

[0066] Step 3: forming an M.sub.8XY.sub.6 channel layer 501 in the trench 401.

[0067] As shown in FIG. 6, as a preferred embodiment, a material used for the M.sub.8XY.sub.6 channel layer 501 may be Cu.sub.8GeS.sub.6 or Ag.sub.8GeS.sub.6, and the M.sub.8XY.sub.6 channel layer 501 may be deposited by single target sputtering or multi-target co-sputtering with a thickness of 5 nm to 200 nm.

[0068] Step 4: forming a control terminal 601 on the M.sub.8XY.sub.6 channel layer 501 in the trench 401.

[0069] As shown in FIG. 7, as a preferred embodiment, a material used for the control terminal 601 may be a multilayer composite electrode of one or more of Ti, TiN, Ta, TaN, Ru, or Cu, and the control terminal 601 may be manufactured by sputtering, atom Chemical vapor deposition, or plating with a thickness of 10 nm to 1000 nm.

[0070] Step 5: planarizing the control terminal 601 and the M.sub.8XY.sub.6 channel layer 501.

[0071] This step comprises performing planarization on the control terminal 601 and the M.sub.8XY.sub.6 channel layer 501 by chemical mechanical polishing, to remove of a horizontal portion of the control terminal 601 of completely removed, and also remove a horizontal portion of the M.sub.8XY.sub.6 channel layer 501 partially. Thus, the patterning of the bit line is completed, as shown in FIG. 2.

[0072] Thereby, the vertical cross-array structure with a self-gating functionality for a resistive memory shown in FIG. 2 is completed.

[0073] Further, as another preferred embodiment, there may be one or more dielectric layers further provided between the M.sub.8XY.sub.6 channel layer 501 and the control terminal 601. The one or more dielectric layers are deposited by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering with a thickness of 0.5 nm to 50 nm after forming the M.sub.8XY.sub.6 channel layer 501 in the trench 401 in step 3. Thus, the above-described step 4 of forming a control terminal 601 on the M.sub.8XY.sub.6 channel layer 501 in the trench 401 comprises forming the control terminal 601 on the dielectric layer(s) in the trench 401, and detailed descriptions thereof will be omitted here.

[0074] Preferably, the dielectric layer may be any selected from an inorganic material of CuS, AgS, AgGeSe, CuI.sub.xS.sub.y, ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, WO.sub.x, NiO, CuO.sub.x, ZnO, TaO.sub.x, CoO, Y.sub.2O.sub.3, Si, PCMO, SZO, or STO, or any organic material.

[0075] Many different embodiments may be made without departing from the spirit and scope of the invention. It is to be understood that the invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

[0076] FIG. 8 is a schematic diagram showing the relationship between the control terminal voltage and the channel resistance of the three-terminal atomic switching device of the present invention. As shown in FIG. 8, the channel resistance of the three-terminal atomic switching device starts with a high-impedance state, i.e., the ‘off’ state. When the control terminal voltage reaches 0.7 V, the channel resistance decreases rapidly, and thus the device becomes ‘open’ state. When the control terminal voltage gradually reduces to 0.2V, the source-drain resistance increases rapidly, and thus the device becomes ‘off’ state again. The switching ratio of the three-terminal atomic switching device can reach more than 10.sup.5, and thus the read crosstalk of the cross-array structure can be effectively inhibit to avoid misreading occurring.

[0077] In the foregoing detailed description, the objects, technical solutions and advantages of the invention has been further described in detail. It is to be understood that the foregoing description provides only some specific embodiments of the invention and is not intended to limit the invention. Any modifications, equivalents, improvements, and the like without departing from the spirit and principle of the invention are intended to be included within the scope of the present invention.