Thyristor Memory Cell with Assist Device

Abstract

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Claims

1. A vertical thyristor memory array comprising: A vertical thyristor memory cell, the vertical thyristor memory cell comprising: a p+ anode; an n-base disposed below the p+ anode; a p-base disposed below the n-base; a n+ cathode disposed below the p-base; an isolation trench disposed around the vertical thyristor memory cell; an assist gate disposed in the isolation trench around the n-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the n-base.

2. The vertical thyristor memory array of claim 5 wherein the assist gate comprises PMOS.

3. The vertical thyristor memory array of claim 1 wherein the assist gate runs orthogonal to the bit lines.

4. The vertical thyristor memory array of claim 1 wherein the assist gate runs parallel to the word lines.

5. A vertical thyristor memory array comprising: A vertical thyristor memory cell, the vertical thyristor memory cell comprising: a p+ anode; an n-base disposed below the p+ anode; a p-base disposed below the n-base; a n+ cathode disposed below the p-base; an isolation trench disposed around the vertical thyristor memory cell; an assist gate disposed in the isolation trench around the p-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the p-base.

6. The vertical thyristor memory array of claim 3 wherein the assist gate comprises NMOS.

7. The vertical thyristor memory array of claim 5 wherein the assist gate runs orthogonal to the bit lines.

8. The vertical thyristor memory array of claim 5 wherein the assist gate runs parallel to the word lines.

9. The vertical thyristor memory array of claim 5 wherein the assist gate is disposed completely around the p-base.

10. The vertical thyristor memory array of claim 5 wherein the assist gate is disposed partially in segments around the p-base.

11. The vertical thyristor memory array of claim 1 wherein the assist gate is disposed completely around the n-base.

12. The vertical thyristor memory array of claim 1 wherein the assist gate is disposed partially in segments around the n-base.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a plane view of a layout of a 2×2 vertical thyristor memory cell array as implemented in an integrated circuit according to an embodiment of a claimed invention.

[0017] FIG. 2A illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with a PMOS assist gate parallel to word line according to an embodiment of a claimed invention.

[0018] FIG. 2B illustrates a perspective view of perpendicular cross-sections of a thyristor memory cell with an NMOS assist gate parallel to word line according to an embodiment of a claimed invention.

[0019] FIG. 3A illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with a PMOS assist gate parallel to bit line according to an embodiment of a claimed invention.

[0020] FIG. 3B illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with an NMOS assist gate parallel to bit line according to an embodiment of a claimed invention.

[0021] FIG. 4 illustrates doping profile of a vertical thyristor according to an embodiment of a claimed invention.

[0022] FIG. 5 illustrates cross-section of vertical thyristor with NMOS assist gate located below upper edge and above lower edge of p-base according to an embodiment of a claimed invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] This invention discloses position of an assist gate relative to an upper edge and a lower edge of a base of a vertical thyristor memory cell in an array.

[0024] FIG. 1 shows a plane view of a layout of a 2×2 vertical thyristor memory cell array as implemented in an integrated circuit according to an embodiment of a claimed invention.

[0025] The four vertical thyristors, including anodes, are located at the corners of the layout. The thyristors are separated in two perpendicular directions with trenches filled with oxide.

[0026] A first set of parallel conductive lines provides a word line for each row of the memory array by being coupled to the cathodes of the thyristors in the row. A second set of parallel conductive lines provides a bit line for each column of the memory array by being coupled to the anodes of the thyristors in the column. The word lines are perpendicular to the bit lines.

[0027] FIG. 4 shows doping profile of a vertical thyristor according to an embodiment of a claimed invention. The doping concentration varies as a function of depth below the upper surface. In an embodiment of the present claimed invention, some peaks may include a shoulder (not shown). The dose may have a tolerance of +/−6% while the ion implantation energy may have a tolerance of +/−2%.

[0028] In an embodiment, an assist device, such as a gate, such as PMOS or NMOS, may be formed next to the sidewalls of the isolation trenches adjacent the thyristor. The assist gates may increase write speed and may reduce write voltage.

[0029] The sidewalls of the trench are oxidized, thus forming the gate oxide that isolates the gate electrodes from the doped regions. In an embodiment of the present claimed invention, the gate oxide may have a thickness of 3.0 (+/−0.3) nm.

[0030] The trenches are then partially filled with silicon dioxide, such as by a chemical vapor deposition process.

[0031] Then a conformal doped-polycrystalline silicon layer is deposited over the structure.

[0032] An anisotropic etching step removes the entire conformal polycrystalline silicon layer except for a desired thickness to form a gate (control) line that includes the assist gate.

[0033] Then, another trench filling operation is performed to finish filling the trenches.

[0034] Planarization steps are then performed, such as by using chemical mechanical polishing or other techniques.

[0035] Later, an electrical connection is made to couple the gate (control) lines.

[0036] As shown in FIG. 2(a), a PMOS assist gate 80 may be positioned adjacent to the n-base of the vertical thyristor. The PMOS assist gate 80 may run parallel to the word lines. The word lines may be buried and connected with a conductor in (and through) the isolation trench.

[0037] As shown in FIG. 2 (b), an NMOS assist gate 86 may be positioned adjacent to the p-base of the vertical thyristor. The PMOS assist gate 86 may run parallel to the word lines. The word lines may be buried and connected with a conductor in (and through) the isolation trench.

[0038] As shown in FIG. 3(a), a PMOS assist gate 80 may be positioned adjacent to the n-base of the vertical thyristor. The PMOS assist gate 80 may run parallel to the bit lines. The bit lines may include an overlying M1.

[0039] As shown in FIG. 3(b), an NMOS assist gate 86 may be positioned adjacent to the p-base of the vertical thyristor. The PMOS assist gate 86 may run parallel to the bit lines. The bit lines may include an overlying M1.

[0040] In an embodiment of the present claimed invention, the p-base may have a height of 110.0 (+/−11.0) nm.

[0041] In an embodiment of the present claimed invention, the NMOS assist gate may have a gate length (vertical height) of 55.0 (+/−5.5) nm.

[0042] As shown in an embodiment of the present claimed invention in FIG. 5, an upper edge of the NMOS assist gate may be positioned about 30.5 (+/−3.0) nm below an upper edge of the p-base.

[0043] As shown in an embodiment of the present claimed invention in FIG. 5, a lower edge of the NMOS assist gate may be positioned about 24.5 (+/−2.5) nm above an upper edge of the p-base.

[0044] In other embodiments, the assist gates may be formed (not shown)—partially, in separate segments, or completely—around the vertical thyristor.

[0045] In other embodiments, the sidewall gates 80, 86 may be formed from other conductive material, such as metal, such as tungsten, or silicide(s), or combinations of different materials.

[0046] In an embodiment of the present claimed invention, p+ anodes are connected to bit lines (M1 layer) while n+ anodes are connected to word lines (M2 layer straps between drops for about every 32 vertical thyristors) are connected to N+ cathodes.

[0047] This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.