DISCRETE DYNODE ELECTRON MULTIPLIER FABRICATION METHOD

Abstract

A process of fabricating a discrete-dynode electron multiplier (DDEM) including the steps of mounting an insulator block to a conductor block, and forming a series of ion-optics geometrical structures in the conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter. The forming step may be performed by electrical discharge machining (EDM), laser cutting, and/or water jet cutting.

Claims

1. A process of manufacturing a discrete-dynode electron multiplier (DDEM) comprising the steps of: mounting an insulator block to a monolithic conductor block; and forming a series of ion-optics geometrical structures in the monolithic conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter.

2. The process of claim 1, wherein the forming step is performed by electrical discharge machining (EDM), laser cutting, and/or water jet cutting.

3. The process of claim 1, wherein the series of ion-optics geometrical structures comprise a series of alternating fingers and slots in the monolithic conductor block.

4. The process of claim 3, wherein one of the fingers and/or slots is curved in a direction along the smallest dimension.

5. The process of claim 1, wherein the mounting step comprises either bonding or brazing the conductor block to the insulator block.

6. The process of claim 1, wherein the step of forming further comprises the step of forming an opening in the conductor block.

7. The process of claim 6 further comprising mounting a circuit board to the DDEM by positioning a fastener through the opening in the conductor block and through an opening in the circuit board.

8. The process of claim 1, wherein the forming step comprises forming two separate conductors from the monolithic conductor block.

9. The process of claim 1, wherein the mounting step further comprises mounting the insulator block to one side of the conductor block and mounting a second insulator block to an opposing side of the conductor block.

10. The process of claim 9 wherein the forming step follows the mounting step.

11. The process of claim 1, wherein following the forming step, the method further comprises the step of applying a secondary electron emissive layer to exposed surfaces of the conductor block.

12. A process of manufacturing a discrete-dynode electron multiplier (DDEM) comprising the steps of: mounting at least one insulator block to a monolithic conductor block; forming a series of ion-optics geometrical structures in the monolithic conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter; forming an opening in the monolithic conductor block; and connecting a circuit board to the DDEM by positioning a fastener through the opening in the monolithic conductor block and through an opening in the circuit board.

13. The process of claim 12, wherein the forming steps are performed by electrical discharge machining (EDM), laser cutting, and/or water jet cutting.

14. The process of claim 12, wherein the mounting step further comprises mounting two insulator blocks to opposing sides of the monolithic conductor block.

15. The process of claim 12, wherein the series of ion-optics geometrical structures comprise a series of alternating fingers and slots in the block of conductive material.

16. The process of claim 15, wherein one of the fingers and/or slots is curved in a direction along the smallest dimension.

17. A process of manufacturing a discrete-dynode electron multiplier (DDEM) comprising the steps of: mounting a monolithic conductor block between two insulator blocks; and forming a series of ion-optics geometrical structures in the monolithic conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter.

18. The process of claim 17, wherein the monolithic conductor block is sandwiched between the two insulator blocks.

19. The process of claim 17, wherein the mounting step comprises either bonding or brazing the conductor block to both insulator blocks.

20. The process of claim 17, wherein the DDEM has a U-shape, an L-shape, a circular shape, an annular shape, a rectangular shape or a square shape.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0015] FIG. 1 depicts a schematic view of a conventional DDEM according to the prior art.

[0016] FIG. 2 depicts an assembled view of the DDEM, according to one exemplary embodiment of the invention.

[0017] FIG. 3 depicts an exploded view of the DDEM of FIG. 2.

[0018] FIG. 4A depicts a side elevation view of the dynode arrays of the DDEM of FIG. 2.

[0019] FIG. 4B depicts a side elevation view of alternative dynode arrays for a DDEM of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0020] FIGS. 2 and 3 depict assembled and exploded views, respectively, of a discrete-dynode electron multiplier (DDEM) 10, according to one exemplary embodiment of the invention. DDEM 10 generally comprises a first anode array 12 spaced apart from a second anode array 14, and two circuit boards 16 and 18 that are fixedly mounted on opposing sides of the first anode array 12 and the second anode array 14 by four fasteners 20 and corresponding nuts 22 and washers 24.

[0021] FIG. 4A depicts a side elevation view of the dynode arrays 12 and 14 of the DDEM 10. Arrays 12 and 14 together form an input 34 at one end of DDEM 10 through which ions (electrons) are distributed into DDEM 10, and an output (anode) 36 at an opposite end of DDEM 10 at which the ions (electrons) are collected.

[0022] Each dynode array 12 and 14 includes an insulator 26 and a conductor 30 that is mounted to the insulator 26. Either one or both conductors 30 may be formed from a single, unitary, monolithic block of conductive material, such as KOVAR®, for example. In other words, the conductors 30 of both arrays 12 and 14 may be formed from the same single, unitary, monolithic block of conductive material. Insulators 26 may be formed of any insulative material known to those skilled in the art, such as ceramic, for example.

[0023] Each insulator 26 has a series of slots 28 (9 shown) that are uniformly disposed on the side of the insulator 26 that faces the conductor 30. Each slot 28 extends along the entire depth ‘D’ of the insulator 26, and along a portion of the width ‘W’ of the insulator 26.

[0024] Each conductor 30 includes a series of ion-optics geometrical structures in the form of alternating fingers 32 and kerfs 33 (i.e., channels or slits). Each finger 32 is a thin slice of metal that extends along the entire depth ‘D’ of the conductor 30, and along at least a portion of the width ‘W’ of the conductor 30. The length of each finger 32 may vary. Each finger 32 extends from the emission surface 35 of the conductor 30 by a defined angle ‘A’ (e.g., from 0 to 90 degrees). Each finger 32 may be substantially straight (see the fingers 32 at the inlet end 34) or it may be curved (e.g., see the finger 32 at the outlet end 36 of array 14). The smallest dimension t.sub.1 of each finger 32 may be less than 1 millimeter.

[0025] Each kerf 33 extends along the entire depth ‘D’ of the conductor 30, and along at least a portion of the width ‘W’ of the conductor 30. The base of each kerf 33 is substantially aligned with a respective slot 28 of the insulator 26. Each kerf 33 may be substantially straight, bi-directional (e.g., see the kerf 33 at the inlet end of array 14), or curved, for example. The smallest dimension t.sub.2 of each kerf 33 may be less than 1 millimeter.

[0026] The position and geometrical structure (i.e., size and shape) of the fingers 32 and kerfs 33 are tailored to achieve a desired result, such as splitting electrons for dual mode applications or achieving rapid electron pulse response for applications where timing may be critical. The geometrical structure is designed to reduce ion feedback, while the rest of the dynode structure is designed to maximize electron transmission. It should be understood that the position and geometrical structure of the fingers 32 and kerfs 33 can vary greatly. FIG. 4B, for example, depicts a side elevation view of alternative dynode arrays 12′ and 14′ for a DDEM including conductor channels 32′ and kerfs 33′ having their own unique geometries.

[0027] Two openings 38 are disposed on opposing sides of each conductor 30, through which the fasteners 20 are inserted upon assembling DDEM 10. Each circuit board 16 and 18 also includes openings either at or near all four corners for receiving the fasteners 20. The holes in the circuit board 16 and 18 and the conductors 30 are positioned and sized for precision alignment of the arrays 12 and 14 with respect to one another such that the distance ‘D’ (see FIG. 4A) between the conductors 30 is maintained at a tight tolerance.

[0028] A secondary electron emissive layer 31 is applied to the exterior surfaces of conductors 30 including the emission surfaces 35. The layer 31 is capable of generating secondary electrons with a coefficient of greater than one. The layer 31 may be composed of Al.sub.2O.sub.3, MgO, or SiO.sub.2, for example. The layer 31 could be applied to the exposed surfaces of conductors 30 by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), for example, or the layer 31 may be a thermally grown oxide. Another layer of metal material could be deposited onto the exposed surfaces of conductors 30 prior to depositing the emissive layer in order to enhance the performance of the DDEM 10.

[0029] Two circuit boards 16 and 18 are mounted to opposing length-wise sides of the arrays 12 and 14 such that the circuit boards 16 and 18 face each other in the assembled configuration of DDEM 10. The circuit boards 16 and 18 may be composed of ceramics, glass epoxy, or any other material known to those skilled in the art.

[0030] The circuit created by circuit boards 16 and 18 provides an electric field in operation. An electrical circuit driver including a chain of resistors are fabricated on circuit board 16 using active and/or passive electrical components having standard or surface mount type configurations. Circuit board 18 provides an output signal connector for electron collection, which is isolated from the environment of the circuit driver of circuit board 16 to limit pick-up noise.

[0031] In lieu of circuit boards 16 and 18, a mechanical frame or series of posts may be used to connect the arrays 12 and 14, and the circuitry including the voltage divider network could be integrated directly on the insulators 26.

[0032] Also, the DDEM 10 is not limited to the rectangular shape shown. The DDEM may be circular, square, annular, U-shaped or L-shaped.

[0033] Described hereinafter is a method of manufacturing and assembling the DDEM 10.

[0034] As a first step, the slots 28 are formed in the insulators 26 by one or more machining techniques that are capable of cutting thin dimensions (e.g., t.sub.1 and t.sub.2) of less than 1 millimeter. Such machining techniques include, for example, electrical discharge machining (EDM), laser cutting, water jet cutting, plasma cutting, flame cutting, or any combination thereof. Alternatively, the slots 28 may be formed at the third step.

[0035] As a second step, a block of conductive material (e.g., KOVAR®), which will eventually constitute conductor(s) 30, is joined to either one or both insulators 26 by brazing, adhesive bonding, or diffusive bonding, for example. Either one block of conductive material may be used to form both conductors 30 of arrays 12 and 14 (in which case the single block of material would be bonded to both insulators 26) or each conductor 30 may be formed from its own block of material (in which case one block of material would be bonded to a single insulator 26).

[0036] As a third step, the conductors 30 including all of their fingers 32, kerfs 33 and openings 38 are formed in the block(s) of conductive material by one or more machining techniques that are capable of cutting thin dimensions (e.g., t.sub.1 and t.sub.2) of less than 1 millimeter. Such machining techniques include, for example, electrical discharge machining (EDM), laser cutting, water jet cutting, plasma cutting, flame cutting, or any combination thereof. Traditional machining techniques have historically been incapable of achieving cut dimensions of less than 1 millimeter, but the invention in its broadest form is not necessarily limited to any particular machining technique. The input and output ends of the arrays 12 and 14 are also formed at this stage. As noted above, the slots 28 in the insulators 26 may also be formed at this stage instead of step 1.

[0037] The above-described machining techniques offer unmatched precision in achieving precise dynode geometry and position with a great level of reproducibility, and without the need for complicated fixturing devices during the assembly phase. Another advantage of the above machining techniques is that design changes for different DDEM applications are relatively simple to execute because they merely require machine programming changes. Yet another advantage is that the above-described machining techniques offer design flexibility in tuning the device for various applications such as dual mode (analog and counting) and fast response pulse application

[0038] As a fourth step, the emissive layer 31 is formed on the exposed surfaces of the conductors 30. As noted above, the layer 31 could be applied to the exposed surfaces of conductors 30 by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), for example, or the layer 31 may be a thermally grown oxide. The arrays 12 and 14 are now ready for assembly.

[0039] As a fifth step, the circuit boards 16 and 18 are assembled onto the arrays 12 and 14 using the fasteners 20, nuts 22 and washers 24 to form the assembled DDEM 10 shown in FIG. 2. DDEM 10 comprises less individual parts than prior art DDEM's, which is ideal from the assembly, labor, supply chain and quality assurance perspectives. DDEM 10 may be used in a mass spectrometer, for example.

[0040] The electronic driver (circuit board) may be configured to be mounted in various ways and positions with respect to the two arrays in order to either perform a single or a multiplexed collection of a signal.

[0041] Although the invention is illustrated and described herein with reference to specific examples, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.