Time constant calibration circuit and method

Abstract

A time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch and a second switch. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.

Claims

1. A time constant calibration circuit comprising: a resistor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal; an amplifier having a first input, a second input, and an output; a plurality of switches including a first switch and a second switch; and digital logic configured to control the plurality of switches and adjust resistances of the resistor and capacitances of the capacitor, wherein a resistance of the resistor and/or a capacitance of the capacitor is variable, wherein the first terminal of the resistor, the first terminal of the capacitor, and the first input of the amplifier are coupled together at a common node, wherein the second input of the amplifier is coupleable to a reference voltage, wherein the output of the amplifier is coupled to the second terminal of the resistor and to the second terminal of the capacitor, wherein the first terminal of the resistor, the first terminal of the capacitor, and the first input of the amplifier are coupleable to a reference current source at the common node, and wherein the time constant calibration circuit is operable to perform a time constant calibration process comprising one or more calibration cycles in which: the first switch and the second switch selectively route a reference current provided by the reference current source using the digital logic: through the resistor in a first phase of the, or each, calibration cycle; and through the capacitor in a second phase of the, or each, calibration cycle, and the resistance of the resistor and/or the capacitance of the capacitor is adjusted, using the digital logic, between each calibration cycle iteratively to determine an adjusted resistance of the resistor and/or an adjusted capacitance of the capacitor for producing said time constant.

2. The time constant calibration circuit of claim 1, wherein the common node is a virtual ground node.

3. The time constant calibration circuit of claim 1, comprising a comparator having a first input selectively coupleable to the second terminal of the resistor and/or the second terminal of the capacitor.

4. The time constant calibration circuit of claim 3, comprising the digital logic operable to adjust the resistance of the resistor and/or the capacitance of the capacitor between each calibration cycle based on a signal received from an output of the comparator.

5. The time constant calibration circuit of claim 3, further comprising a comparator switch coupled between the output of the comparator and a second input of the comparator, wherein: in the first phase the calibration circuit is operable to close the comparator switch to configure the comparator in a voltage follower mode in which a voltage at the first input of the comparator is copied to the second input of the comparator, and in the second phase the calibration circuit is operable to open the comparator switch.

6. The time constant calibration circuit of claim 5 comprising a storage capacitor coupled to the second input of the comparator for storing said voltage copied to the second input of the comparator in said first phase.

7. The time constant calibration circuit of claim 1, comprising the digital logic operable to open/close the first and second switches to configure the time constant calibration circuit for the first phase and the second phase.

8. The time constant calibration circuit of claim 1, operable to output a control signal corresponding to a resistance value and/or a capacitance value determined by the time constant calibration circuit during said time constant calibration process.

9. A continuous-time sigma-delta analog-to-digital converter comprising: a time constant calibration circuit comprising: a resistor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal; an amplifier having a first input, a second input, and an output; a plurality of switches including a first switch and a second switch; and digital logic configured to control the plurality of switches and adjust resistances of the resistor and capacitances of the capacitor, wherein a resistance of the resistor and/or a capacitance of the capacitor is variable, wherein the first terminal of the resistor, the first terminal of the capacitor and the first input of the amplifier are coupled together at a common node, wherein the second input of the amplifier is coupleable to a reference voltage, wherein the output of the amplifier is coupled to the second terminal of the resistor and to the second terminal of the capacitor, wherein the first terminal of the resistor, the first terminal of the capacitor and the first input of the amplifier are coupleable to a reference current source at the common node, and wherein the time constant calibration circuit is operable to perform a time constant calibration process comprising one or more calibration cycles in which: the first switch and the second switch selectively route a reference current provided by the reference current source using the digital logic: through the resistor in a first phase of the, or each, calibration cycle; and through the capacitor in a second phase of the, or each, calibration cycle, and the resistance of the resistor and/or the capacitance of the capacitor is adjusted between each calibration cycle iteratively to determine an adjusted resistance of the resistor and/or an adjusted capacitance of the capacitor for producing said time constant.

10. The continuous-time sigma-delta analog-to-digital converter of claim 9, further comprising an analog filter having one or more analog integrators, wherein the time constant calibration circuit is operable to output a control signal corresponding to a resistance value and/or a capacitance value determined during said time constant calibration process to the one or more analog integrators.

11. A time constant calibration method comprising: providing a calibration circuit comprising: a resistor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal; an amplifier having a first input, a second input, and an output; a plurality of switches including a first switch and a second switch; and digital logic configured to control the plurality of switches and adjust resistances of the resistor and capacitances of the capacitor, wherein a resistance of the resistor and/or a capacitance of the capacitor is variable, wherein the first terminal of the resistor, the first terminal of the capacitor and the first input of the amplifier are coupled together at a common node, wherein the second input of the amplifier is coupled to a reference voltage, wherein the output of the amplifier is coupled to the second terminal of the resistor and to the second terminal of the capacitor, wherein the first terminal of the resistor, the first terminal of the capacitor and the first input of the amplifier are coupled to a reference current source at the common node; and performing a time constant calibration process comprising one or more calibration cycles in which: the first switch and the second switch selectively route a reference current provided by the reference current source using the digital logic: through the resistor in a first phase of the, or each, calibration cycle; and through the capacitor in a second phase of the, or each, calibration cycle, and the resistance of the resistor and/or the capacitance of the capacitor is adjusted, using the digital logic, between each calibration cycle iteratively to determine an adjusted resistance of the resistor and/or an adjusted capacitance of the capacitor for producing said time constant.

12. The time constant calibration method of claim 11, wherein the common node is a virtual ground node.

13. The time constant calibration method of claim 11, wherein the time constant calibration circuit comprises a comparator having a first input selectively coupleable to the second terminal of the resistor and/or the second terminal of the capacitor, the method further comprising adjusting the resistance of the resistor and/or the capacitance of the capacitor between each calibration cycle based on a signal received from an output of the comparator.

14. The time constant calibration method of claim 13, further comprising operating the comparator in a voltage follower mode in which a voltage at the first input of the comparator is copied to a second input of the comparator for storage of the voltage copied to the second input of the comparator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of this disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:

(2) FIG. 1 shows a functional diagram of a ΣΔ ADC;

(3) FIG. 2 shows an integrator;

(4) FIG. 3 shows the transfer function of the integrator shown in FIG. 2;

(5) FIG. 4 shows a time constant calibration circuit according to an embodiment of this disclosure;

(6) FIGS. 5 and 6 show operational phases of the time constant calibration circuit of FIG. 4 according to an embodiment of this disclosure;

(7) FIG. 7 shows signal waveforms of the time constant calibration circuit of FIGS. 4 to 6 during a linear search method according to an embodiment of this disclosure; and

(8) FIGS. 8 and 9 show operational modes of a time constant calibration circuit according to another embodiment of this disclosure.

DETAILED DESCRIPTION

(9) Embodiments of this disclosure are described in the following with reference to the accompanying drawings.

(10) Embodiments of this disclosure can provide a novel position of a reference current source and offset compensation mechanism, which may avoid calibration inaccuracies due to the parasitic capacitances (denoted herein by C.sub.P1 and C.sub.P2) and comparator offset. Embodiments of this disclosure may be operable to perform calibration of a time constant τ=RC in a reduced number of operating phases (e.g. as few as two operating phases may be required in each calibration cycle).

(11) The principle of operation of the calibration method disclosed herein comprises charging a capacitor C with a reference current I.sub.REF for a predetermined time period T.sub.REF. At the end of the predetermined time period T.sub.REF, the voltage V.sub.C across the capacitor C is compared to a reference voltage V.sub.REF, which may be provided by a reference resistor R.sub.REF and which may be stored across a capacitor C.sub.STORE. If the voltage V.sub.C is lower than V.sub.REF then C may be reduced. On the other hand, if the voltage V.sub.C is higher than V.sub.REF then C may be increased. The calibration method disclosed herein may be determined as complete when V.sub.C is sufficiently close to V.sub.REF (for instance, when V.sub.C matches V.sub.REF to within a predetermined error margin, such as an error margin that corresponds to a minimum adjustment step in the value of C). Once the calibration method is complete, the capacitance value C may be supplied to one or more analog integrators (e.g. analog integrators 30 of the kind described above in relation to FIGS. 2 and 3) of a filter (such as the analog filter 6 of the kind described above in relation to FIG. 1). The capacitance value C may be supplied using a digital signal, such a digital capacitor adjustment command (DCAC).

(12) In some embodiments an alternative approach may be taken in which, instead of performing iterations in which a capacitor C is charged with a reference current I.sub.REF for a predetermined time period T.sub.REF (after which V.sub.C is compared to a reference voltage V.sub.REF), the time for the voltage V.sub.C across C to reach V.sub.REF is measured. In this alternative implementation, a counter, clocked with a reference clock, may start counting at the beginning of the charging operation of C and then stop when V.sub.C is equal to or exceeds V.sub.REF. The content of the counter is indicative of the time for the V.sub.C to reach V.sub.REF. C may then be adjusted, based on a comparison of the actual value of the counter to a reference time value T.sub.REF. These iterations may continue until V.sub.C just reaches V.sub.REF after a targeted duration T.sub.REF.

(13) FIG. 4 shows a time constant calibration circuit 50 according to an embodiment of this disclosure.

(14) The calibration circuit 50 may be coupled to one or more analog integrators 30 of an analog filter of a ΣΔ ADC, so that the calibration circuit 50 can output a calibrated capacitance value to the analog integrator(s) 30 (e.g. using a digital capacitor adjustment command, DCAC, as will be described in more detail below). Note that in this embodiment, the analog integrator(s) 30 may be similar in design to the analog integrator 30 described above in relation to FIGS. 2 and 3. As such, the analog integrator 30 may include an input 32 for receiving a voltage V.sub.in, a resistor 34 having a resistance R.sub.FILTER for converting the input voltage V.sub.in into a current I, and a capacitor 42 having a variable (e.g. programable using the DCAC) capacitance C.sub.FILTER for converting the current I into a signal voltage (V.sub.out) to be outputted at output 44. The analog integrator 30 may also include an amplifier 40, which may be a high-gain and high-bandwidth amplifier, to create a virtual ground 36, allowing a simple combination of the first (V.sub.in.fwdarw.I) and second (I.fwdarw.V.sub.out) converted signals, as explained previously in relation to FIG. 2. A first input of the amplifier 40 maybe coupled to the virtual ground (node) 36 and a second input of the amplifier 40 may be connected to a reference voltage (e.g. ground). An output of the amplifier 40 may be connected to the output 44. The capacitor 42 may be coupled in parallel with the first input and the output of the amplifier 40.

(15) The analog integrator 30 may have a transfer function in the frequency domain of the kind described above in relation to FIG. 3.

(16) While only a single analog integrator 30 is shown in FIG. 4, it will be appreciated that a device such as a ΣΔ ADC in accordance with embodiments of this disclosure may comprise an analog filter having one or more analog integrators. In embodiments in which the analog filter has multiple analog integrators, the analog integrators may be coupled together in a linear chain by coupling the input 32 of each analog integrator 30 to the output 44 of a preceding analog integrator 30 in the chain.

(17) In this embodiment, the calibration circuit 50 comprises: A voltage generator, which generates a voltage V.sub.B; An amplifier V.sub.AMP 52; A reference current source, which provides a reference current I.sub.REF; A reference resistor having a reference resistance R.sub.REF; A first switch SW1, and second switch SW2, a third switch SW3 and a fourth switch SW4; A capacitor having a variable (e.g. programable) capacitance C; A storage capacitor, which has a capacitance value C.sub.STORE; A comparator 54; and Digital logic 56.

(18) An output of the voltage generator (V.sub.B) is coupled to a positive input of an amplifier V.sub.Amp 52, so as to provide a reference voltage V.sub.B to the amplifier V.sub.AMP 52.

(19) An output of the amplifier V.sub.AMP 52 is coupled to a positive input of the comparator 54. A negative input of the comparator 54 is coupled to ground via the storage capacitor (C.sub.STORE). An output of the comparator 54 is coupled to the negative input of the comparator 54 in a feedback loop. The coupling between the output of the comparator 54 and the negative input of the comparator 54 is switchable, using switch SW4. The output of the comparator 54 is also coupled to an input of the digital logic 56.

(20) The digital logic 56 has an output coupled to a control input of the variable capacitor (C). The digital logic 56 is operable to control (vary) the capacitance of the variable capacitor (C), by outputting a control command to the variable capacitor (C). Similarly, the digital logic may control the capacitance of the filter capacitor C.sub.FILTER in one or more analog integrator(s) 30. The control command for the variable capacitor (C) and/or the filter capacitor(s) C.sub.FILTER may be a digital capacitor adjustment command (DCAC). The DCAC may comprise a digital word having a value that indicates the capacitance set value instructed by the command from the digital logic. The number of bits in the digital word may be chosen in accordance with the desired granularity of the capacitance control.

(21) The digital logic 56 is also operable to control the switches SW1, SW2, SW3, SW4 during the operation of the calibration circuit 50. This control of the switches SW1, SW2, SW3, SW4 by the digital logic 56 may be implemented using control signal θ.sub.REF and θ.sub.INT. The control signals θ.sub.REF and θ.sub.INT can be derived from a common signal, and may have opposite phase.

(22) An output of the reference current source (I.sub.REF) is coupled to a common node 55 of the reference resistor (R.sub.REF), the variable capacitor (C) and the negative input of the amplifier V.sub.AMP 52. The common node 55 can act as a virtual ground which can be maintained constant by the amplifier V.sub.AMP 52, set in a feedback configuration.

(23) The reference resistor (R.sub.REF) and the first switch SW4 are coupled in series in a first branch between the negative input of the amplifier V.sub.AMP 52 and the output of the amplifier V.sub.AMP 52. The variable capacitor (C) and the third switch SW3 are coupled in series in a second branch between the negative input of the amplifier V.sub.AMP 52 and the output of the amplifier V.sub.AMP 52. The second switch SW2 is coupled in parallel to the capacitor C.

(24) A number of parasitic capacitances C.sub.P1, C.sub.P2 are also marked in FIG. 4. The parasitic capacitance C.sub.P1 is located between ground and a line connecting the output of the amplifier V.sub.AMP 52 to a positive input of the comparator 54. The parasitic capacitance C.sub.P2 is located between ground and a line connecting a negative input of the amplifier V.sub.AMP 52 and the variable capacitor (C) (note that this line includes the common node 55).

(25) During operation, a reference time constant R.sub.REF*C can be measured by the digital logic 56, which can adjust the value of C in a number of iterations such that R.sub.REF*C=T.sub.REF. This may be implemented in a two-phase process, which will now be described.

(26) In this embodiment, a first phase of the process may be referred to as a reference setting phase. The operation of the calibration circuit 50 during this phase is illustrated in FIG. 5. During the reference setting phase, the digital logic 56 controls the switches (e.g. using the control signals θ.sub.REF and θ.sub.INT as illustrated in FIG. 5) such that switches SW1, SW2, SW4 are closed and SW3 is open. This causes the variable capacitor (C) to be discharged. The amplifier V.sub.AMP 52, in closed-loop configuration, ensures that: The voltage at the bottom terminals of the reference resistor (R.sub.REF) and the variable capacitor (C) (i.e. the terminals of those two components which are coupled to the negative input of the amplifier V.sub.AMP 52), is set to V.sub.AMP_INM=V.sub.B+V.sub.OFFSET1, where V.sub.OFFSET1 is an input offset of the amplifier V.sub.AMP 52; and The reference current I.sub.REF flows through the reference resistor (R.sub.REF).

(27) In this phase, the voltage V.sub.REF at the top terminal of the reference resistor (R.sub.REF) (i.e. the terminal that is coupled to the output of the amplifier V.sub.AMP 52 via the switch SW1) is equal to V.sub.B+V.sub.OFFSET1+I.sub.REF*R.sub.REF. This voltage is applied to the positive input of the comparator 54. With the switch SW4 closed, the comparator 54 is configured as a voltage follower with the output of the comparator 54 coupled to the negative input of the comparator 54. The voltage at the output and the negative input of the comparator 54 is thus driven towards V.sub.REF. This causes the storage capacitor (C.sub.STORE) to store a voltage value given by V.sub.REF+V.sub.OFFSET2, where V.sub.OFFSET2 is an input offset of the comparator 54.

(28) At the end of the reference setting phase, the parasitic capacitance C.sub.P2 is charged to V.sub.B+V.sub.OFFSET1. The duration of the first phase may be defined such that the calibration circuit 50 has sufficient time to drive I.sub.REF into R.sub.REF and apply V.sub.REF to the positive input of the comparator 54 and then to the negative input of the comparator 54.

(29) In this embodiment, a second phase of the process may be referred to as an integration phase. V.sub.B+V.sub.OFFSET1+I.sub.REF*R.sub.REF+V.sub.OFFSET2.

(30) The differential voltage V.sub.COMP_DIFF between the positive (V.sub.COMP_INP) and negative (V.sub.COMP_INM) inputs of the comparator 54 at the end of the integration phase is:

(31) $V_{\mathrm{COMP\_DIFF}}=V_{\mathrm{COMP\_INP}}-V_{\mathrm{COMP\_INM}}$$V_{\mathrm{COMP\_DIFF}}=V_B+V_{\mathrm{OFFSET}1}+I_{\mathrm{REF}}/C*T_{\mathrm{REF}}-\left(V_B+V_{\mathrm{OFFSET}1}+I_{\mathrm{REF}}*R_{\mathrm{REF}}+V_{\mathrm{OFFSET}2}\right)$$V_{\mathrm{COMP\_DIFF}}=I_{\mathrm{REF}}/C*T_{\mathrm{REF}}-I_{\mathrm{REF}}*R_{\mathrm{REF}}-V_{\mathrm{OFFSET}2}$

(32) Again, note that V.sub.OFFSET2 is the input offset of the comparator 54. Having V.sub.OFFSET2 in the equation of V.sub.COMP_DIFF means that this offset can be cancelled. Indeed, the differential threshold of an ideal comparator is 0 (zero) and if there is an offset V.sub.OFFSET2, then the differential threshold is equal to this offset V.sub.OFFSET2.

(33) Depending on the value at the output of the comparator 54 at the end of each integration phase, the digital logic 56 can adjust the capacitance of the variable capacitor (C) successively to a value C.sub.ADJ. If the output of the comparator 54 is high at the end of an integration phase, then the capacitance of the variable capacitor (C) can be increased. On the other hand, if the output of the comparator 54 is low at the end of an integration phase, then the capacitance of the variable capacitor (C) can be decreased.

(34) The process described above may be repeated in a number of iterations (each iteration including a reference setting phase followed by an integration phase) until the calibration circuit 50 settles at a differential input V.sub.COMP_DIFF of the comparator 54 that is substantially equal to the differential threshold V.sub.OFFSET2. We get then:

(35) $I_{\mathrm{REF}}/C_{\mathrm{ADJ}}*T_{\mathrm{REF}}-I_{\mathrm{REF}}*R_{\mathrm{REF}}=0C_{\mathrm{ADJ}}*R_{\mathrm{REF}}=T_{\mathrm{REF}}$

(36) As the calibration circuit 50 can be viewed as a time-discrete system, when the calibration circuit 50 reaches the desired point, the capacitance of variable capacitor (C) will generally toggle within the smallest capacitance step (which may correspond to the increment associated with the least significant bit (LSB) of a control word applied to the variable capacitor (C) by the digital logic 56).

(37) In accordance with embodiments of this disclosure, the measured time constant is not dependent on the parasitic capacitances C.sub.P1, C.sub.P2. In accordance with embodiments of this disclosure, the measured time constant is not dependent upon the input offset of the comparator 54 and/or the amplifier V.sub.AMP 52. Moreover, each calibration cycle may only require two phases (the reference setting phase followed by an integration phase noted above).

(38) Once the calibration circuit 50 has settled at the capacitance value that yields the desired time constant, the digital logic 54 may output a control signal to the filter capacitor 42 in one or more analog integrators 30 (see FIG. 4) so as to set the capacitance of the filter capacitor(s) 42 to that capacitance value. As explained previously, this may be achieved using a digital capacitor adjustment command (DCAC), which may be a digital (e.g. binary) word.

(39) Accordingly, the calibration circuit 50 may include an innovative placement of a unique reference current source, used for generating a reference voltage and charging a capacitor such that the calibration is natively insensitive to parasitic capacitance. In contrast to some state of the art designs, the reference current source may be located on a virtual ground side of a reference resistor and capacitor. In accordance with embodiments of this disclosure, a reference current may flow only through the capacitor under calibration (i.e. the variable capacitor (C)) and may not diverted into a parasitic capacitance.

(40) In accordance with embodiments of this disclosure, the search algorithm executed by the digital logic 54 of the calibration circuit 50 may be a classical binary (dichotomy) search or a linear search.

(41) FIG. 7 shows signal waveforms of the time constant calibration circuit 50 of FIGS. 4 to 6 during a classical linear search method according to an embodiment of this disclosure. FIG. 7 shows a plurality of calibration cycles (102, 104 . . . ), each calibration cycle including a first (e.g. reference setting) phase 110 (in which θ.sub.REF is high and θ.sub.INT is low) followed by a second (e.g. integration) phase 112 (in which θ.sub.REF is low and θ.sub.INT is high). Virtual ground is denoted by the reference number 130 in FIG. 7. As can be seen in FIG. 7, at the end 114 of the first calibration cycle 102 in this example, the output of the comparator 54 is at logic LOW level thus C is decreased at the next cycle. Similarly, at the end 116 of the next calibration cycle 104 in this example, the output of the comparator 54 is again at logic LOW level thus C is once again decreased at the next cycle. In contrast, at the end 118 of the next cycle, the output of the comparator 54 at logic HIGH level and C is increased. At the end 120 of the next cycle, the input voltages at the comparator 54 are substantially equal: V.sub.COMP_INP=V.sub.COMP_INM, indicating the capacitance of the variable capacitor (C) has converged on a value that yields the desired time constant. Thus, the calibration reaches convergence when the output of the comparator 54, at the end of the integration phase, toggles alternatively between logic H and logic L from one cycle to another (this can be seen in FIG. 7 by noting the H/L value of C.sub.COMP_OUT at the cycle ends 118, 120, 122). The capacitor value toggles then above and below the desired value with a delta at most equal to the capacitance step value. While a linear search approach is shown in FIG. 7, it will be appreciated that other search methodologies may be followed (e.g. a binary search).

(42) Although the effect of the parasitic capacitors C.sub.P1 and C.sub.P2 as well as input offsets of the comparator 54 and amplifier V.sub.AMP 52 are cancelled in the first embodiment, the resistance of switches SW1 and SW3 may still impact the accuracy of the measurement due to the voltage drop in relation to the current I.sub.REF flowing through these switches. Indeed, at the end of the reference setting phase, the voltage at the positive input of the comparator (V.sub.COMP_INP) may no longer be V.sub.B+I.sub.REF*R.sub.REF (V.sub.OFFSET1 is ignored for simplicity here) but may instead be V.sub.B+I.sub.REF*(R.sub.SW1+R.sub.REF), owing to the resistance of the switch SW1. Similarly, the voltage at V.sub.COMP_INP at the end of the integration phase may be V.sub.B+I.sub.REF*(T.sub.REF/C+R.sub.SW3) instead of V.sub.B+I.sub.REF*T.sub.REF/C, owing to the resistance of the switch SW3.

(43) FIGS. 8 and 9 show operational modes of a time constant calibration circuit 50 according to another embodiment of this disclosure. The calibration circuit 50 itself is similar in some respects to the calibration circuit 50 described above in relation to FIGS. 4 to 7 and only the differences will be described below in detail. In this embodiment, the problem noted above in respect of the resistance of the switches modifying the voltages in the circuit, such as the voltage at the positive input of the comparator 54 may be addressed.

(44) In the embodiment of FIGS. 8 and 9, two further switches SW11 and SW31 are added to the calibration circuit 50. The switch SW11 is coupled between a node located between the reference resistor (R.sub.REF) and the switch SW1 and the positive input of the comparator 54. The switch SW31 is coupled between a node located between the variable capacitor (C) and the switch SW3 and the positive input of the comparator 54. Note that although the switches SW1 and SW3 are still coupled to the output of the amplifier V.sub.AMP 52, neither switch SW1, SW3 is coupled directly to the positive input of the comparator 54.

(45) As in the embodiment of FIGS. 4 to 7, a calibration cycle performed by the calibration circuit 50 may include a reference setting phase followed by an integration phase. The operation of the calibration circuit 50 in the reference setting phase of this embodiment is shown in FIG. 8, while the operation of the calibration circuit 50 in the integration phase of this embodiment is shown in FIG. 9.

(46) Again, the digital logic 56 may use control signals θ.sub.REF and θ.sub.INT to control the switches SW1, SW2, SW3, SW4, SW11, SW31 during these phases (the application of these control signals is noted in FIGS. 8 and 9).

(47) In the reference setting phase (FIG. 8), switches SW1, SW11, SW2 and SW4 are closed, while switches SW3 and SW31 are open. This configuration couples the node between the switch SW1 and the reference resistor (R.sub.REF) to the positive input of the comparator in the reference setting phase.

(48) In the integration phase (FIG. 9), switches SW1, SW11, SW2 and SW4 are open, while switches SW3 and SW31 are closed. This configuration couples the node between the switch SW3 and the variable capacitor (C) to the positive input of the comparator in the integration phase.

(49) The operation of the calibration circuit 50 in the reference setting phase shown in FIG. 8 is analogous to the operation of the calibration circuit 50 as illustrated in FIG. 5, while the operation of the calibration circuit 50 in the integration phase shown in FIG. 9 is analogous to the operation of the calibration circuit 50 as illustrated in FIG. 6. However, in the present embodiment, note that in neither phase does the current I.sub.REF flow through the switches SW11 or SW31. Because of this, no voltage drop will impact the accuracy of the measurements made at the comparator 54. Accordingly, the resistance of the switches of the calibration circuit 50 (e.g. SW1 and SW2) no longer interfere with the calibration measurement.

(50) While the embodiments described above use a variable capacitor, an alternative approach is in envisaged in which the capacitor is a reference capacitor having a fixed capacitance and the reference resistor (R.sub.REF) described above is replaced by a variable resistor. The operation of a calibration circuit in this kind of embodiment would be similar to the embodiments described above, except that instead of determining the capacitance of a variable capacitor which, in combination with reference resistor, produces the desired time constant, the calibration circuit instead determines the resistance of the variable resistor which, in combination with the reference capacitor, produces the desired time constant. The layout of circuits in such embodiments may be substantially the same as described above in relation to FIGS. 4 to 9. The digital logic 56 in such embodiments may use a control signal to vary the resistance of the variable resistor in each calibration cycle in much the same way as described above in respect of the variable capacitor (C), until the calibration circuit settles upon the resistance value that yields the desired time constant. In such embodiments, the calibration circuit may output a control signal to one or more analog integrators of an analog filter as described above. However, in such embodiments, the analog integrator(s) may comprise a variable resistor (R.sub.FILTER) (instead of the variable capacitor (C.sub.FILTER) described above in relation to FIG. 4), which may be set using the control signal from the calibration circuit to the resistance value that yields the desired time constant.

(51) It is also envisaged that the approaches outlined above may be combined in an embodiment in which both the resistance of the resistor and the capacitance of the capacitor in the calibration circuit may be varied. In such a combined approach, the digital logic may vary the resistance of the resistor and/or the capacitance of the capacitor in each calibration cycle, and subsequently output resistance and capacitance values to analog integrator(s) of an analog filter comprising a variable filter resistor and filter capacitor. This can allow for further fine tuning of the time constant.

(52) Accordingly, there has been described a time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch, a second switch and a current source. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance of the resistor and/or the capacitance of the capacitor is adjusted between calibration cycles to determine a resistance and/or a capacitance for producing the time constant.

(53) Although particular embodiments of this disclosure have been described, it will be appreciated that many modifications/additions and/or substitutions may be made within the scope of the claims.