MBE growth technique for group II-VI inverted multijunction solar cells
09837563 · 2017-12-05
Assignee
Inventors
- Sivalingam Sivananthan (Naperville, IL, US)
- James W. Garland (Aurora, IL, US)
- Michael W. Carmody (Western Springs, IL, US)
Cpc classification
H01L31/0296
ELECTRICITY
Y02P70/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/1892
ELECTRICITY
H01L31/1836
ELECTRICITY
H01L21/02485
ELECTRICITY
H01L31/073
ELECTRICITY
Y02E10/543
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
H01L21/06
ELECTRICITY
H01L31/073
ELECTRICITY
H01L31/18
ELECTRICITY
Abstract
A method of forming a Group II-VI multijunction semiconductor device comprises providing a Group IV substrate, forming a first subcell from a first Group II-VI semiconductor material, forming a second subcell from a second Group II-VI semiconductor material, and removing the substrate. The first subcell is formed over the substrate and has a first bandgap, while the second subcell is formed over the first subcell and has a second bandgap which is smaller than the first bandgap. Additional subcells may be formed over the second subcell with the bandgap of each subcell smaller than that of the preceding subcell and with each subcell preferably separated from the preceding subcell by a tunnel junction. Prior to the removal of the substrate, a support layer is affixed to the last-formed subcell in opposition to the substrate.
Claims
1. A method of forming a Group II-VI multijunction semiconductor solar cell, comprising the steps of: providing a silicon growth substrate; forming, on the growth substrate, a passivation layer including Arsenic: forming, on the passivation layer, a buffer layer of zinc telluride, a lattice constant of the buffer layer being substantially mismatched to a lattice constant of the growth substrate; forming, on the buffer layer, a first subcell from a first Group II-VI semiconductor material selected from the group consisting of CdTe, Cd.sub.wMn.sub.1-wTe, Hg.sub.xCd.sub.1-xTe, Cd.sub.yZn.sub.1-yTe, Cd.sub.zMg.sub.1-zTe, CdSe, Cd.sub.aMn.sub.1-aSe, Hg.sub.bCd.sub.1-bSe, Cd.sub.cZn.sub.1-cSe, Cd.sub.dMg.sub.1-dSe and combinations thereof, where 0<w<1, 0<x<1, 0<y<1, 0<z<1, 0<a<1, 0<b<1, 0<c<1 and 0<d<1, the first subcell having a lattice constant substantially mismatched to the lattice constant of the growth substrate, the first subcell having a first band gap; forming, over the first subcell, a second subcell from a second Group II-VI semiconductor material selected from the group consisting of CdTe, Cd.sub.wMn.sub.1-wTe, Hg.sub.xCd.sub.1-xTe, Cd.sub.yZn.sub.1-yTe, Cd.sub.zMg.sub.1-zTe, CdSe, Cd.sub.aMn.sub.1-aSe, Hg.sub.bCd.sub.1-bSe, Cd.sub.cZn.sub.1-cSe, Cd.sub.dMg.sub.1-dSe and combinations thereof, where 0<w<1, 0<x<1, 0<y<1, 0<z<1, 0<a<1, 0<b<1, 0<c<1 and 0<d<1, the second subcell having a lattice constant substantially mismatched to the lattice constant of the growth substrate, the second subcell having a second band gap that is smaller than the first band gap; affixing a back support such that the back support is proximate the second subcell and remote from the first subcell; and removing the growth substrate.
2. The method of claim 1, wherein the passivation layer is arsenic.
3. The method of claim 1, further comprising: after said step of forming the second subcell, forming a back contact to be proximate the second subcell and remote from the first subcell.
4. The method of claim 3, wherein the back contact is adjacent to the second subcell.
5. The method of claim 1, further comprising: after said step of removing the growth substrate, forming a front contact to be proximate to the first subcell and remote from the second subcell.
6. The method of claim 5, wherein the front contact is formed to be adjacent to the first subcell.
7. The method of claim 1, further comprising a step of forming a homojunction in each of the first and second subcells.
8. The method of claim 1, wherein the step of forming the first subcell comprises the substeps of: forming a first emitter having a first conductivity type to be adjacent to the growth substrate; and forming a first base having a second conductivity type on the first emitter, the second conductivity type being opposite the first conductivity type.
9. The method of claim 8, further comprising: after the step of forming the first subcell, foming, over the first subcell a first tunnel junction of Group II-VI semiconducting material selected from the group consisting of ZnTe, ZnS, MgTe, Cd.sub.eZn.sub.1-eTe, Cd.sub.fMg.sub.1-fTe and combinations thereof, where 0<e<1 and 0<f<1.
10. The method of claim 9, wherein the step of forming the first tunnel junction comprises the substeps of: forming a highly doped first layer having the first conductivity type on the first base; and forming a highly doped second layer having the second conductivity type on the first layer.
11. The method of claim 1, wherein the step of removing the growth substrate comprises the substeps of: chemically etching the substrate with CP4; and following the chemical etch, etching the growth substrate with an inductively coupled plasma process.
12. The method of claim 1, wherein the step of removing the growth substrate comprises the substep of ion cutting.
13. The method of claim 1, further comprising forming a third subcell from a third Group II-VI semiconductor material and having a third band gap over the second subcell, the third band gap being lower than the second band gap.
14. The method of claim 13, wherein the third Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the third band gap is about 0.95 eV, the second Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the second band gap is about 1.4 eV, the first GroupII-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, and the first band gap is about 1.96 eV.
15. The method of claim 13, wherein the third Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the third band gap is about 0.95 eV, the second Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x the second band gap is about 1.4 eV, the first Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, and the first band gap is about 1.96 eV.
16. The method of claim 13, wherein the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, the third band gap is about 1.08 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first GroupII-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, and the first band gap is about 2.04 eV.
17. The method of claim 13, wherein the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, the third band gap is about 1.08 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, and the first band gap is about 2.04 eV.
18. The method of claim 13, wherein the third Group Ii-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the third band gap is about 0.95 eV, the second GroupII-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the second band gap is about 1.4 eV, the first Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, and the first band gap is about 1.96 eV.
19. The method of claim 13, wherein the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, the third band gap is about 1.08 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, and the first band gap is about 2.04 eV.
20. The method of claim 13, further comprising the step of forming a fourth subcell from a fourth Group II-VI semiconductor material and having a fourth band gap over the third subcell, the fourth band gap being lower than the third band gap.
21. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.y′Zn.sub.1-y′Te, the second band gap is about 1.55 eV, and the first Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, where y′>y, and the first band gap is about 2.08 eV.
22. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, the second band gap is about 1.55 eV, and the first Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, and the first band gap is about 2.08 eV.
23. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, the second band gap is about 1.55 eV, the first Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, and the first band gap is about 2.08 eV.
24. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.z′Mg.sub.1-z′Te, the second band gap is about 1.55 eV, the first Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, where z′>z, and the first band gap is about 2.08 eV.
25. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′, the fourth band gap is about 0.68 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.1 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, and the first band gap is about 2.04 eV.
26. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.68 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.1 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first Group II-VI semiconductor material is Cd.sub.zMg.sub.1-zTe, and the first band gap is about 2.04 eV.
27. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, the second band gap is about 1.55 eV, the first Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, and the first band gap is about 2.08 eV.
28. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.yZn.sub.1-yTe, the second band gap is about 1.55 eV, the first Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, and the first band gap is about 2.08 eV.
29. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.75 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.16 eV, the second Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, the second band gap is about 1.55 eV, the first Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, where w′>w, and the first band gap is about 2.08 eV.
30. The method of claim 20, wherein the fourth Group II-VI semiconductor material is Hg.sub.x′Cd.sub.1-x′Te, the fourth band gap is about 0.68 eV, the third Group II-VI semiconductor material is Hg.sub.xCd.sub.1-xTe, where x′>x, the third band gap is about 1.1 eV, the second Group II-VI semiconductor material is CdTe, the second band gap is about 1.5 eV, the first Group II-VI semiconductor material is Cd.sub.wMn.sub.1-wTe, and the first band gap is about 2.04 eV.
31. The method of claim 1, wherein the steps of forming the first and second subcells are performed through the process of molecular beam epitaxy.
32. The method of claim 20, wherein the first, second, third, and fourth subcells are formed in a single run by molecular beam epitaxy.
33. A method of forming a Group II-VI multijunction semiconductor solar cell, comprising the steps of: providing a growth substrate of Group IV semiconductor material, a growth surface of the growth substrate presenting a first lattice constant; forming, on the growth substrate, a passivation layer including Arsenic; forming, on the passivation layer, a buffer layer of zinc telluride, a lattice constant of the buffer layer being substantially mismatched to the first lattice constant; forming, on the buffer layer, a first subcell from a first Group II-VI semiconductor material selected from the group consisting of CdTe, Cd.sub.wMn.sub.1-wTe, Hg.sub.xCd.sub.1-xTe, Cd.sub.yZn.sub.1-yTe, Cd.sub.zMg.sub.1-zTe, CdSe, Cd.sub.aMn.sub.1-aSe, Hg.sub.bCd.sub.1-bSe, Cd.sub.dMg.sub.1-dSe and combinations thereof, where 0<w<1, 0<x<1, 0<y<1, 0<z<1, 0<a<1, 0<b<1 and 0<d<1, the first subcell having a lattice constant substantially mismatched to the first lattice constant and having a first band gap; forming, over the first subcell, a second subcell from a second Group II-VI semiconductor material selected from the group consisting of CdTe, Cd.sub.wMn.sub.1-wTe, Hg.sub.xCd.sub.1-xTe, Cd.sub.yZn.sub.1-yTe, Cd.sub.zMg.sub.1-zTe, CdSe, Cd.sub.aMn.sub.1-aSe, Hg.sub.bCd.sub.1-bSe, Cd.sub.dMg.sub.1-dSe, and combinations thereof, where 0<w<1, 0<x<1, 0<y<1, 0<z<1, 0<a<1, 0<b<1 and 0<d<1, the second subcell having a lattice constant substantially mismatched to the first lattice constant, the second subcell having a second band gap that is smaller than the first band gap; affixing a back support such that the back support is proximate the second subcell and remote from the first subcell; and removing the growth substrate.
34. The method of claim 33, wherein the passivation layer consists of arsenic.
35. The method of claim 33, wherein the step of forming the first subcell comprises the substeps of forming a first emitter to have a first conductivity type and to be proximate the growth substrate, and forming a first base to have a second conductivity type opposite the first conductivity type and to be remote from the growth substrate, the method further comprising: after the step of forming the first subcell, forming, over the first subcell, a first tunnel junction of Group II-VI semiconductor material selected from the group consisting of ZnTe, ZnS, MgTe, Cd.sub.eZn.sub.1-eTe, Cd.sub.fMg.sub.1-fTe and combinations thereof, where 0<e<1 and 0<f<1, the step of forming the first tunnel junction comprising the substeps of forming, on the first base, a degeneratively doped first layer having the first conductivity type, and forming, on the first layer, a degeneratively doped second layer having the second conductivity type.
36. The method of claim 33, further comprising forming, over the second subcell, a third subcell from a third Group II-VI semiconductor material, the third Group II-VI semiconductor material having a third band gap which is lower than the second band gap.
37. The method of claim 36, further comprising forming, over the third subcell, a fourth subcell from a fourth Group II-VI semiconductor material, the fourth Group II-VI semiconductor material having a fourth band gap which is lower than the third band gap.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Further aspects of the invention and their advantages can be discerned in the following detailed description, in which like characters denote like parts and in which:
(2)
(3)
(4)
DETAILED DESCRIPTION
(5) Referring to
(6) The substrate 202 may be made of any Group IV material such as Ge, strained silicon-germanium, SOI, Si, or GaAs, but Si is preferred because it is more robust, is available in the largest area, and is inexpensive. The Group II-VI semiconductor materials may be selected from CdTe, Cd.sub.wMn.sub.1-wTe, Hg.sub.xCd.sub.1-xTe, Cd.sub.yZn.sub.1-yTe, Cd.sub.zMg.sub.1-zTe, CdSe, Cd.sub.aMn.sub.1-aSe, Hg.sub.bCd.sub.1-bSe, Cd.sub.cZn.sub.1-cSe, Cd.sub.dMg.sub.1-dSe, and combinations thereof, where 0<w<1, 0<x<1, 0<y<1, 0<z<1, 0<a<1, 0<b<1, 0<c<1, and 0<d<1. The semiconducting device may contain one, two, or more layers of any of these semiconductor alloys. In cases in which the same material is used more than once in a cell, the second composition is denoted with a prime. Thus, in a preferred embodiment, the third and fourth subcells 308 and 312 (
(7) The individual layers of the photovoltaic cell 200 may be formed through a variety of processes such as MOCVD and MBE, but MBE is preferred because it is less expensive, allows more rapid expansion of manufacturing capacity, allows the layers to be formed in a single run and is a less toxic process. Each subcell 204, 206 has a homojunction.
(8) The step of forming (104) the first subcell 204 comprises the substeps of forming (128) a first emitter 212 having a first conductivity type to be adjacent to the substrate 202 and forming (130) a first base 214 having a second conductivity type on the first emitter 212. The second conductivity type is opposite the first conductivity type.
(9) Prior to forming (104) the first subcell 204, additional layers may be formed to enhance the properties of the device 200. Thus, the method may further comprise the steps of forming (120) a passivation layer 208, preferably including arsenic, on the substrate 202 and forming (122) a buffer layer 210, preferably of zinc telluride, on the passivation layer 208.
(10) Moreover, the method may include forming (126) additional subcells from Group II-VI semiconductor alloys. Thus, to build the four-subcell structure shown by way of example in
(11) As with forming (104) the first subcell 204, the step of forming (108) the second subcell 206 includes the substeps of forming (136) a second emitter 222 and forming (138) a second base 224. Similarly, the step of forming (126) additional subcells 308, 312 includes the substeps of forming (140) additional emitters 318 and 326 and forming (142) additional bases 320 and 328. The subsequent emitters and bases have opposite conductivity types. Table 1 below shows various preferred three-cell embodiments.
(12) TABLE-US-00001 TABLE 1 1st Layer 2nd Layer 3rd Layer No. Bandgap/Composition Bandgap/Composition Bandgap/Composition 1 1.96 eV/Cd.sub.yZn.sub.1−yTe 1.4 eV/Hg.sub.xCd.sub.1−xTe 0.95 eV/Hg.sub.x′Cd.sub.1−x′Te 2 1.96 eV/Cd.sub.zMg.sub.1−zTe 1.4 eV/Hg.sub.xCd.sub.1−xTe 0.95 eV/Hg.sub.x′Cd.sub.1−x′Te 3 2.04 eV/Cd.sub.yZn.sub.1−yTe 1.5 eV/CdTe 1.08 eV/Hg.sub.x′Cd.sub.1−x′Te 4 2.04 eV/Cd.sub.zMg.sub.1−zTe 1.5 eV/CdTe 1.08 eV/Hg.sub.x′Cd.sub.1−x′Te 5 1.96 eV/Cd.sub.wMn.sub.1−wTe 1.4 eV/Hg.sub.xCd.sub.1−xTe 0.95 eV/Hg.sub.x′Cd.sub.1−x′Te 6 2.04 eV/Cd.sub.wMn.sub.1−wTe 1.5 eV/CdTe 1.08 eV/Hg.sub.x′Cd.sub.1−x′Te where 0 < w ≦ 1, 0 ≦ x < x′ < 1; 0 < y ≦ 1, and 0 < z ≦ 1.
Table 2 shows various preferred four-cell embodiments.
(13) TABLE-US-00002 TABLE 2 1st Layer 2nd Layer 3rd Layer 4th Layer No. Bandgap/Composition Bandgap/Composition Bandgap/Composition Bandgap/Composition 1 2.08 eV/Cd.sub.yZn.sub.1−yTe 1.55 eV/Cd.sub.y′Zn.sub.1−y′Te 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 2 2.08 eV/Cd.sub.yZn.sub.1−yTe 1.55 eV/Cd.sub.zMg.sub.1−zTe 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 3 2.08 eV/Cd.sub.zMg.sub.1−zTe 1.55 eV/Cd.sub.yZn.sub.1−yTe 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 4 2.08 eV/Cd.sub.zMg.sub.1−zTe 1.55 eV/Cd.sub.z′Mg.sub.1−z′Te 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 5 2.04 eV/Cd.sub.yZn.sub.1−yTe 1.50 eV/CdTe 1.10 eV/Hg.sub.xCd.sub.1−xTe 0.68 eV/Hg.sub.x′Cd.sub.1−x′Te 6 2.04 eV/Cd.sub.zMg.sub.1−zTe 1.50 eV/CdTe 1.10 eV/Hg.sub.xCd.sub.1−xTe 0.68 eV/Hg.sub.x′Cd.sub.1−x′Te 7 2.08 eV/Cd.sub.yZn.sub.1−yTe 1.55 eV/Cd.sub.wMn.sub.1−wTe 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 8 2.08 eV/Cd.sub.wMn.sub.1−wTe 1.55 eV/Cd.sub.yZn.sub.1−yTe 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 9 2.08 eV/Cd.sub.wMn.sub.1−wTe 1.55 eV/Cd.sub.w′Mn.sub.1−w′Te 1.16 eV/Hg.sub.xCd.sub.1−xTe 0.75 eV/Hg.sub.x′Cd.sub.1−x′Te 10 2.04 eV/Cd.sub.wMn.sub.1−wTe 1.50 eV/CdTe 1.10 eV/Hg.sub.xCd.sub.1−xTe 0.68 eV/Hg.sub.x′Cd.sub.1−x′Te where 0 < w < w′ ≦ 1; 0 ≦ x < 1, 0 < x ≦ x′ < 1, 0 < y < y′ ≦ 1; 0 < z < z′ ≦ 1.
(14) It is advantageous to form a tunnel junction comprising Group II-VI semiconducting material in between each subcell to provide a non-blocking path for the series current generated by the subcells and passing through them. Thus, the method further includes forming (106,
(15) Once the desired number of layers or subcells is formed, the method continues with a step of affixing (110,
(16) After the support layer has been affixed, the substrate 202 is removed at step 114. The substrate 202 can be removed with a variety of techniques including chemical etching, plasma etching, and/or ion cutting. Preferably, the step of removing (114) the substrate 202 comprises the substeps of chemically etching (146) the substrate 202 with an acid etch and subsequently etching (148) the substrate 202 with an inductively coupled plasma etch. A preferred chemical etchant comprises a mixture of hydrofluoric acid, nitric acid, and acetic acid in a 3:5:3 ratio, referred to hereinafter as “CP4.”
(17) Alternatively, the substrate 202 can be removed by ion cutting the substrate 202 from photovoltaic cell. A complete description of the ion cutting technique is disclosed in U.S. Pat. No. 6,346,458 B1 to Bower, which is expressly incorporated by reference into this disclosure.
(18) After removing (114) the substrate 202, the method continues with a step of forming (116) a front contact 304 (
(19) The antireflection coating (ARC) minimizes surface reflections, thereby enabling more photons of the incident light to enter the photovoltaic solar cell, and can also be used as an encapsulant for radiation hardening to improve radiation tolerance against damage from high energy photons and charged particles. The ARC has a relatively wide energy gap (E.sub.gARC≈3.20 eV) in comparison to the energy gap of the subcells that it is protecting, and a relatively thin layer thickness (d.sub.ARC≈0.05 to 0.5 μm). It preferably comprises a material selected from the group consisting of Cd.sub.2SnO.sub.4, SnO.sub.2, ZnSe, TiO.sub.2, MgTe, ZnO, ZnS, MgSe, ITO, MgS, MgO, SiO.sub.2, and MgF.sub.2. In addition, the ARC can be made by stacking together multiple thin layers of appropriate thicknesses from the materials listed above to further reduce the reflection of the incident light at the top surfaces.
(20) In summary, the described method of forming a Group II-VI multi junction semiconductor device eliminates the lattice matching that is necessary when using Group III-V semiconductor layers. This allows for more flexibility in selecting the bandgap of each layer. Also, it provides a more robust physical structure.
(21) While illustrated embodiments of the present invention have been described and illustrated in the appended drawings, the present invention is not limited thereto but only by the scope and spirit of the appended claims.