STATIC RANDOM-ACCESS MEMORY DEVICE WITH THREE-LAYERED CELL DESIGN

Abstract

The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.

Claims

1. A static random-access memory (SRAM) device comprising: a storage cell for storing a bit, the storage cell comprising a first storage transistor, a second storage transistor, a third storage transistor, and a fourth storage transistor; a first access transistor and a second access transistor configured to control access to the storage cell for storing or reading the bit; and a stack of layer structures comprising three layer structures; wherein the first storage transistor and the third storage transistor of the storage cell are formed in a first layer structure of the stack of layer structures, wherein the second storage transistor and the fourth storage transistor of the storage cell are formed in a second layer structure of the stack of layer structures, wherein the second layer structure is adjacent to the first layer structure, wherein the first access transistor and the second access transistor are formed in a third layer structure of the stack adjacent to the second layer structure, wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material, and wherein the semiconductor materials of at least two of the three layer structures are of different types from each other.

2. The SRAM device of claim 1, wherein each of the different types of the semiconductor materials comprises: a silicon-based semiconductor material, a two-dimensional (2D) semiconductor material, or an oxide semiconductor material.

3. The SRAM device of claim 1, wherein the first layer structure and the second layer structure each comprise a silicon-based semiconductor material, and wherein the third layer structure comprises one or both of a 2D semiconductor material and an oxide semiconductor.

4. The SRAM device of claim 3, wherein relative to a main surface of a substrate: the first layer structure is formed above the main surface, the second layer structure is formed above the first layer structure, and the third layer structure is formed above the first layer structure and the second layer structure.

5. The SRAM device of claim 1, wherein the first layer structure and the second layer structure each comprises a 2D semiconductor material, an oxide semiconductor material, or both, and wherein the third layer structure comprises a silicon-based semiconductor material.

6. The SRAM device of claim 5, wherein relative to a main surface of a substrate: the third layer structure is formed above the main surface, the second layer structure is formed above the third layer structure, and the first layer structure is formed above the third layer structure and the second layer structure.

7. The SRAM device of claim 1, wherein the first layer structure is a doped layer structure of a first-conductivity type and the second layer structure is a doped layer structure of a second conductivity-type.

8. The SRAM device of claim 1, wherein the first storage transistor and the second storage transistor are arranged as a first complementary field effect transistor (CFET).

9. The SRAM device of claim 8, wherein the third storage transistor and the fourth storage transistor are arranged as a second CFET.

10. The SRAM device of claim 9, wherein: one or both of the first CFET and the second CFET comprise an integrated silicon-based nanosheet transistor.

11. The SRAM device of claim 1, further comprising: a first vertical element electrically connecting a gate of the first storage transistor to a gate of the second storage transistor.

12. The SRAM device of claim 11, further comprising: a second vertical element electrically connecting a gate of the third storage transistor to a gate of the fourth storage transistor.

13. The SRAM device of claim 12, further comprising: a third vertical element electrically connecting a source/drain of the first storage transistor, a source/drain of the second storage transistor, and a source/drain of the first access transistor.

14. The SRAM device of claim 13, further comprising: a fourth vertical element electrically connecting a source/drain of the third storage transistor, a source/drain of the fourth storage transistor, and a source/drain of the second access transistor.

15. The SRAM device of claim 12, further comprising: a third vertical element electrically connecting a source/drain of the first storage transistor, a source/drain of the second storage transistor, and a source/drain of the first access transistor; and a fourth vertical element electrically connecting a source/drain of the third storage transistor, a source/drain of the fourth storage transistor, and a source/drain of the second access transistor, wherein the first vertical element is electrically connected to the fourth vertical element, and wherein the second vertical element is electrically connected to the third vertical element.

16. The SRAM device of claim 15, wherein: a source/drain of the first storage transistor and a source/drain of the third storage transistor are connected to a ground line; and a source/drain of the second storage transistor and a source/drain of the fourth storage transistor are connected to a supply voltage line.

17. The SRAM device of claim 1, further comprising: a wordline; and a bitline arranged in the third layer structure and connected to a source/drain of the first access transistor, and a complementary bitline arranged in the third layer structure and connected to the source/drain of the second access transistor.

18. The SRAM device of claim 17, wherein the wordline is arranged above the stack and electrically connected to a gate of the first access transistor and a gate of the second access transistor.

19. The SRAM device of claim 17, wherein the wordline is arranged between the second layer structure and the third layer structure and electrically connection to a gate of the first access transistor and a gate of the second access transistor.

20. A method for fabricating a static random-access memory, SRAM, device comprising a stack of layer structures comprising three layer structures, the method comprising: forming a first layer structure of the stack, wherein two storage transistors of a storage cell of the SRAM device are formed in the first layer structure; forming a second layer structure of the stack adjacent to the first layer structure, wherein two other storage transistors of the storage cell are formed in the second layer structure; forming a third layer structure of the stack adjacent to the second layer structure, wherein two access transistors are formed in the third layer structure, the two access transistors being configured to control access to the storage cell for storing or reading a bit to or from the storage cell; and wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material, and wherein at least two of the three layer structures comprise a different type of semiconductor material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above-described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:

[0042] FIG. 1 shows an SRAM cell of a conventional SRAM device.

[0043] FIG. 2 shows an SRAM cell of a SRAM device according to an embodiment of this disclosure in a sectional view.

[0044] FIG. 3A shows a first example of an SRAM cell of an SRAM device according to an embodiment of this disclosure in a sectional view.

[0045] FIG. 3B shows a schema of the example SRAM cell depicted in FIG. 3A.

[0046] FIG. 4A shows the first example of the SRAM cell in a top view

[0047] FIG. 4B and shows a schema of the example SRAM cell depicted in FIG. 4A.

[0048] FIG. 5A shows a second example of an SRAM cell of an SRAM device according to an embodiment of this disclosure in a sectional view.

[0049] FIG. 5B shows a schema of the example SRAM cell depicted in FIG. 5A.

[0050] FIG. 6A shows the second implementation of the SRAM cell in a top view.

[0051] FIG. 6B shows the schema of the SRAM cell depicted in FIG. 6A.

[0052] FIG. 7 shows a flow-diagram of a method for fabricating a SRAM cell of a SRAM device according to an embodiment of this disclosure.

[0053] FIGS. 8A and 8B show a first step of an exemplary process of fabricating the first example of the SRAM cell.

[0054] FIGS. 9A and 9B show a second step of an exemplary process of fabricating the first example of the SRAM cell.

[0055] FIGS. 10A and 10B show a third step of an exemplary process of fabricating the first example of the SRAM cell.

[0056] FIGS. 11A and 11B show a fourth step of an exemplary process of fabricating the first example of the SRAM cell.

[0057] FIGS. 12A and 12B show a fifth step of an exemplary process of fabricating the first example of the SRAM cell.

[0058] FIGS. 13A and 13B show a sixth step of an exemplary process of fabricating the first example of the SRAM cell.

[0059] FIGS. 14A and 14B show a seventh step of an exemplary process of fabricating the first example of the SRAM cell.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0060] FIG. 2 shows an SRAM cell 20 of an SRAM device according to an embodiment of this disclosure. The SRAM device may have multiple of such SRAM cells 20, and each SRAM cell 20 may be configured to store a bit.

[0061] To this end, the SRAM cell 20 can include a storage cell for storing the bit. The storage cell of the SRAM cell 20 can include four storage transistors, in particular, it can include a first storage transistor M1, a second storage transistors M2, a third storage transistor M3, and a fourth storage transistor M4. The four storage transistors M1-M4 may form two cross-coupled inverters, as in a conventional SRAM cell (see, e.g., FIG. 1).

[0062] Further, the SRAM cell 20 can include two access transistors, in particular, it can include a first access transistor M5 and a second access transistor M6. The two access transistors M5 and M6 are configured to control access to the storage cell for storing or reading the bit, as in a conventional SRAM cell (see, e.g., FIG. 1).

[0063] The SRAM cell 20 can include a stack of layer structures, wherein the stack comprises three layer structures, in particular, it can include a first layer structure 21, a second layer structure 22, and a third layer structure 23. The four storage transistors M1-M4 and the two access transistors M5 and M6 can be formed in and distributed over the stack of the three layer structures 21, 22, and 23.

[0064] In particular, two storage transistors—for example, the first storage transistor M1 and the third storage transistors M3—of the four storage transistors M1-M4 can be formed in the first layer structure 21 of the stack. The other two storage transistors—in this example, the second storage transistor M2 and the fourth storage transistor M4—of the four storage transistors M1-M4 can be formed in the second layer structure 22 of the stack. The second layer structure 22 can be adjacent to the first layer structure 21 in the stack. The two access transistors M5 and M6 can be formed in the third layer structure 23 of the stack, and the third layer structure 23 can be adjacent to the second layer structure 22 of the stack.

[0065] Each respective layer structure of the at least three layer structures 21, 22, and 23 can comprise a semiconductor material. The respective layer structure of the at least three layer structures 21, 22 and 23 may be formed from the semiconductor material. The transistors, which can be arranged in the respective layer structure 21, 22, or 23, can be based on said semiconductor material (e.g., formed using the semiconductor material).

[0066] At least two of the three layer structures 21, 22, 23 can comprise a different type of semiconductor material. For example, the first layer structure 21 may comprise a first semiconductor material, and the first storage transistor M1 and the third storage transistor M3 can be based on the first semiconductor material. Further, the second layer structure 22 may comprise a second semiconductor material 22, and the second storage transistor M2 and the fourth storage transistor M4 can be based on the second semiconductor material. Finally, the third layer structure 23 may comprise a third semiconductor material 22, and the first access transistor M5 and the second access transistor M6 can be based on the third semiconductor material. For example, the third semiconductor material may be of a different type of semiconductor material than the first semiconductor material and/or than the second semiconductor material.

[0067] In some embodiments, the first semiconductor material may form the transistor channels of respectively the first storage transistor M1 and the third storage transistor M3. The second semiconductor material may form the transistor channels of respectively the second storage transistor M2 and the fourth storage transistor M4. The third semiconductor material may form the transistor channels of respectively the first access transistor M5 and the second access transistor M6. Possible types of semiconductor materials, which may be used to form the stack, may include silicon-based semiconductor materials, 2D semiconductor materials, and semiconductor oxide materials. An alternative to the silicon-based semiconductor material may be another group IV semiconductor material, for example, germanium. For example, the third semiconductor material can comprise a 2D semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a silicon-based semiconductor material and/or an oxide semiconductor material. In another example, the third semiconductor material can comprise a silicon-based semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a 2D semiconductor material and/or an oxide semiconductor material. In another example, the third semiconductor material can comprise an oxide semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a 2D semiconductor material and/or a silicon-based semiconductor material.

[0068] It is possible that each of the three layer structures 21, 22, and 23 is made up of a different type of semiconductor material (e.g., the stack can include at least three different types of semiconductor materials). Generally, however, the stack of layer structures in this disclosure includes at least two different types of semiconductor materials. That is, one layer structure of the stack can comprise one type of semiconductor material, while another layer structure of the stack can comprise another type of semiconductor material. Notably, each layer structure 21, 22, and 23 of the stack may itself comprise only one type of semiconductor material or may itself comprise more than one type of semiconductor material. However, two layer structures 21, 22, 23 comprising a different type of semiconductor material preferably do not share a type of semiconductor material.

[0069] FIGS. 3A and 3B show a first example of the SRAM cell 20 of a SRAM device according to an embodiment of this disclosure, which builds on the embodiment shown in FIG. 2. Like elements in FIG. 2, FIG. 3A, and FIG. 3B are labelled with the same reference signs and can be implemented likewise. In particular, FIG. 3A shows the SRAM cell 20 in a sectional view, and FIG. 3B shows a schema of the SRAM cell 20.

[0070] In the example SRAM cell 20 of FIG. 3A, the first layer structure 21 and the second layer structure 22 each comprise the same type of semiconductor material, and as a particular example, they both comprise a silicon-based semiconductor material. The third layer structure 23 comprises a different type of semiconductor material than the first and the second layer structure 22 and 23, and in this particular example, it comprises at least one of a 2D semiconductor material and an oxide semiconductor material. The silicon-based semiconductor material may be silicon and/or silicon-germanium. The 2D semiconductor material may be carbon-based, e.g., graphene, or based on boron nitride or transition metal dichalcogenides. The semiconductor oxide material may be IGZO, ITO, or IZO.

[0071] With respect to a direction of stacking the three layer structures 21, 22, and 23 of the stack (along the vertical direction in FIG. 3A), the second layer structure 22 is arranged above the first layer structure 21, and the third layer structure 23 is arranged above the first layer structure 21 and the second layer structure 22. The first layer structure 21 may be arranged on a substrate or may be arranged on a base material layer.

[0072] In this first example, the SRAM cell 20 may comprise the four storage transistors M1-M4 in the so-called complementary field effect transistor (CFET) architecture. That is, the first storage transistor M1 and the second storage transistor M2 may constitute a first CFET and the third storage transistor M3 and the fourth storage transistor M4 may constitute a second CFET. At least one of the first CFET and the second CFET can be an integrated silicon-based nanosheet transistor. That is, the SRAM cell 20 may be based on one or two heterogeneously integrated silicon nanosheet transistors M1/M2 and M3/M4, respectively. The integration of the access transistors M5 and M6 based on the 2D semiconductor material and/or the semiconductor oxide material may be on top of the storage transistors M1-M4.

[0073] FIGS. 5A and 5B show a second example of the SRAM cell 20 of a SRAM device according to an embodiment of this disclosure, which builds on the embodiment shown in FIG. 2. Same elements in FIG. 2, FIG. 5A, and FIG. 5B are labelled with the same reference signs, and can be implemented likewise. In particular, FIG. 5A shows the SRAM cell in a sectional view, and FIG. 5B shows a schema of the SRAM cell 20.

[0074] In the SRAM cell of FIG. 5A, the first layer structure 21 and the second layer structure 22 each comprise, as another particular example, a 2D semiconductor material and/or an oxide semiconductor material. That is, they may be formed of the same type or of a different type of semiconductor material (in the latter case, one can be based on the 2D semiconductor material, and the other one can be based on the semiconductor oxide material). The third layer structure 23 can comprise a different type of semiconductor material from the first and/or second layer structures 22, 23, and in this further particular example, it can comprise a silicon-based semiconductor material. Again, the silicon-based semiconductor material may be silicon and/or silicon-germanium. The 2D semiconductor material may again be carbon-based, e.g., graphene, or based on boron nitride or transition metal dichalcogenides. The semiconductor oxide material may again be IGZO, ITO, or IZO.

[0075] With respect to a direction of stacking the layer structures of the stack (along the vertical direction in FIG. 5A), the second layer structure 22 is arranged above the third layer structure 23, and the first layer structure 21 is arranged above the third layer structure 23 and the second layer structure 22. The third layer structure 21 may be arranged on a substrate, or on a base material layer, or the like.

[0076] In this second example, the SRAM cell 20 may comprise the four storage transistors M1-M4 in the CFET architecture. For example, the first storage transistor M1 and the second storage transistor M2 may constitute a first CFET, and the third storage transistor M3 and the fourth storage transistor M4 may constitute a second CFET.

[0077] FIG. 3B and FIG. 5B show the schema of the respective SRAM cell 20 of FIG. 3A and FIG. 5A, which corresponds to the conventional schema shown in FIG. 1. Relevant portions in the schemas of the SRAM cell 20 are labelled and emphasized with different shadings. FIG. 3A and FIG. 5A show in the sectional view the first and the second example of the SRAM cell 20, respectively, with the corresponding relevant parts labelled and emphasized with the same different shadings. The labelled elements in the sectional view FIG. 3A and FIG. 5A correspond to the labelled wirings between the different transistors M1-M6 in the SRAM cell 20 as shown in FIG. 3B and FIG. 5B.

[0078] It can be seen in both FIG. 3A and FIG. 5A that the SRAM cell 20 may comprise, in the first example and in the second example, a first vertical element 31, a second vertical element 32, a third vertical element 33, and a fourth vertical element 34. Notably, “vertical” is defined to be along the stacking direction of the stack of the three layer structures 21, 22, and 23 of the SRAM cell 20. “Vertical” may be along the vertical direction (bottom to top) in FIG. 3A and FIG. 5A, which may correspond to a z-axis of a Cartesian coordinate system. The sectional view of the SRAM cell 20 can be along the x-axis of this Cartesian coordinate system, and may be “horizontal” (left to right) in FIG. 3A and FIG. 5A. The y-axis of the Cartesian coordinate system can be into the figure plane in FIG. 3A and FIG. 5A.

[0079] The first vertical element 31 can electrically connect a gate of the third storage transistor M3 in the first layer structure 21 to a gate of the fourth storage transistor M4 in the second layer structure 22. The second vertical element 32 can electrically connect a gate of the first storage transistor M1 in the first layer structure 21 to a gate of the second storage transistor M2 in the second layer structure 22. The third vertical element can electrically connect a source/drain of the first storage transistor M1, a source/drain of the second storage transistor M2, and a source/drain of the first access transistor M5. The fourth vertical element 34 can electrically connect a source/drain of the third storage transistor M3, a source/drain of the fourth storage transistor M4, and the source/drain of a second access transistor M6. Each vertical element 31, 32, 33, 34 accordingly can connect transistor parts that are formed in different layer structures 21, 22, 23 of the stack, wherein the different layer structures 21, 22, 23 can be arranged along the stacking direction of the stack. For example, the layer three structures 21, 22, 23 may be arranged above each along the vertical direction. In this sense, each vertical element can be at least partly vertical, but does not have to be only vertical (in its extension). Further, the first vertical element 31 can be electrically connected to the fourth vertical element 34, and the second vertical element 32 can be electrically connected to the third vertical element 33 in the first example or the second example of the SRAM cell 20. The electrical connections provided by the vertical elements 31-34 correspond to the wirings between the transistors M1-M6, which are shown in the schema of FIG. 3B and FIG. 5B respectively.

[0080] In addition, it can be seen in FIG. 3A and FIG. 5A that the SRAM cell 20, in the first and in the second example, has a source/drain of the first storage transistor M1 and a source/drain of the third storage transistor M3 connected to a ground line 39. Further, a source/drain of the second storage transistor M2 and a source/drain of the fourth storage transistor M4 are connected to a supply voltage line 38 (also “Vd” or “Vdd” in this disclosure).

[0081] Finally, it can be seen in FIG. 3A and FIG. 5A that the SRAM cell 20, in the first and in the second example, can comprise a wordline 35, a bitline 36, and a complementary bitline 37. The wordline 35 in the first example can be arranged above the stack, and can be electrically connected to the gates of the two access transistors M5 and M6. The wordline 35 in the second example can be arranged between the second layer structure 22 and the third layer structure 23, and can be electrically connected to the gates of the two access transistors M5 and M6. The bitline 36 can be arranged in the third layer structure 23 in both examples, and can be connected to the source/drain of the first access transistor M5. The complementary bitline 37 can be arranged in the third layer structure 23 in both examples, and can be connected to the source/drain of the second access transistor M6.

[0082] The ground line 39, supply voltage line 38, bitline 36, complementary bitline 37, and wordline 39 are also shown in the schema of the SRAM cell 20 in FIG. 3B and FIG. 5B.

[0083] FIG. 4A shows the first example of the SRAM cell 20 in a top view, and FIG. 4B shows the same schema as in FIG. 3B for ease of reference. FIG. 6A shows the second example of the SRAM cell 20 in a top view, and FIG. 6B shows the same schema as in FIG. 5B for ease of reference. Like elements in FIGS. 3A-4B, as well as FIGS. 5A-6B are labelled likewise and shown in the same shadings. The top views of the SRAM cell 20 in FIG. 4B and FIG. 6B show the SRAM cell 20 along the above-mentioned x-axis (left to right) and y-axis (bottom to top) of the Cartesian coordinate system, while the z-axis is into the figure plane.

[0084] The dashed squares in FIG. 4A and FIG. 6A indicate the final footprint of one SRAM cell 20. Notably, in these figures, two SRAM cells 20 are shown next to each other, which share the same bitline 36, wordline 35, ground line 39 and supply voltage line 38. As can be seen, the small footprint of the SRAM cell 20 can be achieved by the stacking of the three layer structures, comprising two transistors each, and the (vertical) connection elements used for connecting the six transistors as shown in the schema of the SRAM cell 20.

[0085] The two flip-flops (cross-coupled inverters, which are formed by the storage transistors M1-M4) can be integrated in the first layer structure 21 and the second layer structure 22, while the access transistors that may drive (read and write) the flip-flops are integrated in the third layer structure 23. In the first example of the SRAM cell 20, the access transistors M5 and M6 may be freely accessible for the wordline and the bitline(s).

[0086] The design of the SRAM cell 20 can enable greatly simplifying the interconnect scheme, as there is no need to connect the ground line 39 and the supply voltage line 38 connection to the top of the SRAM cell 20 (third layer structure 23 in the first example, first layer structure 21 in the second example). Instead, they can be connected at the beginning and the end of the SRAM arrays comprising multiple SRAM cells 20. Notably, in the integration scheme, the contact to the transistors M1 and M3 and the gates of the transistors M2 and M4 may be slightly shifted to make the connection better possible. Finally, since in the first example of the SRAM cell 20 the access transistors M5 and M6 are on top of the SRAM cell 20, a channel width of these access transistors M5 and M6 can be fine-tuned to optimize the read and write current of the SRAM cell 20, and to fine-tune the switching speed.

[0087] FIG. 7 shows a flow-diagram of a basic method 70, which may be used to fabricate the SRAM cell 20 according to an embodiment of this disclosure, in particular, the embodiment shown in FIG. 2. The method 70 may also be used to fabricate the SRAM device comprising the stack of layer structures comprising the three layer structures 21, 22, and 23.

[0088] The method 70 comprises a step 71 of forming the first layer structure 21 of the stack, wherein two storage transistors, e.g., M1 and M3, of the storage cell of the SRAM device are formed in the first layer structure 21. Further, the method 70 comprises a step 72 of forming the second layer structure 22 of the stack adjacent to the first layer structure 21, wherein two other storage transistors, e.g., M2 and M4, of the storage cell are formed in the second layer structure 22. The method 70 also comprises a step 73 of forming the third layer structure of the stack adjacent to the second layer structure 22, wherein the two access transistors M5 and M6 are formed in the third layer structure 23. The method 70 can be performed such that each layer structure of the three layer structures 21, 22, and 23 comprises a semiconductor material, wherein the transistors in the layer structure are based on the semiconductor material, and such that at least two of the three layer structures 21, 22, and 23 comprise a different type of semiconductor material. Notably, there is no particular order in which the steps 71-73 are to be performed, and no step has to be completed before another step may be started.

[0089] FIG. 8A-14B show a specific process 80 for fabricating the first example of the 3-level stacked SRAM cell 20 shown in FIGS. 3A-3B and FIGS. 4A-4B. FIGS. 8A, 9A, 10A, 11A, 12A, 13A, and 14A show over time the sectional view (showing the x-axis and z-axis) of the proposed SRAM cell 20. FIGS. 8B, 9B, 10B, 11B, 12B, 13B, and 14B show over time the top view (showing the x-axis and y-axis, and being indicative of the footprint) of the proposed integrated SRAM cell 20.

[0090] FIGS. 8A and 8B show a first step of the process 80, in which the first layer structure 21 and the second layer structure 22 are formed on top of each other. For instance, the first layer structure 21 and the second layer structure 22 may be doped to the n-type and the p-Type, respectively, and may be processed like a conventional CFET (e.g., using the Intel Flow). In particular, the first layer structure 21 and the second layer structure 22 may each be a silicon nanosheet. Source/drain (S/D) contacts may be processed in the first layer structure 21 (which may, e.g., be an N-type silicon nanosheet), wherein these S/D contacts are for the first storage transistor M1 and the third storage transistor, respectively, which are formed in the first layer structure 21. The outer S/D contacts in FIGS. 8A and 8B may be intended for ground (Gr), which may be connected to the S/D of the first storage transistor M1 and to the S/D of the third storage transistor M3 in the final SRAM cell 20.

[0091] FIGS. 9A and 9B show a second step of the process 80, in which S/D contacts are also made in the second layer structure 22 (which may, e.g., be a p-type silicon nanosheet), wherein these S/D contacts made in the second layer structure 22 are connected to the S/D contacts made in the first layer structure 21, in the middle of SRAM cell 20. The S/D contacts made in the second layer structure 22 are for the second storage transistor M2 and the fourth storage transistor M4, respectively, which are formed in the second layer structure 22. The connection may be realized by forming the third vertical element 33 and the fourth vertical element 34. The third vertical element 33 at this stage of the process 80 connects the S/D for the first storage transistor M1 with the S/D for the second storage transistor M2. The fourth vertical element 34 at this stage of the process 80 connects the S/D for the third storage transistor M3 and the S/D for the fourth storage transistor M4.

[0092] FIGS. 10A and 10B show a third step of the process 80, in which gate contacts are processed in the first layer structure 21 and the second layer structure 22, in particular, for the storage transistors M1-M4. The gate contacts are processed by forming the first vertical element 31 and the second vertical element 32. At this stage of the process 80, the first vertical element 31 connects a gate for the first storage transistor M1 in the first layer structure 21 to a gate for the second storage transistor M2 in the second layer structure 22, and the second vertical element 32 connects a gate for the third storage transistor M3 in the first layer structure 21 to a gate of the fourth storage transistor M4 in the second layer structure 22.

[0093] FIGS. 11A and 11B show a fourth step of the process 80, in which a further S/D contact is formed in the second layer structure. This S/D contact is intended for the supply voltage (Vd), which may be supplied to the S/D of the second storage transistor M2 and to the S/D of the fourth storage transistor M4 in the final SRAM cell 20.

[0094] FIGS. 12A and 12B show a fifth step of the process 80, in which the storage transistors M1-M4 are connected. In particular, the gates of the first and the second storage transistor M1 and M2, which are connected to each other by the first vertical element 31, are further connected to the S/D contact of the third and the fourth storage transistor M3 and M4, which are already connected to each other by the fourth vertical element. The further connection is realized by connecting the first vertical element 31 to the fourth vertical element 34. Further, the S/D contacts of the first and the second storage transistor M1 and M2, which are connected to each other by the third vertical element 33, are further connected to the gates of the third and the fourth storage transistor M3 and M4, which are already connected to each other by the second vertical element. This further connection is realized by connecting the third vertical element 33 to the second vertical element 32.

[0095] FIGS. 13A and 13B show a sixth step of the process 80, in which the bitline 36 and the complementary bitline 37 are formed, and in which further contacts to the storage transistors M1-M$ are processed by vertically extending the third vertical element 33 and the fourth vertical element 34 (as also indicated by the squares in FIG. 13B).

[0096] FIGS. 14A and 14B show a seventh step of the process 80, in which the third layer structure 23 is processed and the wordline 35 is processed. Processing the third layer structure 23 includes forming the first and second access transistors M5 and M6. The bitline 36 is connected to the S/D of the first access transistor M5, and the complementary bitline 37 is connected to the S/D of the second access transistor M6. The wordline 35 is connected to the gates of the two access transistors M5 and M6. This step concludes the processing of the SRAM cell 20.

[0097] Two or more SRAM cells 20 may be processed in parallel according to this process 80. FIG. 14B shows again that this process 80 finally achieves a SRAM cell 20 with a very small footprint. Nevertheless, the SRAM cell 20 can still be wired according to a conventional SRAM schema, for example as shown in FIG. 1.