CLOCK AND DATA RECOVERY CIRCUIT FROM AN N-PULSE AMPLITUDE MODULATION SIGNAL

Abstract

An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

Claims

1. Apparatus for recovering clock and data from a multilevel pulse amplitude modulated signal received as an input signal by the apparatus, wherein the input signal has a first symbol rate and transfers two bits per symbol, wherein the apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop, wherein the voltage-controlled oscillator outputs a clock signal that is provided as a first input signal to the phase detector, characterized in that the apparatus comprises a sampler configured to extract an MSB signal from the input signal, wherein the output of the sampler is connected with an input of the phase detector to provide the MSB signal as a second input to the phase detector; an interleave circuit configured to receive the input signal and generates two output signals having a second symbol rate which is half of the first symbol rate of the input signal, a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal, and a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

2. Apparatus according to claim 1, wherein the output signals of the interleave circuit are phase-shifted by 180°.

3. Apparatus according to claim 2, wherein during a time window two consecutive symbols of the input signal contained in the output signals of the interleave circuit are overlapping in the time domain.

4. Apparatus according to claim 1, wherein the logical gate is an XNOR gate.

5. Apparatus according to claim 1, wherein the interleave circuit comprises two track and hold circuits.

6. Apparatus according to claim 1, wherein the interleave circuit is configured to receive the clock signal from the voltage-controlled oscillator.

7. Apparatus according to claim 1, wherein the converter is configured to receive the clock signal from the voltage-controlled oscillator.

8. Method for recovering clock and data signals from a multilevel pulse amplitude modulated signal transferring two bits per symbol at a first symbol rate, comprising receiving the multilevel pulse amplitude modulated signal as input signal; extracting an MSB signal from the input signal; providing the MSB signal to a phase detector included in a clock and data recovery loop; generating from the input signal two output signals having a second symbol rate which is half of the first symbol rate of the input signal; receiving the output signals at a logical gate generating an enable signal for the phase detector indicating symmetrical transitions in the input signal; and converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

9. Method according to claim 8, further comprising generating a clock signal and providing the clock signal to the phase detector included in the clock and data recovery loop.

10. Method according to claim 9, further comprising providing the clock signal to an interleave circuit generating the output signals having the second symbol rate and to a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

11. Method according to claim 8, further comprising phase shifting the output signals by 180°.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Exemplary embodiments of the present disclosure are illustrated in the drawings and are explained in more detail in the following description. In the figures, the same or similar elements are referenced with the same or similar reference signs. It shows:

[0026] FIG. 1A a generic block diagram of a conventional CDR circuit;

[0027] FIG. 1B another generic block diagram of a conventional CDR circuit;

[0028] FIGS. 2A, 2B two examples of PAM signals with N=2 and N=4 modulation levels;

[0029] FIG. 3A transitions between voltage levels of a PAM-2 signal;

[0030] FIG. 3B transitions between voltage levels of a PAM-4 signal;

[0031] FIG. 4 a CDR circuit for a PAM-4 signal utilizing only symmetrical transitions;

[0032] FIG. 5A a CDR circuit for a PAM signal according to the present disclosure;

[0033] FIG. 5B a timing diagram of signals of the CDR circuit of FIG. 5A;

[0034] FIG. 5C a schematic block diagram of the converter included in the CDR circuit shown in FIG. 5A;

[0035] FIG. 5D the CDR circuit shown in FIG. 5A illustrating the functioning with a PAM-6 signal as input signal; and

[0036] FIG. 6 a schematic flow diagram of the method according to the present disclosure.

[0037] In the figures the same or similar components are labelled with the same or similar reference signs. The direction of signal transmission is indicated with arrows.

DETAILED DESCRIPTION

[0038] FIG. 1A shows a generic block diagram of a CDR circuit 100a. The CDR circuit 100a includes a phase detector (PD) 101, which receives a data input signal Din as a first input. An output signal of the PD 101 is applied to a low-pass filter (LPF) 102, which suppresses high-frequency components in the output signal of the PD 101. The LPF 102 is connected with a voltage-controlled oscillator (VCO) 103, the oscillation frequency of which is tuned by an output signal of the LPF 102. An output signal CKout of the VCO 103 represents a clock signal and is transmitted via a feedback loop 104 as a second input signal to PD 101. The PD 101 generates an output signal proportional to the phase difference between input signals Din and CKout. The PD 101 drives the oscillation frequency of the VCO 103 such that phase and frequency of data input signal Din and clock signal CKout are the same. The ensemble of components 101-104 forms a CDR loop 107 within the CDR circuit 100a. The data input signal Din is also supplied to flip-flop 106 where it is stored. The flip-flop 106 is triggered with the clock signal CKout. As a result, the flip-flop outputs a data output signal Dout in synchronicity with the clock signal CKout.

[0039] The circuit diagram shown in FIG. 1A is a simplified because a perquisite enabling a CDR circuit to acquire the right phase and frequency of the clock signal CKout is an on-chip clock source oscillating close to the target data frequency which is the frequency of the clock signal CKout. A CDR circuit 100b taking this prerequisite into account is illustrated in FIG. 1B.

[0040] Compared with CDR circuit 100a, the CDR circuit 100b further comprises a crystal oscillator (XTAL) 108 providing a reference clock signal that is supplied to a phase frequency detector (PFD) 109. An output signal of the PFD 109 passes through a low-pass filter (LPF2) 111. An output signal of the LPF2 111 is transmitted as a second input signal to the VCO 103. The output signal of the VCO 103 passes through the frequency divider 112 sending the frequency divided version of the output signal is the VCO 103 as a second input signal to the PFD 109. The VCO 103, frequency divider 112, PFD 109 and LPF 111 form a phase locked loop (PLL), which assists the CDR loop 107 and tunes the VCO's 103 center frequency coarsely while the PD 101 tunes the VCO 103 finely.

[0041] The CDR circuit 100b illustrated in FIG. 1B works well for NRZ signals. However, when the number N of modulation levels of a pulse amplitude modulation signal (PAM) (PAM-N, N≥4) increases, the performance required by the PD becomes challenging. A PAM signal with N modulation levels is designated with the acronym PAM-N.

[0042] FIGS. 2A and 2B illustrate two examples PAM signals with N=2 and N=4 modulation levels, i.e a PAM-2 and a PAM-4 signal. The two voltage levels L1 and L2 of the PAM-2 signal are associated with two different bits, namely the low voltage level L1 with 0 and the high voltage level L2 with 1. The PAM-2 signal can transmit one bit per clock cycle.

[0043] The four voltage levels L1-L4 of the PAM-4 signal are associated with pairs of bits, namely the lowest voltage level L1 with 00, the next voltage level L2 with 01, the next higher voltage level L3 with 10, and the highest voltage level L4 with 11. For this reason, the PAM-4 signal can transmit two bits per clock cycle, which makes PAM-4 modulation very attractive for high-speed data communication networks.

[0044] However, the clock and data recovery from PAM-4 signals is challenging compared to the clock and data recovery from PAM-2 signals, which will be explained in the following with reference to FIGS. 3A and 3B.

[0045] FIG. 3A shows transitions from voltage level L1 to voltage level L2 and conversely for a PAM-2 signal. The transition edges intersect the medium voltage Vmed between voltage level L1 and L2 at the same point in time t0. The clock signal CKout, for instance its raising edge, is aligned with this point in time t0.

[0046] For a PAM-4 signal the alignment of the clock signal CKout is more complicated because between the four voltage levels there are 12 non-uniform transition edges as it is shown in FIG. 3B. For each one of the four voltage levels L1-L4 there are three possible transitions to a different voltage level. For instance, from voltage level L4 there are three possible transitions to voltage levels L1, L2, and L3. From voltage level L3 there are also three possible transitions to voltage levels L1, L2, and L4, etc. The transition edges intersect with the medium voltage Vmed at three different points in time which are indicated as t−1, t0, and t+1. The intersections are emphasized with circles in FIG. 3B. If the points in time t−1, t0, and t+1 are used to synchronize the clock signal CKout like in the case of the PAM-2 signal, the clock signal CKout cannot be properly aligned since there is no stable reference point t0 like for a PAM-2 signal and, as a result, a large amount of clock jitter is generated unless appropriate counter measures are taken.

[0047] FIG. 4 shows an advanced solution of a circuit 400 for clock and data recovery for PAM-4 signals have been proposed, where only the symmetrical transitions occurring between the topmost and lowest levels or the middle-low and the middle-high ones are used to align the clock signal CKout. To achieve the goal of detecting symmetrical transitions, the CDR circuit 400 detects the transitions after decoding the PAM-4 signal into binary formats. To this end, the PAM-4 signal Din is converted within a converter 401. Specifically, the converter 401 employs three samplers 402-404 including analogue-to-digital converters (ADC). The sampler 402 detects the highest voltage level L4 and outputs the most significant bit (MSB) signal corresponding to the first bit of the bit pairs shown in FIG. 2B. The second bit corresponds to the least significant bit (LSB) with a further modification. If the MSB of a bit pair is 1, then the LSB is denominated upper slice LSB and is labelled LSB+. If the MSB of a bit pair is 0 then the LSB is denominated lower slice LSB is labelled LSB−.

[0048] The sampler 403 detects the upper slice LSB+ of the PAM-4 signal, and the sampler 404 detects the lower slice LSB− of the PAM-4 signal. A re-timer stage 406 assures that the output signals MSB, LSB+, and LSB− of the samplers 402-404 remain within a predefined time window. The importance of the timing increases as the data rate of data transmission increases. The detected MSB signal triggers 2:1 multiplexer 407 that functions as a selector switch, which sends the least significant bit LSB to an output line 408. The 2:1 multiplexer 407 selects either the LSB+ signal from sampler 403 if the MSB is 1 or the LSB− signal from sampler 404 if the MSB is 0. The MSB signal is outputted on output line 409. The time matching between the MSB and LSB signals is maintained by appropriately dimensioned delays 411, 412.

[0049] The converter works as follows. If the signal Din at a given clock cycle is at voltage level L1, then sampler 402 outputs a 0 which controls the 2:1 multiplexer 407 to output the LSB− signal of sampler 404 corresponding to a bit value 0. If the signal Din at a given clock cycle is at voltage level L2, then sampler 402 outputs a 0 which controls the 2:1 multiplexer 407 to output the LSB− signal of sampler 404 corresponding to a bit value 1. If the signal Din at a given clock cycle is at voltage level L3, then sampler 402 outputs a bit value 1, which controls the 2:1 multiplexer 407 to output the LSB+ signal of sampler 403 corresponding to a bit value 0. If the signal Din at a given clock cycle is at voltage level L4, then sampler 402 outputs a bit value 1, which controls the 2:1 multiplexer 407 to output the LSB+ signal of sampler 403 corresponding to a bit value 1. As a result, the converter outputs a stream of MSB and LSB bits on the output lines 408 and 409. Table 1 summarizes this behaviour.

TABLE-US-00001 TABLE 1 Din MSB LSB− LSB+ L1 0 0 Not selected L2 0 1 Not selected L3 1 Not selected 0 L4 1 Not selected 1

[0050] It is noted that “not selected” means that the multiplexer 407 selects the respective other sampler.

[0051] The CDR circuit 400 comprises the CDR loop composed of the phase detector 101, the low-pass filter 102 and the voltage-controlled oscillator 103 that have already been described with reference to FIG. 1A. The MSB signal from output line 409 is provided as input signal to the phase detector 101 via connection 413. The phase detector 101 generates an output signal to align the VCO 103 with the MSB signal provided that PD 101 receives an enable signal En from transition detector 414. The transition detector is configured to output the enable signal only when symmetrical transitions in the input signal Din occur, namely from voltage level L1 to L4 or from L2 to L3 and vice versa. Transition detector 414 determines the symmetrical transition by analysing each two consecutive MSBs and LSBs data information. For instance, in FIG. 2B a symmetrical transition from L2 to L3 occurs once the MSB is switched from 0 to 1 and at the same time LSB is changed from 1 to 0. These symmetrical transitions intersect with medium voltage level Vmed at the same point in time t0 to control VCO 103. Thus, the CDR circuit 400 utilizes transitions from voltage level L1 to voltage level L4 (and also opposite direction from L4 to L1) or from voltage level L2 to voltage level L3 (and also in opposite direction), to control the VCO 103 which generates the clock signal CKout. In this way, jitter of the clock signal CKout is avoided. The clock signal CKout is also provided to converter 401 and to flip-flop 416 to synchronize MSB and LSB output streams.

[0052] It should be noted that the architecture presented in FIG. 4, as well as the other known architectures, employs ADCs within the samplers 402-404, which require a clock. The symmetrical transitions are detected after they are processed and delayed by the ADCs. Therefore, a mistuned clock phase can lead to wrong ADC outputs and, consequently, wrong data transitions. This algorithm would become more challenging for higher modulation orders, i.e for N>4.

[0053] Consequently, there remains a desire for faster transition detection and clock recovery to accelerate clock acquiring and avoid error propagation through a system.

[0054] FIG. 5A shows an embodiment of a proposed clock and the data recovery (CDR) circuit 500. The CDR circuit 500 comprises the CDR loop 107 composed of the phase detector 101, a low pass filter 102, a voltage-controlled oscillator 103 and a feedback loop 104. A PAM-4 input signal Din is provided to a sampler 402 to detect the most significant bit MSB in the input signal and to output the MSB signal to the phase detector 101. The input signal Din is also provided to a time interleave circuit 501 comprising two half-rate track and hold circuits 502, 503. In FIG. 5A all levels L1-L4 of the input signal are shown simultaneously while in reality at each clock cycle only one symbol corresponding to one level is transferred. The half rate track and hold circuits 502, 503 sample at rising and falling edges of the clock signal CKout, respectively, and output half rate signals HR1 and HR2 on lines 506, 507, respectively. The phase of the of signals HR1 and HR2 is away by 180°.

[0055] FIG. 5B shows the timing of the input signal Din, the clock signal CKout and the half rate signals HR1 and HR2. The track and hold circuit 502, samples the data at a rising edge RE of the clock and holds the data during the next half clock cycle until the next rising edge RE of the clock occurs. The track and hold circuits 503, samples the data at a falling edge FE of the clock and holds the data during the next half clock cycle until the next falling edge FE of the clock occurs. Thus, it can be concluded that each track and hold circuit samples every output of 2-bit information of the PAM-4 input signal either on rising or falling edges of the clock and holds it for the next half cycle of the clock signal CKout. Specifically, a rising edge RE of a clock pulse triggers the track and hold circuit 502 which holds the signal Din for a half clock cycle until a next rising edge RE of the next clock pulse is detected. The falling edge FE of clock pulse triggers the track and hold circuit 503 which holds the signal Din for a half clock cycle until the next falling FE edge of the next clock pulse is detected. The same reasoning applies if the track and hold circuits are interchanged. In other words, the high-speed PAM-4 input signal Din is converted into two separate PAM-4 signals HR1, HR2 having only have half of the bit rate of the input signal Din.

[0056] FIG. 5A displays a time window W. A stored level of input signal Din is outputted as half rate signal HR1 from the beginning to the end of time Window W. During the time window W, a consecutive level of the input signal Din is outputted as half rate signal HR2 by track and hold circuit 503. A corresponding situation is displayed in FIG. 5B. A stored level of input signal Din is outputted as half rate signal HR2 from the beginning to the end of time Window W. During the time window W, a consecutive level of the input signal Din is outputted as half rate signal HR1 by track and hold circuit 502. Thus, during time window W two consecutive symbols carrying two bit pairs of the input signal Din contained in the half rate signals HR1, HR2, are overlapping in the time domain.

[0057] The half rate signal HR1 is a supplied to an input of an analogue XNOR gate 508, while at the same time the half rate signal HR2 is supplied to an inverted input of the XNOR gate 508. By computing an analogue XNOR function between the two interleaved output signals HR1 and HR2, symmetrical transitions between the voltage levels L1-L4 can be evaluated as shown in Table 2. In lines 3, 5, 8, and 10 of Table 2 the symmetrical transitions are highlighted. The transition edges for all these transitions intersect with the medium voltage Vmed at the point in time t0. Hence, VCO 103 is properly controlled and no jitter in the clock signal CKout is generated.

TABLE-US-00002 TABLE 2 Inverted # HR1 HR2 HR2 XNOR 1 L4 L3 L2 0 2 L4 L2 L3 0 3 L4 L1 L4 1 4 L3 L4 L1 0 5 L3 L2 L3 1 6 L3 L1 L4 0 7 L2 L4 L1 0 8 L2 L3 L2 1 9 L2 L1 L4 0 10 L1 L4 L1 1 11 L1 L3 L2 0 12 L1 L2 L3 0

[0058] The output signal of the analogue XNOR gate is used as an enable signal for the phase detector 101. Consequently, only symmetrical transitions are used to align the clock signal CKout.

[0059] The half rate signals HR1 and HR2 are provided as input signals to a converter 502 that generates an MSB and an LSB bit stream as output signals on lines 503, 504. FIG. 5C displays an implementation of converter 502 in detail. The currents I.sub.ADC Up and I.sub.ADC Low set the threshold levels for upper and lower levels of the PAM-4 signal. The shown design of converter 502 has been published by A. Malignaggi et al. [1]. However, the specific design of converter 502 is not part of the present disclosure in the sense that any other converter design could be used as well that converts the half rate signals HR1 and HR2 an MSB and an LSB bit stream.

[0060] FIG. 5D shows the CDR circuit 500 of FIG. 5A when it receives a PAM-6 signal as input signal Din having six different levels L1-L6. Like for a PAM-4 signal described in connection with FIG. 5A, the input signal is converted into two half rate signals HR1 and HR2 to determine symmetrical transitions for synchronizing the clock signal CKout. For the sake of clarity, not all possible transitions between the levels L1-L6 are indicated in FIG. 5C. The working principle of the CDR circuit remains the same even for PAM-8 (three bits of information) signals or PAM-N signals with N>8.

[0061] FIG. 6 shows a flow diagram of a method for recovering clock and data signals from a multilevel pulse amplitude modulated signal transferring two bits per symbol at a first symbol rate. In step S1 the multilevel pulse amplitude modulated signal is received as input signal Din. In step S2 an MSB signal is extracted from the input signal Din. In step S3 the MSB signal is provided to a phase detector 101 included in a clock and data recovery loop 107. In step S4 two output signals HR1, HR2 having a second symbol rate, which is smaller than half of the first symbol rate of the input signal Din, are generated from the input signal Din. In step S5 the output signals HR1, HR2 are received at a logical gate 508 generating an enable signal En for the phase detector 101 indicating symmetrical transitions in the input signal. Finally, in step S6 the output signals HR1, HR2 from the interleave circuit 501 are converted into an MSB and an LSB bit stream. Even though the steps are described in a sequential order, they rather take place in parallel.

[0062] The early evaluation of symmetrical transitions helps the CDR loop 107 to lock faster. Furthermore, the bit error rate of the CDR circuit 500 is improved and reduces the detection error probability due to a wrong clock phase. Another advantage of the CDR circuit 500 is that its complexity does not increase with an increasing number of levels N of a PAM-N signal.

[0063] Individual components or functionalities of the present invention are described in the embodiment examples as software or hardware solutions. However, this does not mean that a functionality described as a software solution cannot also be implemented in hardware and vice versa. Similarly, mixed solutions are also conceivable for a person skilled in the art, in which components and functionalities are simultaneously partially realized in software and hardware.

[0064] In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” does not exclude a plurality.

[0065] A single unit or device may perform the functions of multiple elements recited in the claims. The fact that individual functions and elements are recited in different dependent claims does not mean that a combination of those functions and elements could not advantageously be used.

Non-Patent Literature

[0066] [1] A. Fatemi, G. Kahmen and A. Malignaggi, “A 96-Gb/s PAM-4 Receiver Using Time-Interleaved Converters in 130-nm SiGe BiCMOS,” in IEEE Solid-State Circuits Letters, vol. 4, pp. 60-63, 2021, 10.1109/LSSC.2021.3059254.