DIGITAL ANALOG MULTIPLICATION DRIVING METHOD FOR A DISPLAY DEVICE

Abstract

The present disclosure provides operating methods and apparatuses of a display device. In an implementation, a method includes driving each pixel for each frame, wherein a plurality of pixels of the display device are disposed in an array of rows and columns, where a period of one frame comprises Nd time sections, one of Ba different voltage levels is applied to the pixel in each time section, Ba is greater than or equal to 3, the sum of the results of multiplying the length of each time section by the applied voltage level corresponds to a brightness, grey scale color, or luminance. One of suitable applications of the present invention is a micro-LED display.

Claims

1. An operating method of a display device, comprising: driving each of a plurality of pixels of a display device for each of a plurality of frames, wherein the plurality of pixels are disposed in an array of rows and columns, a period of each of the plurality of frames comprises Nd time sections, one of Ba voltage levels is applied to a pixel in each of the Nd time sections, wherein Ba is greater than or equal to 3, and a sum of results of multiplying a length of each of the Nd time sections by a respective one of the Ba voltage levels applied corresponds to one of a brightness, a grey scale color, or a luminance.

2. The operating method according to claim 1, wherein Ba equals 2.sup.Na, and Na×Nd is equals a total bit depth of pixel data.

3. The operating method according to claim 1, wherein a M.sup.th time section of the Nd time sections has a length that is Ba times of a length of a (M−1).sup.th time section, wherein M is an integer from 2 to Nd.

4. The operating method according to claim 1, wherein the display device is a micro-LED display.

5. A display device, comprising: a plurality of pixels disposed in an array of rows and columns, wherein a period of a frame comprises Nd time sections, one of Ba voltage levels is applied to a pixel in each of the Nd time sections, wherein Ba is greater than or equal to 3, a sum of results of multiplying a length of each of the Nd time section by a respective one of the Ba voltage levels corresponds to one of a brightness, a grey scale color, or a luminance; and a driver that drives each pixel for the frame.

6. The display device according to claim 5, wherein Ba equals 2=.sup.Na, and Na×Nd equals a total bit depth of pixel data.

7. The display device according to claim 5, wherein a M.sup.th time section of the Nd time sections has a length that is Ba times of a length of a (M−1).sup.th time section, wherein M is an integer from 2 to Nd.

8. The display device according to claim 5, wherein the display device is a micro-LED display.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0014] To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. The accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

[0015] FIG. 1 shows a simplified diagram of a PWM light control;

[0016] FIG. 2 shows an example of basic PWM waveforms for driving pixels;

[0017] FIG. 3 shows an example of waveforms for driving pixels;

[0018] FIG. 4 shows another example of waveforms for driving pixels;

[0019] FIG. 5 shows another example of waveforms for driving pixels for 16 grey scales;

[0020] FIG. 6 shows an example of waveforms for driving pixels with ideal binary sections;

[0021] FIG. 7 shows a waveform for data ‘2106’ for the pure digital driving;

[0022] FIG. 8 shows a waveform for data ‘2106’ for “Digital 6, Analog 2 Multiplication” driving;

[0023] FIG. 9 shows a luminance reference map for “Digital 6, Analog 2 Multiplication” driving;

[0024] FIG. 10 shows several examples of pixel waveforms for “Digital 6, Analog 2 Multiplication” driving;

[0025] FIG. 11 shows a waveform of data ‘63179’ for the pure digital driving;

[0026] FIG. 12 shows a luminance reference map for “Digital 9 and Analog 2 Multiplication” driving;

[0027] FIG. 13 shows several examples of pixel waveforms for “Digital 9, Analog 2 Multiplication” driving;

[0028] FIG. 14 shows a waveform for data ‘2106’ for the pure digital driving;

[0029] FIG. 15 shows a luminance reference map for “Digital 4, Analog 3 Multiplication” driving;

[0030] FIG. 16 shows several examples of pixel waveforms for “Digital 4, Analog 3 Multiplication” driving;

[0031] FIG. 17 shows a comparison of T.sub.DP between different driving schemes for the number of lines from 800 to 1,700; and

[0032] FIG. 18 shows a comparison of T.sub.DP between different driving schemes for the number of lines from 1,700 to 2,600.

DESCRIPTION OF EMBODIMENTS

[0033] The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are only some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protected scope of the present invention.

[0034] FIG. 1 shows a simplified diagram of a PWM light control. The PWM is widely used for driving a light emitting diode (LED). The LED is controlled according to the pulse width so that the LED has different accumulate energy and then has different luminance to achieve different grey scale color. The PWM is to modulate turn-on ratio, or called duty cycle in a period. The higher turn-on ratio be in the period, the higher accumulate energy the LED gets, and the higher accumulate energy the LED gets, the higher luminance the LED provides, and vice versa. For display applications, the PWM period is often set the same as a frame period.

[0035] A pixel may be a circuit for emitting light with a specified color and a specified brightness, grey scale, or luminance. A set of LEDs with red, blue, and green colors may be used for each pixel. However, the embodiments of the present invention focus on controlling brightness, grey scale, or luminance of each LED.

[0036] FIG. 2 shows an example of basic PWM waveforms by a Binary Address Group (BAG) scheme. The BAG scheme is based on digital driving or PWM scheme. It only has a two-state signal (1 or 0) for driving pixels on a display device. Original grey scale data is converted into n-bit binary data, and then a PWM period is divided into n time sections. The length of each time section is not the same but the time length relationship from small to large is 1T, 2T, 4T, 8T, . . . . The length of the last time section is 2{circumflex over ( )}(n−1)*T. The order of time sections can be changed in any order. The only restriction is the total length of time sections should be (2{circumflex over ( )}n−1)*T. In an example shown in FIG. 1, n=4 and time sections are arranged from small to large. The total energy or luminance of an LED is in proportion to the sum of the areas under the waveform (grey areas marked “1”). It can be seen that the LED can be driven only by changing states n times (n is 4 in FIG. 1) in one PWM period (for example, changing states at the beginning of 1T, 2T, 3T, and 4T), then we can get 2{circumflex over ( )}n steps (16 steps in FIG. 1) of different energy or luminance can be obtained. The 2{circumflex over ( )}n steps can be used for displaying grey scales and the bit depth of pixel data is n.

[0037] Since each time section above corresponds to one bit data, this time section is also referred to as “a data section” below, and in particular, since in most examples below, the data is binary data, this time section is also referred to as “a binary section”, and the length of this time section is referred to as “a binary length”.

[0038] In general, pixels are disposed in an array of p rows (p scan lines) and q columns (q data lines) on a display device. The array may correspond to all or a part of the display device. The pixel may include a thin film transistor (TFT) or a silicon substrate. All pixels need to be driven in one frame time. The value of q has no relation to the driving time sequences, and the driving time sequences are repeated for q columns, and thus q can be any number, and it can be just assumed to be one for easy to understand.

[0039] FIG. 3 shows an example of waveforms for driving 7 scan lines (7 pixels), and each pixel is driven with 3 bits (hereinafter, each waveform for driving a pixel is also referred to as “a driving sequence”). At the initial part of SF1 (sub-field 1), SF2, and SF4, a high signal means being turned ON, and a low signal means being turned OFF, namely, state changes are performed. First, each line is driven with bit1 (least significant bit (LSB)). After a time period 1T, the same line is driven with bit 2. After a time period 2T, the same line is driven with bit 3 (most significant bit (MSB)). After a time period 4T, this time frame ends.

[0040] In this example, the number of bits for specifying a brightness, grey scale color, or illuminance is n=3, and the sum of the weights of bit1, bit2, and bit3 is 2{circumflex over ( )}n−1 is 7, so one frame time is divided into 7 sub-fields (SFs). However, no processing is performed in SF3, SF5, SF6, and SF7 for driving pixels, namely, a duration of time is not used efficiently. In this method, if the number of lines is p, p*(2{circumflex over ( )}n−1) SFs are needed for driving data.

[0041] FIG. 4 shows another example of driving pixels in an efficient way. The pixel on the Scan L1 line is driven in SF1 for bit 1, SF2 for bit 2, and SF4 for bit 3. For the Scan L2 line, one SF is shifted compared to the Scan L1 line, and the pixel is driven in SF2 for bit 1, SF3 for bit 2, and SF5 for bit 3. For the Scan L3 line, one SF is shifted compared to the Scan L2 line, and the pixel is driven in SF3 for bit 1, SF4 for bit 2, and SF6 for bit 3. The same operations are repeated for the Scan L4 line to the Scan L7 line.

[0042] This kind of driving scheme is called “Binary Address Group (BAG)” driving. The characteristic of the BAG is that the number of small periods for driving pixel data is p*n, which is much smaller than p*(2{circumflex over ( )}n−1) when n becomes larger such as 10, 12, or 14. Only 7*3=21 data driving periods are needed in the example of FIG. 4, while 7*7=49 data driving periods are needed in the example of FIG. 3, because the SFs with a turn-on signal cannot be simultaneously processed.

[0043] More efficient driving waveforms in one frame can be constructed based on the BAG scheme. It is assumed that the number of rows p is 15, and bit depth n is 4. FIG. 5 shows another example of waveforms for driving pixels for 16 grey scales or 16 linear steps from 0 to 15 for all pixels in 15 lines.

[0044] In FIG. 5, one frame time T.sub.FRAME is divided into 15 sub-field times T.sub.SF because n=4 and 2{circumflex over ( )}n−1 is 15. Therefore, T.sub.FRAME equals 15*T.sub.SF in this example. Next, each SF is divided into 4 periods for each bit for a state change. This period is called “available data driving time” represented by T.sub.DP, and T.sub.DP is a unit of time for constructing a driving sequence. Therefore, T.sub.SF equals 4*T.sub.DP in this example. In the BAG scheme, the binary length corresponding to each bit is mainly produced by combining SFs. If we set the starting time of the Scan L1 line to be located at SF1, and the order of the binary length is 1, 2, 4, and 8, bits 1, 2, 3, and 4 for state changes are located in SF1, SF2, SF4, and SF8, respectively.

[0045] As mentioned above, there are 15 T.sub.SF in one T.sub.FRAME and 4 T.sub.DP in one T.sub.SF. Therefore, there are 60 T.sub.DP in one frame (or in one T.sub.FRAME). 60 T.sub.DP are numbered from 1 to 60 and each position is called an absolute position (AbsPos) in one frame. In FIG. 5, for Scan L1 line, bit 1 is at AbsPos 1, bit 2 is at AbsPos 6, bit 3 is at AbsPos 15, and bit 4 is at AbsPos 32. For Scan L2 line, the starting point is located at first T.sub.DP of SF2 which is at AbsPos 5 in this frame. Bits 1, 2, 3 and 4 of Scan L2 line are located at AubPos 5, 10, 19 and 36. For Scan L3 line to Scan L15 line, bits 1, 2, 3, and 4 are located similarly. The periods for holding states for bits 1, 2, 3, and 4 are expected to be 1×, 2×, 4×, and 8× (multiples of 1, 2, 4, and 8), respectively. However, the actual periods are 5*T.sub.DP, 9*T.sub.DP, 17*T.sub.DP, and 29*T.sub.DP, as shown in TABLE 1 below. It should be noted that for example, for Scan L1 line, 29*T.sub.DP comes from the time length between bit 4 of SF8 of the current frame and bit 1 of SF1 of the next frame. The series 5, 9, 17, and 29 do not comply with binary relationships 1×, 2×, 4×, and 8×. There exists errors in this solution. Therefore, serial binary sections are non-ideal.

TABLE-US-00001 TABLE 1 Binary Section Length by Basic BAG Scheme (Bit Depth = 4, Line = 15) Time Length T.sub.SF + T.sub.DP Value Multi Binary sec 1 = T.sub.SF* 1 + T.sub.DP* 1  = 5 1 Binary sec 2 = T.sub.SF* 2 + T.sub.DP* 1  = 9 1.8 Binary sec 3 = T.sub.SF* 4 + T.sub.DP* 1 = 17 3.4 Binary sec 4 = T.sub.SF* 8 + T.sub.DP* − 3 = 29 5.8 Sum = T.sub.SF* 15 + T.sub.DP* 0 = 60 12

[0046] FIG. 6 shows an example of waveforms for driving pixels with ideal binary sections. In order to solve the above problem of non-ideal binary sections, the driving waveform is modified. In this example, bit depth n is 4, and the number of lines is 12. First, SFs are divided into 5 periods but not 4 periods. It means T.sub.SF equals 5*T.sub.DP. The number of periods in one SF is defined as the number of cycles (CY). So, the CY is set to be n+1, which is bit depth+1. Second, a grey scale unit (GSU) is determined. GSU corresponds to the number of T.sub.DP corresponding to the minimum binary section. In this case, in order to construct a sequence of ideal binary sections, the total length of binary sections will be a multiple of 15, because 1+2+4+8=15. The number of lines is 12, and GSU is selected to be 4. Since the time length of GSU is 4*T.sub.DP, the total length of binary sections is 4*15 which equals 60. Therefore, T.sub.FRAME=60*T.sub.DP. Since CY=5, each T.sub.SF equals 5*T.sub.DP, there are 12 SFs in one frame, and thereby each SF can be a starting point of one line. Therefore, this is a solution with ideal binary sections for the case where n=4, and the number of lines=12.

[0047] Besides, there is one difference between the basic BAG scheme (FIG. 5) and the BAG scheme with ideal binary sections (FIG. 6). We can observe that all T.sub.DP in one SF are used for driving a pixel in FIG. 5. But there is one T.sub.DP which is not used for driving a pixel in FIG. 6. It is the second T.sub.DP position in every SF. The T.sub.DP without driving a pixel is an “idle” period in each SF. It is an unavoidable sacrifice in timing when trying to use the BAG scheme with ideal binary sections.

[0048] The T.sub.DP position in one SF is defined with a relative position (RelPos) so as to be easily described below. For each AbsPos, the relationship between AbsPos and RelPos is

AbsPos=(k−1)×CY+RelPos  (1)

where AbsPos belongs to the k.sup.th SF.

[0049] TABLE 2 shows line numbers to be turned ON for each sub-field and each RelPos in the waveforms in FIG. 6. It is easy to check when the waveform sequence becomes long and lines increase significantly. TABLE 3 shows binary section length by the BAG Scheme with ideal binary sections (bit depth=4, the number of lines=12).

TABLE-US-00002 TABLE 2 Line numbers to be turned ON by BAG Scheme with Ideal Binary Sections (Bit Depth = 4, Line = 12) RelPos 1 2 3 4 5 Bit Bit 1 Idle Bit 3 Bit 4 Bit 2 SF 1 1 — 11 8 1 SF 2 2 — 12 9 2 SF 3 3 — 1 10 3 SF 4 4 — 2 11 4 SF 5 5 — 3 12 5 SF 6 6 — 4 1 6 SF 7 7 — 5 2 7 SF 8 8 — 6 3 8 SF 9 9 — 7 4 9 SF 10 10 — 8 5 10 SF 11 11 — 9 6 11 SF 12 12 — 10 7 12

TABLE-US-00003 TABLE 3 Binary Section Length by BAG Scheme with Ideal Binary Sections (Bit Depth = 4, Line = 12) Time Length T.sub.SF + T.sub.DP Value Multi Binary sec 1 = T.sub.SF* 1 + T.sub.DP* − 1  = 4 1 Binary sec 2 = T.sub.SF* 2 + T.sub.DP* − 2  = 8 2 Binary sec 3 = T.sub.SF* 4 + T.sub.DP* − 4 = 16 4 Binary sec 4 = T.sub.SF* 8 + T.sub.DP* − 8 = 32 8 Sum = T.sub.SF* 15 + T.sub.DP* − 15 = 60 15

[0050] The waveforms for driving pixels in FIG. 6 show ideal binary sections, in which brightness relationship is correct for a display device with p rows. However, the main problem is that the available data driving time T.sub.DP is short and it is hard to complete the whole driving action. Also, in some cases, the ideal binary sections cannot use a duration of time in a most optimized way.

[0051] For further discussion, this BAG scheme is summarized with mathematical equations:

SF×CY=GSU×DSW_sum  (2)

[0052] DSW_sum means “data section weight sum” that is the sum of the weight of all data sections (binary sections). For example, if n=4, the sum of the weight of all binary sections is 1+2+4+8=15. All BAG solutions need to satisfy equation (2) and the following equation (3):

T.sub.FRAME=T.sub.DP×SF×CY  (3)

[0053] T.sub.DP is the time period for driving pixels of each line, because T.sub.FRAME is fixed once the frame rate is determined. CY depends on bit depth n. If T.sub.DP needs to be increased for driving, the number of SFs needs to be decreased. However, as can be seen from the example in FIG. 6, the number of SFs cannot be lower than the number of lines, because each line should be driven once in one frame. Therefore, the principle to find a BAG solution is to find the minimum GSU that satisfies equation (2) and following equation (4):

SF≥the number of lines  (4)

[0054] Using a large number of bits, it is assumed that bit depth n=12, and the number of lines=630. Then, CY should be n+1 which is 13 and DSW_sum is 1+2+4+ . . . +1024+2048=4095. According to equation (4), the minimum GSU should be 2 and the number of SFs becomes 2×4095/13=630, which satisfies SF≥the number of lines.

[0055] T.sub.DP can be derived from equations (2) and (3) as follows:

[00001]$\begin{array}{cc}{T}_{\mathrm{DP}}=\frac{T_{\mathrm{SF}}}{\mathrm{CY}}=\frac{T_{\mathrm{FRAME}}}{\mathrm{CY}\times \mathrm{SF\_number}}=\frac{T_{\mathrm{FRAME}}}{\mathrm{GSU}\times \mathrm{DSW\_sum}}& \left(5\right)\end{array}$

[0056] According to equation (5) with CY=13 and SF_number=630, T.sub.DP is calculated as (T.sub.FRAME/630/13)=(T.sub.FRAME/8190). Assuming that frame rate=60 Hz, T.sub.FRAME= 1/60 s. Then, T.sub.DP is 2.035 us. In some worse cases, it might be insufficient to drive pixels. Thus, it needs to find ways to provide a longer T.sub.DP and correct grey scales for each pixel.

[0057] In an example where a bit depth n=12, it is assumed that data for a certain pixel in a certain frame in the binary system is ‘1000_0011_1010’. In the BAG scheme, the waveform for the data for this pixel is as shown in FIG. 7.

[0058] This kind of basic BAG driving waveform is also called a pure digital driving. The feature of the pure digital driving is that data for driving a pixel is only ‘1’ and ‘0’ which are V.sub.CC and V.sub.SS, or V.sub.1 and V.sub.0 in the voltage domain. This kind of pure digital driving can drive each pixel in a correct grey scale, but as mentioned before, the available data driving time T.sub.DP may be not enough, and then cause a wrong display color. It needs to find ways to extend T.sub.DP and still keep each pixel in a correct grey scale at the same time.

[0059] The following describes a “Digital Analog Multiplication” driving sequence. This idea is a kind of digital and analog hybrid driving scheme. The total bit depth of pixel data is decomposed into two parts, digital bits and analog bits, and the product of the number of digital bits and the number of analog bits is the number of total bits.

[0060] In an example where the number of total bits n=12, in the conventional BAG scheme, the total grey scales have 2{circumflex over ( )}12 steps. All the 12 bits are digital bits. According to this idea, one solution is that the analog bits are set to 2 bits, and then the digital bits becomes 12/2 which is 6 bits. The product of 2 and 6 is 12. Therefore, this scheme is called a “Digital Analog Multiplication” driving scheme.

[0061] An embodiment of the present invention is described with reference to FIG. 8 to FIG. 10. FIG. 8 shows an example of a Digital Analog Multiplication driving sequence for a pixel in one frame with total bit depth n=12. This driving sequence for each pixel in one frame has only 6 time periods or 6 time sections, which is different from the pure digital driving which has 12 time periods or 12 time sections. The number of time periods is equal to the number of digital bits. Thus, the number of digital bits for a driving waveform in FIG. 8 is 6.

[0062] Each time section in FIG. 8 has 4 possible driving voltages, namely, 4 different steps in the voltage domain. The driving voltage of each time section is determined by the analog bits. In this case of 4 possible driving voltages, since 4 is 2{circumflex over ( )}2, the analog bits in this example of FIG. 8 is 2. The number of digital bits is 6, the number of analog bits is 2, and the number of total bits is 6×2=12.

[0063] It is assumed that data with total bit depth n=12 of a certain pixel in a certain frame is ‘1000_0011_1010’ that is the same as data in FIG. 7. In order to use the Digital Analog Multiplication driving, the pixel data needs to be converted from the binary system to another carry system.

[0064] First, the analog bits are set to 2 and the digital bits are set to 6 because 12/2=6. This means that there are 2{circumflex over ( )}2=4 possible driving voltages in each time section, and there are 6 time sections in total for each pixel in one frame. The time length relationship between time sections is 4 times. That is to say, if the time length of the LSB time section is 1T, then the time length of time sections are 1T, 4T, 16T, 64T, 256T, and 1024T.

[0065] Second, data is converted from the binary system to the 4th carry system, for example, binary data ‘1000_0011_1010’ becomes 4th carry data ‘20_0322’. The resulting waveform of the pixel is shown in FIG. 8. The relationship between V.sub.3, V.sub.2, V.sub.1, and V.sub.0 is output emission energy ratio or output luminance ratio that is driven by V.sub.3, V.sub.2, V.sub.1, and V.sub.0 and is 3×, 2×, 1×, and 0 (multiples of 3, 2, 1, and 0).

[0066] FIG. 9 shows luminance levels corresponding to voltage steps in each time section.

[0067] FIG. 10 shows several examples of pixel waveforms for different grey scales. The first waveform for data ‘2106’ is the same as that in FIG. 8, and it can be seen how this scheme works for 12 bit data: 2, 3, 4, 4094, and 4095, namely, how the waveforms change for data from 2 to 4, and how the waveforms change for data from 4094 to 4095. This scheme works correctly when the energy ratio or luminance ratio for driving satisfies that V.sub.3 is 3 times as high as V.sub.1, and V.sub.2 is twice as high as V.sub.1.

[0068] The following describes three embodiments of the present invention, and comparison with the pure digital driving waveform.

[0069] The first embodiment of the present invention refers to the same example as described above with reference to FIG. 8 to FIG. 10, and is compared with the pure digital driving waveform shown in FIG. 7. In this embodiment, the total bit depth n of the pixel data is 12.

[0070] FIG. 7 shows a pure digital driving waveform example of a pixel in one frame with total bit depth n=12. It has 12 time periods or 12 time sections in one frame The number of digital bits here is 12. The data “2106” in the decimal system is ‘1000_0011_1010’ in the binary system. So, there are 12 time sections in one frame.

(1) In the time domain, the time length of the first time section is 1T long, the second time section is 2T long, the third time section is 4T long, . . . , and the last time section is 2,048T long.
(2) In the voltage domain, the voltage level of the first time section is high or V.sub.1, the second time section is low or V.sub.0, the third time section is low or V.sub.0, the fourth time section is low or V.sub.0, . . . , and the last time section is low or V.sub.0.
(3) Checking the available data driving time T.sub.DP, there are 1T+2T+4T+ . . . +2,048T=4,095T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/4,095).

[0071] This waveform in FIG. 7 can drive pixel data ‘2106’.

[0072] FIG. 9 shows a luminance level reference of the Digital Analog Multiplication scheme where the number of analog bits is 2 and the number of digital bits is 6. The time length of each time section is 4 times as long as the previous time section. There are 4 voltage levels V.sub.3, V.sub.2, V.sub.1, and V.sub.0. The emission device turns OFF when driving at V.sub.0. The luminance of driving at V.sub.2 is as twice as that of driving at V.sub.1, and the luminance of driving at V.sub.3 is 3 times as high as that of driving at V.sub.1. And then a full map of luminance level reference in one frame is as shown in FIG. 10.

[0073] FIG. 10 shows the pixel waveforms of the Digital Analog Multiplication scheme where the number of analog bits is 2 and the number of digital bits is 6. For example, data “2106” in the decimal system is ‘1000_0011_1010’ in the binary system. The data needs to be converted into a 4.sup.th carry system, in which the data is ‘20_0322’, and then the waveform is as shown at the top of FIG. 10. The other waveforms are also shown in FIG. 10.

(1) In the time domain, the time length of the first time section is 1T long, the second time section is 4T long, the third time section is 16T long, . . . , and the last time section is 1,024T long.
(2) In the voltage domain, the voltage level of the first time section is V.sub.2, the second time section is V.sub.0, the third time section is V.sub.0, the fourth time section is V.sub.3, . . . , and the last time section is V.sub.2.
(3) Checking the available data driving time T.sub.DP, there are 1T+4T+16T++1,024T=4,095T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/1,365). In this embodiment, T.sub.DP is 3 times as long as that of the pure digital driving scheme.

[0074] Next, the second embodiment of the present invention is described with reference to FIG. 11 to FIG. 13. In this embodiment, the total bit depth n of the pixel data is 18.

[0075] FIG. 11 shows a pure digital driving waveform example of a pixel in one frame with total bit depth n=18. It has 18 time periods or 18 time sections in one frame. The number of digital bits here is 18. The data ‘63179’ in the decimal system is ‘0011_1101_1011_0010_11’ in the binary system. So, there are 18 time sections in one frame.

(1) In the time domain, the time length of the first time section is 1T long, the second time section is 2T long, the third time section is 4T long, and the last time section is 131,072T long.
(2) In the voltage domain, the voltage level of the first time section is low or V.sub.0, the second time section is low or V.sub.0, the third time section is high or V.sub.1, the fourth tome section is high or V.sub.1, . . . , and the last time section is high or V.sub.1.
(3) Checking the available data driving time T.sub.DP, there are 1T+2T+4T+ . . . +131,072T=262,143T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/262,143).

[0076] Then this waveform in FIG. 11 can display pixel data ‘63179’.

[0077] FIG. 12 shows a luminance level reference of the Digital Analog Multiplication scheme wherein the number of analog bits is 2 and the number of digital bits is 9. The time length of each time section is 4 times as long as that of the previous time section. There are 4 voltage levels V.sub.3, V.sub.2, V.sub.1, and V.sub.0. The emission device turns OFF when driving at V.sub.0. The luminance of driving at V.sub.2 is as twice as that of driving at V.sub.1, the luminance of driving at V.sub.3 is 3 times as high as that of driving at V.sub.1. And then a full map of luminance level reference in one frame is as shown in FIG. 12.

[0078] FIG. 13 shows the data waveform of the Digital Analog Multiplication scheme where the number of analog bits is 2 and the number of digital bits is 9. The data ‘63179’ in the decimal system is ‘0011_1101_1011_0010_11’ in the binary system. The data need to be converted into a 4.sup.th carry system in which the data is ‘0331_2302_3’, and then waveform is as shown at the top of FIG. 13. The other waveforms are also shown in FIG. 13.

(1) In the time domain, the time length of the first time section is 1T long, the second the section is 4T long, the third time section is 16T long, and the last time section is 65,536T long.
(2) In the voltage domain, the voltage level of the first time section is V.sub.0, the second time section is V.sub.3, the third time section is V.sub.3, the fourth time section is V.sub.1, . . . , and the last time section is V.sub.3.
(3) Checking the available data driving time T.sub.DP, there are 1T+4T+16T+ . . . +65,536T=87,381T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/87,381). In this embodiment, T.sub.DP is 3 times as long as that of the pure digital driving scheme.

[0079] Next, the third embodiment of the present invention is described with reference to FIG. 14 to FIG. 16. In this embodiment, the total bit depth n of the pixel data is 12.

[0080] FIG. 14 shows a pure digital driving waveform example of a pixel in one frame with total bit depth n=12. It has 12 time periods or 12 time sections in one frame. The number of digital bits here is 12. The data ‘2106’ in the decimal system is ‘1000_0011_1010’ in the binary system. So, there are 12 time sections in one frame.

(1) In the time domain, the time length of the first time section is 1T long, the second time section is 2T long, the third time section is 4T long, . . . , and the last time section is 2,048T long.
(2) In the voltage domain, the voltage level of the first time section is high or V1, the second time section is low or V0, the third time section is low or V0, the fourth time section is low or V0, . . . , and the last time section is low or V0.
(3) Checking the available data driving time T.sub.DP, there are 1T+2T+4T++2,048T=4,095T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/4,095).

[0081] This waveform in FIG. 14 can display pixel data ‘2106’.

[0082] FIG. 15 shows a luminance level reference of the Digital Analog Multiplication scheme where the number of analog bits is 3 and the number of digital bits is 4. The time length of each time section is 8 times as long as that of the previous time section. There are 8 voltage levels V.sub.7, V.sub.6, V.sub.5, V.sub.4, V.sub.3, V.sub.2, V.sub.1, and V.sub.0. The emission device turns OFF when driving at V.sub.0. The luminance of driving at V.sub.2 is as twice as that of driving at V.sub.1, the luminance of driving at V.sub.3 is 3 times as high as that of driving at V.sub.1, and the luminance of driving at V.sub.7 is 7 times as high as that of driving at V.sub.1. And then a full map of luminance level reference in one frame is as shown in FIG. 15.

[0083] FIG. 16 shows the data waveform of the Digital Analog Multiplication scheme where the number of analog bits is 3 and the number of digital bits is 4. The data ‘2106’ in the decimal system is ‘1000_0011_1010’ in the binary system. The data need to be converted into an 8.sup.th carry system, in which the data is ‘4072’, and then the waveform is as shown at the top of FIG. 16. The other waveforms are also shown in FIG. 16.

(1) In the time domain, the time length of the first time section is 1T long, the second time section is 8T long, the third time section is 64T long, . . . , and the last time section is 512T long.
(2) In the voltage domain, the voltage level of the first time section is V.sub.4, the second time section is V0, the third time section is V.sub.7, and the last time section is V.sub.2.
(3) Checking the available data driving time T.sub.DP, there are 1T+8T+64T+512T=585T in total in one frame, and therefore, T.sub.DP here is (T.sub.FRAME/585). In this embodiment, T.sub.DP is 7 times as long as that of the pure digital driving scheme.

[0084] In another embodiment, the order of time sections may be changed in any order.

[0085] In another embodiment, regarding the second time section to the last time section, each time section may be m times as long as the previous time section, the voltage levels may have m steps, and m is an integer greater than or equal to 3. In addition, the order of time sections may be changed in any order.

[0086] As application scenarios, the embodiments of the present invention can be mainly used for driving micro-LED display devices. Not only micro-LED displays but also any other display devices can be driven by PWM controls such as a display device with a bi-stable emission device. From a product point of view, the embodiments of the present invention can be used in any kind of display in consumer electronics, automotive, and industrial products.

[0087] For micro-LED displays having an array of pixels in which row*column is p*q, the Digital Analog Multiplication driving of the embodiments of the present application provides a driving sequence which is composed by both digital bits and analog bits. The product of the number of digital bits and the number of analog bits is equal to the total bit depth of the pixel data. The digital bits determine the number of time sections in one frame. The number of time sections is always larger or equal to the number of digital bits. The number of analog bits has a relationship with analog voltage steps.

[0088] According to the embodiments of the present invention, all of p*q pixels in an array of a display device can display correct grey scale colors and the available data driving time is arranged in an optimized way.

[0089] The effects and advantages by the embodiments of the present invention are as follows:

[0090] The most significant improvement of the embodiments of the present invention is that the available data driving time T.sub.DP is increased. The larger T.sub.DP makes it easier to drive each pixel with correct data or voltage. So, color performance of the micro-LED is improved.

[0091] Comparing with the BAG scheme which can be recognized as a pure digital driving scheme, according to equations (2) and (3) above, the T.sub.DP equation of the BAG scheme is:

[00002]$\begin{array}{cc}{T}_{\mathrm{DP}}=\frac{T_{\mathrm{SF}}}{\mathrm{CY}}=\frac{T_{\mathrm{FRAME}}}{\mathrm{CY}\times \mathrm{SF\_number}}=\frac{T_{\mathrm{FRAME}}}{\mathrm{GSU}\times \mathrm{DSW\_sum}}& \left(5\right)\end{array}$

[0092] Equation (5) can also be used to calculate T.sub.DP for the Digital Analog Multiplication driving scheme.

[0093] In the case where the total data bit depth is 12 and the number of lines is 960, for the BAG scheme driving sequence with pure digital bits, all the 12 bits are digital bits. Then, the series of data section weights is 1, 2, 4, 8, . . . , 2048 and DSW_sum is 4095. CY is 13 and GSU is chosen to be 4 to get a minimum SF number so that 4095*4/13=1,260 according to CY×SF_number=GSU×DSW_sum that is devived from equation (5). 1,260 is the minimum SF number greater than or equal to 960 in the BAG scheme with the pure digital bit solutions. Thus, for frame rate is 60 Hz, T.sub.DP is 1/60/13/1260=1.018 us according to T.sub.DP=T.sub.FRAME/(CY×SF_number) in equation (5), as shown in the left column in TABLE 4 below.

[0094] In the case where the total data bit depth is 12 and the number of lines is 960, for the driving sequence with the Digital Analog Multiplication scheme, the number of digital bits is chosen to be 6 and the number of analog bits is chosen to be 2. Then, the series of data section weights are 1, 4, 16, 64, . . . , 1024 and DSW_sum is 1365. CY is 7 and GSU is chosen to be 5 so that 1365*5/7=975. 975 is the minimum SF number greater than or equal to 960 in the driving sequence with solution that the number of digital bits is 6 and the number of analog bits is 2 of the Digital Analog Multiplication scheme. Thus, for a frame rate of 60 Hz, T.sub.DP is 1/60/7/975=2.442 us. This is 2.4 times as long as that of the pure digital bit scheme, as shown in the middle column in TABLE 4 below.

[0095] In the case where the total data bit depth is 12 and the number of lines is 960, for the driving sequence with the Digital Analog Multiplication scheme, the number of digital bits is chosen to be 4 and the number of analog bits is chosen to be 3. Then, the series of data section weights are 1, 8, 64, 512 and DSW_sum is 585. CY is 5 and GSU is chosen to be 9 so that 585*9/5=1,053. 1,053 is the minimum SF number greater than or equal to 960 in the driving sequence with the solution that the number of digital bits is 4 and the number of analog bits is 3 of the Digital Analog Multiplication scheme. Thus, for a frame rate of 60 Hz, T.sub.DP is 1/60/5/1053=3.166 us. This is 3.1 times as long as that of the pure digital bit scheme, as shown in the right column in TABLE 4 below.

[0096] TABLE 4 is a summary of comparison between the above cases including the BAG scheme and the Digital Analog Multiplication driving scheme. The CY can be downscaled and then get a larger available data driving time in the driving sequence. For different display resolutions, there are a different number of lines. The improvement percentage of T.sub.DP is different case by case.

TABLE-US-00004 TABLE 4 T.sub.DP Improvement by the Digital Analog Multiplication scheme (Total Bit Depth = 12) Driving Scheme Pure Digital Digital × Analog Digital × Analog Type Prior Art, BAG Embodiment Embodiment Total Data Bit Depth 12 12 12 Digital Bits 12 6 4 Analog Bits — 2 3 Number of Lines — 960 960 960 Number of Cycles CY 13 7 5 Number of Sub-fields SF_Num 1260 975 1053 Grey Scale Unit GSU 4 5 9 Data Section Weight Sum DSW_Sum 4,095 1,365 585 Frame Rate (Hz) 60 60 60 T.sub.SF (us) 13.228 17.094 15.8278 T.sub.DP (us) 1.018 2.442 3.166 ΔT.sub.DP % — 0% 140% 211%

[0097] FIG. 17 and FIG. 18 show the summary of different displays with the number of lines from 800 to 2,600. The x-axis denotes the number of lines of displays and y-axis denotes available data driving time T.sub.DP. We can observe the solutions of the Digital Analog Multiplication driving scheme can provide longer T.sub.DP for driving each pixel on a display device. For the number of lines, the difference in the vertical direction in FIG. 17 and FIG. 18 indicates the T.sub.DP improvement by the Digital Analog Multiplication scheme from the conventional driving scheme. The timing improvement of the embodiments of the present invention is about from 80% to 16%, depending on the number of lines of displays.

[0098] The embodiments of the present invention can be applied to not only micro-LED displays, but also display devices with other materials using PWM control, digital driving, or analog and digital combined driving.

[0099] What is disclosed above is merely exemplary embodiments of the present invention, and certainly is not intended to limit the protection scope of the present invention. A person of ordinary skill in the art may understand that all or some of processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.