Generation of high-rate sinusoidal sequences

Abstract

Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.

Claims

1. An apparatus for generating discrete-time samples of a sinusoidal waveform, comprising: a system output for providing output samples of a sinusoid, said output samples being discrete in time and in value and collectively representing the sinusoid at a desired full sampling rate; a plurality of processing branches coupled to the system output, each of said processing branches including a recursive digital filter that operates at a subsampled rate, relative to the desired full sampling rate, and comprises: (a) a multiplier having a first input, a second input, and an output; (b) an adder having a first input, a second input, and an output; and (c) first and second writeable delay registers, each having an input and an output, with the first input of said adder coupled to the output of said adder through the first writable delay register and through the multiplier, and thereby delayed in time by exactly one processing cycle at the subsampled rate, and with the second input of said adder coupled to the output of said adder through both the first and second writeable delay registers, and thereby delayed in time by exactly two processing cycles at the subsampled rate; a first input line, for setting a frequency of the sinusoid, coupled to an input of said multiplier; and a second input line, coupled to the input of at least one of said first and second writeable delay registers and providing an initial state for the recursive digital filter, in at least one of said processing branches, wherein each of said processing branches operates at the subsampled rate and generates an output sequence at said subsampled rate that represents a different subsampling phase of the sinusoid at the desired full sampling rate, wherein said recursive digital filter within each said processing branch operates independently of the recursive digital filter within the other processing branches, and produces subsampled outputs via a linear combination of exactly two prior output samples generated within said processing branch, wherein the transfer function of the recursive digital filter in at least one of said processing branches represents a recursive form of angle sum and difference formulas for trigonometric functions, and wherein a value provided on said first input line is set based on cos(m.Math.ω.Math.T.sub.S), where m is a total number of said processing branches, ω=2πf is the frequency of said sinusoid in radians/second, and T.sub.S is the sampling period in seconds of said sinusoid at the desired full sampling rate.

2. An apparatus according to claim 1, further comprising a multiplexer with inputs that are coupled to outputs of said parallel processing branches and which combines multiple, sub-rate inputs into a single, full-rate output.

3. An apparatus according to claim 1, wherein the subsampling phase at the output of each of the processing branches is determined by an initial state of the recursive digital filter and is established by a value written to said first and second writeable delay registers within said processing branch once upon configuration.

4. An apparatus for generating discrete-time samples of a sinusoidal waveform, comprising: a system output for providing output samples of a sinusoid, said output samples being discrete in time and in value and collectively representing the sinusoid at a desired full sampling rate; a plurality of processing branches coupled to the system output, each of said processing branches operating at a subsampled rate, relative to the desired full sampling rate, including a sine lookup table, and also including a phase accumulator which comprises: (a) an adder having a first input, a second input, and an output; and (b) a writeable register having an input and an output, with the first input of said adder coupled to an input line that provides a value for establishing, in conjunction with said subsampling rate, a desired frequency of said sinusoid, with the second input of said adder coupled to the output of said adder through said writeable register, and with the output of said writeable register coupled to said sine lookup table, wherein each of said processing branches operates at the subsampled rate and generates an output sequence at said subsampled rate that represents a different subsampling phase of the sinusoid at the desired full sampling rate, wherein said phase accumulator within each said processing branch operates independently of the phase accumulator within the other processing branches, and wherein the writeable register within at least one of said phase accumulators also includes two additional inputs, a write-enable input and a data input which are used to establish the subsampling phase of the processing branch to which said at least one of said phase accumulators belongs.

5. An apparatus according to claim 4, further comprising a multiplexer with inputs that are coupled to outputs of said parallel processing branches and which combines multiple, sub-rate inputs into a single, full-rate output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following disclosure, the invention is described with reference to the attached drawings. However, it should be understood that the drawings merely depict certain representative and/or exemplary embodiments and features of the present invention and are not intended to limit the scope of the invention in any manner. The following is a brief description of each of the attached drawings.

(2) FIG. 1 is a block diagram of a conventional discrete-time oscillator which utilizes a digital phase accumulator and a sine lookup table to generate a sinusoidal output sequence.

(3) FIG. 2 is a block diagram of a conventional discrete-time oscillator which utilizes an adder, a multiplier, and delay registers to generate current sinusoidal output samples from prior sinusoidal output samples, in accordance with a single trigonometric recursion formula.

(4) FIG. 3A is a block diagram of a conventional discrete-time oscillator which utilizes adders, multipliers, and registers to generate current quadrature sinusoidal outputs based on prior quadrature outputs, in accordance with a pair of trigonometric recursion formulas; FIG. 3B is a block diagram of a conventional discrete-time oscillator which uses a recursive structure comprising adders, multipliers, and registers to generate sinusoidal output samples having two distinct frequency components; and FIG. 3C is a block diagram of a conventional discrete-time oscillator which uses a recursive structure comprising adders, multipliers, and registers to generate sinusoidal output samples that are frequency modulated.

(5) FIG. 4 is a block diagram of a discrete-time oscillator which uses conventional polyphase decomposition to realize an effective sampling rate which is twice as high as the operating rate of its constituent circuitry, but which results in recursive structures that are not independent and are unstable.

(6) FIG. 5A is a block diagram of an exemplary implementation of a discrete-time oscillator which uses an output multiplexer, and two parallel processing branches with recursive filters and writable registers, to realize an effective sampling rate which is twice as high as the operating rate of a processing branch; and FIG. 5B is a block diagram of an exemplary implementation of a discrete-time oscillator which uses an output multiplexer, and a number m of parallel processing branches with recursive filters and writable registers, to realize an effective sampling rate which is m-times greater than the operating rate of a processing branch.

(7) FIG. 6A is a block diagram of an exemplary implementation of a discrete-time oscillator which uses an output multiplexer, and two parallel processing branches with writable accumulators and a sine lookup tables, to realize an effective sampling rate which is twice as high as the operating rate of a processing branch; and FIG. 6B is a block diagram of an exemplary implementation of a discrete-time oscillator which uses an output multiplexer, and two parallel processing branches with phase-offset adders and sine lookup tables, to realize an effective sampling rate which is twice as high as the operating rate of a processing branch.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

(8) The present inventor recognized that the sampling rate of the sinusoidal sequences produced by conventional means is limited by the maximum operating rates (i.e., the maximum clocking frequency) of the circuit components which comprise the generating apparatus. One might contemplate a solution to this problem based on conventional polyphase decomposition methods to arrive at circuit 50, illustrated in FIG. 4, for a polyphase decomposition factor of m=2. According to conventional polyphase decomposition methods, the processing for circuit 50 is derived by iterating the recursion relation for the direct-form recursive oscillator (i.e., two iterations for a polyphase decomposition factor of m=2), to obtain
x.sub.2n=(4.Math.cos.sup.2(θ)−1).Math.x.sub.2n−2−2.Math.cos(θ).Math.x.sub.2n−3 and
x.sub.2n+1=(4.Math.cos.sup.2(θ)−1).Math.x.sub.2n−1−2.Math.cos(θ).Math.x.sub.2n−2,
such that a pair of current outputs (e.g., x.sub.2n and x.sub.2n+1) are simultaneously calculated from previous outputs which have been delayed by at least two sampling clock periods. It should be noted that conventional polyphase decomposition results in an oscillator structure having multiple parallel processing branches (e.g., a first processing branch to produce output x.sub.2n and a second processing branch to produce output x.sub.2n+1) which do not operate independently, since the current output of one processing branch depends on delayed outputs from other processing branches (e.g., current output x.sub.2n of a first processing branch depends on delayed output x.sub.2n−3 from a second processing branch). The present inventor has discovered, however, that the resulting recursive filter structures are unstable, and that the number of bits required to represent the filter coefficients grows geometrically with polyphase decomposition factor m (i.e., grows geometrically with the number of iterations on the recursion relation for the direct-form recursive oscillator). Although modern digital signal processors use methods, such as parallel processing, to overcome limitations in the clocking rates of constituent components, these methods have not been adapted for use in discrete-time oscillators. Therefore, the present invention provides novel architectures that allow sinusoidal sequences to be generated at effective sampling rates which are higher than the maximum clocking rates of the constituent components.

(9) A discrete-time oscillator circuit 100 that uses parallel processing branches to generate sinusoidal sequences with an effective sampling rate, f.sub.S, that is higher than the operating rate of each parallel branch, is shown in FIG. 5A. Referring to the exemplary embodiment illustrated in FIG. 5A, circuit 100 incorporates m=2 parallel processing branches (e.g., branches 110 and 120), with each branch containing a recursive digital filter comprised of an adder (e.g., adder 17A or 17B), a multiplier (e.g., multiplier 16A or 16B), and writable registers (e.g., registers 15A&B or 15C&D). Each of registers 15A-D introduces a delay τ equal to two full-rate periods (i.e., τ=2.Math.T.sub.S=2/f.sub.S), and each register is preferably implemented as a single-stage register clocked at half-rate of ½.Math.f.sub.S, rather than as a two-stage register clocked at full-rate of f.sub.S. Regardless of register implementation, however, the multiply-accumulate function performed by adder 17A or 17B with multiplier 16A or 16B, respectively, occurs at one-half rate. The recursive digital filter in each processing branch 110 or 120, implements the difference equation:
y.sub.n=2.Math.cos(2.Math.ω.Math.T.sub.S).Math.y.sub.n−2−y.sub.n−4,
with corresponding discrete-time transfer function,

(10) $H\left(z\right)=\frac{1}{1-2.Math.\cos \left(2.Math.\omega .Math.T_S\right).Math.z^{-2}+z^{-4}},$
where the z-transform variable z represents a unit delay of one full-rate period T.sub.S. The present inventor has discovered that a discrete-time oscillator that implements the above difference equation and corresponding transfer function, generates an output sequence which is subsampled by a factor of two, such that the output sequence represents every other value of a sampled sine wave with frequency f=ω/2π (i.e., the output sequence represents subsamples of a full-rate sinusoidal sequence). In the preferred embodiments, the frequency of the sampled sine wave is controlled by programming the filter coefficient represented by the 2.Math.cos (2.Math.ω.Math.T.sub.S) term in the above difference equation. At a clocking rate of f.sub.S, each subsample occurs twice (i.e., each output sample is replicated two times), and at a clocking rate of ½.Math.f.sub.S, each subsample occurs only once (i.e., output subsamples are not replicated). In the preferred embodiments, therefore, the clocking rate of each processing branch is ½.Math.f.sub.S, when the number of processing branches m is equal to two, and each subsample appears only once at the output of the recursive filter within each of the processing branches. The inventor has also discovered that the phase of the subsampled output sequence (i.e., the offset with which the full-rate sequence is effectively subsampled) depends on the initial condition of the recursive filter in each processing branch. For an initial condition of
y.sub.n−2(t.sub.0)=cos(2.Math.ω.Math.T.sub.S) and y.sub.n−4(t.sub.0)=cos(4.Math.ω.Math.T.sub.S),
the phase φ of the subsampled output sequence is zero (i.e., subsampling begins with the first full-rate sample), and for an initial condition of
y.sub.n−2(t.sub.0)=cos(ω.Math.T.sub.S) and y.sub.n−4(t.sub.0)=cos(3.Math.ω.Math.T.sub.S),
the phase φ of the subsampled output sequence is one (i.e., subsampling begins with the second full rate sample). For this reason, in the preferred embodiments the initial conditions (i.e., the initial state) of the recursive filter in each of the processing branches are established, so that in combination, the subsampled sequences produced by the various processing branches provide all the samples of a complete, full-rate sequence. In the exemplary embodiment of circuit 100, in FIG. 5A, such an initial filter state is provided by writable filter registers 15A-D, having both write enable (e.g., WE) and data (e.g., D0a, D1a, D0b, and D1b) inputs.

(11) In the exemplary embodiment of circuit 100, the subsampled outputs of the recursive digital filter within each processing branch (e.g., output 111 of branch 110 and output 121 of branch 120) are combined into a full-rate sequence (i.e., at output 3C) using 2:1 multiplexer 18A. Multiplexer 18A has two inputs that operate at a subsampling rate of ½.Math.f.sub.S, and a single output that operates at the full sampling rate of f.sub.S. The operation of multiplexer 18A is such that samples at the multiplexer input appear in sequential order at the multiplexer output. Referring to circuit 100 in FIG. 5A, the subsampled output of the first processing branch (i.e., output 111 of branch 110) is given by
x.sub.2n=x.sub.0, x.sub.2, x.sub.4, x.sub.6, x.sub.8, . . .
and the subsampled output of the second processing branch (i.e., output 121 of branch 120) is given by
x.sub.2n+1=x.sub.1, x.sub.3, x.sub.5, x.sub.7, x.sub.9, . . .
Consequently, the full-rate output (i.e., output 3C) of multiplexer 18A is given by
x.sub.n=x.sub.0, x.sub.1, x.sub.2, x.sub.3, x.sub.4, x.sub.5, x.sub.6, x.sub.7, x.sub.8, x.sub.9, . . .
In alternate embodiments, such as those where, for postprocessing purposes, multiple sub-rate outputs are preferable to a single full-rate output, the multiplexer operation is absent.

(12) More generally, a discrete-time oscillator circuit according to the preferred embodiments of the invention has m parallel processing branches, as illustrated by circuit 200 in FIG. 5B. The recursive digital filter in each of the processing branches (e.g., branches 110 through 130, implements the difference equation:
y.sub.n=2.Math.cos(m.Math.ω.Math.T.sub.S).Math.y.sub.n−m−y.sub.n−2m,
with corresponding discrete-time transfer function,

(13) $H\left(z\right)=\frac{1}{1-2.Math.\cos \left(m.Math.\omega .Math.T_S\right).Math.z^{-m}+z^{-2m}},$
where, as before, the z-transform variable z represents a unit delay of one full-rate period T.sub.S. A discrete-time oscillator that implements the above difference equation and corresponding transfer function, generates an output sequence which is subsampled by a factor of m, such that in the preferred embodiments, the clocking rate of each processing branch is 1/m.Math.f.sub.S and each subsample appears only once at the output of the recursive filter within each of the processing branches. The phase φε{0, 1, 2, . . . , m −1} of the subsampled output sequence (i.e., the offset with which the full-rate sequence is effectively subsampled) depends on the initial state (i.e., the initial register values) of the recursive filter in each processing branch, according to
y.sub.n−2m(t.sub.0)=cos((m−φ).Math.ω.Math.T.sub.S) and y.sub.n−4m(t.sub.0)=cos((2m−φ).Math.ω.Math.T.sub.S).
Therefore, the initial state of the recursive filter in each of the processing branches is established (e.g., using writeable filter registers as shown in FIG. 5B), so that in combination, the subsampled sequences produced by the m processing branches provide all the samples of a complete, full-rate sequence. In addition, in the preferred embodiments the frequency of the output sequence is controlled, e.g., by setting the filter coefficient represented by the 2.Math.cos(m.Math.ω.Math.T.sub.S) term in the above difference equation as shown in FIG. 5B. Also, in the exemplary embodiment of circuit 200, the subsampled outputs of the recursive digital filter within each of the m processing branches are combined into a full-rate sequence (i.e., at output 3D) using m:1 multiplexer 18B. In alternate embodiments, however, the multiplexer operation is absent and postprocessing takes place on multiple sub-rate outputs. If present, multiplexer 18B has m inputs that operate at a subsampling rate of 1/m.Math.f.sub.S, and a single output that operates at the full sampling rate of f.sub.S. The operation of multiplexer 18B is such that samples at the multiplexer input appear in sequential order at the multiplexer output.

(14) Although in the preferred embodiments, the parallel processing branches contain recursive digital filters, in alternate embodiments, the parallel processing branches use other approaches to generate a set of subsampled sinusoidal sequences that can be combined to form a full-rate sinusoidal sequence. Exemplary discrete-time oscillator circuits 300A&B, shown in FIGS. 6A&B, generate subsampled sinusoidal sequences using parallel processing branches that contain phase accumulators and sine lookup tables. Referring to the exemplary embodiment illustrated in FIG. 6A, circuit 300A incorporates m=2 parallel processing branches (e.g., branches 115 and 125), with each branch containing a phase accumulator comprised of an adder (e.g., adder 27A or 27B) and a writable register (e.g., register 25A or 25B). Each of registers 25A&B introduces a delay i equal to two full-rate periods (i.e., τ=2.Math.T.sub.S=2/f.sub.S), and each register is preferably implemented as a single-stage register clocked at a half-rate of ½.Math.f.sub.S, rather than as a two-stage register clocked at a full-rate of f.sub.S. Regardless of register implementation, however, the phase accumulation function performed by adder 27A or 27B with register 25A or 25B, occurs at one-half rate. Therefore, the phase accumulator in each processing branch 115 or 125 implements the difference equation:
φ.sub.n=2.Math.θ+φ.sub.n−2,
with corresponding discrete-time transfer function,

(15) $H\left(z\right)=\frac{2}{1-z^{-2}},$
where the z-transform variable z represents a unit delay of one full-rate period T.sub.S. The present inventor has discovered that a discrete-time oscillator that implements the above difference equation and corresponding transfer function, accumulates phase at a rate of 2.Math.θ.Math.(½.Math.f.sub.S). And at a clocking rate of ½.Math.f.sub.S, the discrete-time oscillator generates an output sequence representing every other value of a sampled sine wave with frequency f=θ/2π.Math.f.sub.S (i.e., the output sequence represents subsampling, without replication, by a factor of 2 on a full-rate sequence). In the preferred embodiments, therefore, the clocking rate of each processing branch is ½.Math.f.sub.S, when the number of processing branches m is equal to two, and is more generally equal to 1/m.Math.f.sub.S for subsampling by a factor of m. In addition, in the preferred embodiments the frequency of the output sequence is controlled by setting the phase-step value θ that appears in the above difference equation, e.g., as shown in FIG. 6A.

(16) In addition, the inventor has discovered that the phase of the subsampled output sequence (i.e., the offset with which the full-rate sequence is subsampled) depends on the initial condition of the phase accumulator within each processing branch. For an initial condition of
φ.sub.n−2(t.sub.0)=0,
the phase φ of the subsampled output sequence is zero (i.e., subsampling begins with the first full-rate sample), and for an initial condition of
φ.sub.n−2(t.sub.0)=1,
the phase φ of the subsampled output sequence is one (i.e., subsampling begins with the second full rate sample). In general, the initial condition of the phase accumulation preferably is
φ.sub.n−2(t.sub.0)=φ,
for a subsampling phase equal to φ. In the preferred embodiments, the subsampling phase of each processing branch is established so that, in combination, the subsampled sequences produced by the different processing branches collectively provide all the samples of a complete, full-rate sequence. In exemplary circuit 300A, a phase accumulator with writeable registers (e.g., a registers 25A&D having both write enable and data inputs) is used to establish the subsampling phase of each processing branch. In the alternative embodiment of circuit 300B, shown in FIG. 6B, the subsampling phase is established using an adder (e.g., adder 24A or 24B), which couples the output of the phase accumulator (e.g., the output of register 26A or 26B, respectively) to the sine lookup table (e.g., lookup table 29A or 29B, respectively), and offsets the accumulator output by an amount equal to φ. In the exemplary embodiments of circuits 300A&B, the subsampled outputs of the parallel processing branches are combined into a full-rate sequence (i.e., at output 3E or 3F) using 2:1 multiplexer 18A. In alternate embodiments, however, the multiplexer operation is absent and postprocessing takes place on multiple sub-rate outputs.
Additional Considerations.

(17) As used herein, the term “coupled”, or any other form of the word, is intended to mean either directly connected or connected through one or more other elements or processing blocks.

(18) Several different embodiments of the present invention are described above, with each such embodiment described as including certain features. However, it is intended that the features described in connection with the discussion of any single embodiment are not limited to that embodiment but may be included and/or arranged in various combinations in any of the other embodiments as well, as will be understood by those skilled in the art.

(19) Similarly, in the discussion above, functionality sometimes is ascribed to a particular module or component. However, functionality generally may be redistributed as desired among any different modules or components, in some cases completely obviating the need for a particular component or module and/or requiring the addition of new components or modules. The precise distribution of functionality preferably is made according to known engineering tradeoffs, with reference to the specific embodiment of the invention, as will be understood by those skilled in the art.

(20) Thus, although the present invention has been described in detail with regard to the exemplary embodiments thereof and accompanying drawings, it should be apparent to those skilled in the art that various adaptations and modifications of the present invention may be accomplished without departing from the spirit and the scope of the invention. Accordingly, the invention is not limited to the precise embodiments shown in the drawings and described above. Rather, it is intended that all such variations not departing from the spirit of the invention be considered as within the scope thereof as limited solely by the claims appended hereto.