Direct synthesis of receiver clock

Abstract

The Direct Synthesis of a Receiver Clock (DSRC) contributes a method, system and apparatus for reliable and inexpensive synthesis of inherently stable local clock synchronized to a referencing signal received from an external source. Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver. Such DSRC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI or Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.

Claims

1. A method for direct synthesis of a receiver clock (DSRC) using a clock of a free running oscillator for synthesizing the receiver clock tracking phase of a referencing signal, wherein the DSRC method utilizes predictable phase amendments and remaining phase amendments needed for compensating parts of phase errors remaining after synthesizing previous frames of the receiver clock, for amending phases of current frames of the receiver clock in order to synthesize the receiver clock; wherein the DSRC method comprises the steps of: measuring phase errors of frames of the free running oscillator clock related to frames of the referencing signal, deriving the predictable phase amendments by processing the measured phase errors of the frames of the free running oscillator clock; deriving the remaining phase amendments by utilizing the measured phase errors of the frames of the free running oscillator clock and previous said predictable phase amendments; applying, using a phase synthesizer, a current one of said predictable phase amendments and a current one of said remaining phase amendments to a current one of said frames of the free running oscillator clock, in order to synthesize the receiver clock which is tracking phase of the referencing signal.

2. The DSRC method as claimed in claim 1 wherein the deriving the predictable phase amendments is implemented by utilizing a moving average filter or a weighted moving average filter for the processing the measured phase errors of the frames of the free running oscillator clock.

3. The DSRC method as claimed in claim 1; wherein the DSRC method further comprises the steps of: measuring phase errors of frames of the receiver clock related to the referencing signal frames; using the measured phase errors of the receiver clock frames for periodical standby verifications enabling detection of a disruption of the tracking phase of the referencing signal caused by a hardware malfunction or unpredictable frequency or phase perturbations; recovering the tracking phase of the referencing signal, by reconstructing or restarting the steps of claim 1, when the disruption is detected.

4. The DSRC method as claimed in claim 1; wherein the DSRC method comprises the additional steps of: calculating a previous one of accumulated phase tracking errors between the receiver clock and the referencing signal, by adding a penultimate one of said accumulated phase tracking errors and a previous one of said measured phase errors of the frames of the free running oscillator clock and by subtracting a previous one of said predicted phase amendments and a previous one of said remaining phase amendments; deriving the current remaining phase amendment based on the previous accumulated phase tracking error; wherein the accumulated phase tracking errors and the remaining phase amendments are utilized for implementing gradual distributions of phase amendments applied to the receiver clock.

5. The DSRC method as claimed in claim 1, further including a presetting of a start-up phase offset of the receiver clock related to the referencing signal; wherein the DSRC method comprises the initial steps of: validating the referencing signal, controlled by a programmable control unit (PCU); initializing the phase offset of the receiver clock when a valid said referencing signal is detected, by presetting, using the PCU, a phase modification register in the phase synthesizer.

6. A method of direct frequency locking phase synthesis (DFLPS) for synthesizing a receiver clock synchronous to a referencing signal by applying predicted phase amendments and remaining phase amendments to the receiver clock synthesized with a phase synthesizer (PS) from an oscillator clock, wherein the predicted phase amendments are designed to prevent frequency errors of the receiver clock caused by a frequency difference or misalignment or drift between the referencing signal and the oscillator clock and the remaining phase amendments are designed to remove parts of phase errors of the receiver clock uncompensated by the predicted amendments; wherein the DFLPS method comprises the steps of: measuring phase errors of frames of the oscillator clock related to frames of the referencing signal; deriving the predicted phase amendments by processing the measured phase errors of the oscillator clock frames; deriving, using a programmable control unit (PCU), the remaining phase amendments by utilizing the measured phase errors of the oscillator clock frames and the predicted phase amendments; direct locking of a frequency of the receiver clock to a frequency of the referencing signal in a feed-forward configuration, by applying the predicted phase amendments to the receiver clock by utilizing the PS; synchronizing a phase of the receiver clock to a phase of the referencing signal, by applying the remaining phase amendments to the receiver clock by utilizing the PS.

7. The DFLPS method as claimed in claim 6 wherein the deriving the predicted phase amendments is implemented by using a moving average filter or a weighted moving average filter for the processing the measured phase errors of the oscillator clock frames.

8. The DFLPS method as claimed in claim 6; wherein the DFLPS method further comprises the steps of: measuring phase errors of frames of the receiver clock related to the referencing signal frames; using the measured phase errors of the receiver clock frames for periodical standby verifications enabling detection of a disruption of the synchronizing the phase of the receiver clock caused by a hardware malfunction or unpredictable frequency or phase perturbations; recovering the synchronizing the phase of the receiver clock, by reconstructing or restarting the steps of claim 6, when the disruption is detected.

9. The DFLPS method as claimed in claim 6; wherein the DFLPS method comprises the additional steps of: calculating a previous one of accumulated phase tracking errors between the receiver clock and the referencing signal, by adding a penultimate one of said accumulated phase tracking errors and a previous one of said measured phase errors of the oscillator clock frames and by subtracting a previous one of said predicted phase amendments and a previous one of said remaining phase amendments; deriving a current one of said remaining phase amendments based on the previous accumulated phase tracking error; wherein the accumulated phase tracking errors and the remaining phase amendments are utilized for implementing gradual distributions of phase amendments applied to the receiver clock.

10. The DFLPS method as claimed in claim 6 further including a presetting of a start-up phase offset of the receiver clock versus the referencing signal; wherein the DFLPS method comprises the initial steps of: validating the referencing signal, controlled by the programmable control unit (PCU); initializing the phase offset of the receiver clock when a valid said referencing signal is detected, by presetting, using the PCU, a phase modification register in the phase synthesizer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) General conventions making drawings easier to follow are explained below. Interconnect signals between interrelated drawings have unique names identifying their sources and destinations explained in the DESCRIPTION OF EMBODIMENTS utilizing the same names. Inputs supplied from different drawings are connected at the top or left side and outputs are generated on the bottom, due to the top-down or left-right data flow observed generally. Clocked circuits like registers or flip-flops are drawn with two times thicker lines than combinatorial circuits like arithmometers or selectors.

(2) FIG. 1 Shows an Open Ended Configuration of Software Controlled Clock Synchronizer.

(3) FIG. 2 Shows Open Ended Configuration of SCCS with External Synchronization Mode

(4) FIG. 3 Shows Heterodyne Timing Configuration of SCCS enabling acceptance of a very wide range of referencing clock frequencies.

(5) FIG. 4 Shows Sequential Clocks Generator (SCG) and Output Selection Circuits (OSC) enabling high resolution selections of mutually overlapping sub-clocks.

(6) FIG. 4A Shows Sequential Clocks Generator (SCG) and Return Selection Circuits (RSC), lowering output clock jitter

(7) FIG. 5 Shows Timing Control (TC) and Clocks Equalization (CE), which control timing of high frequency switching of synthesized clock

(8) FIG. 6 Shows Synchronous Sequential Phase Processor (SSPP), which performs programmable high-speed phase synthesis.

(9) FIG. 7 Shows Timing Diagram of Phase Synthesizer.

(10) FIG. 8 Shows Wave Capturing including Edge Regions (WCER), which enable continues capturing of a an oversampled high frequency waveform.

(11) FIG. 9 Shows Sequential Clocks Generation for the NFED(SCG NFED), which provides mutually overlapping sub-clocks enabling high accuracy detection of noisy signal edges.

(12) FIG. 10 Shows Noise Filtering Edge Detectors (NFED)

(13) FIG. 11 Shows Wave Form Screening & Capturing (WFSC), which enables analysis of incoming noisy waveform facilitating adaptive noise filtering

(14) FIG. 12 Shows Timing Diagrams of the WFSC.

(15) FIG. 13 Shows a block diagram of Inherently Stable Synchronization System.

(16) Notes referring to FIG. 13 and its timing diagrams, are provided below: Boundary detection delay (Tbd) determines predictable part of referencing frame delay to OFDM composite frame. Frequency offset (Fos) is not affected by the boundary detection delays Tbd for as long as Tbd remains constant. In order to make up for the boundary detection delay, Phase Synthesizer (PS) positions Local Symbol Frame forward in time compared to Referencing Frame. Frequency offset Fos derived using counted number of sampling clocks (Fcnt) and the nominal number (Fnom), can be measured with over 10× greater accuracy if it is measured over a reference frame interval over 10× longer.

(17) FIG. 14 Shows a block diagram of Synchronization System with Improved Stability.

(18) Notes referring to FIG. 14 and its timing diagrams, are provided below: Boundary detection delay (Tbd) determines predictable part of referencing frame delay to OFDM composite frame. Frequency offset (Fos) is not affected by the boundary detection delays Tbd for as long as Tbd remains constant. Time error (Terr) between local symbol frame and composite frame, amounts to boundary detection delay added to the phase error between reference frame and local symbol frame i.e. Ter=Tbd+(Trf−Is).

(19) FIG. 15 Shows an Inherently Stable Frequency Locked Phase Synthesis system.

(20) FIG. 16 Shows a similar FLPS system with its Frequency Detector utilizing local XTAL clock.

(21) FIG. 17 Shows a similar FLPS with Improved Stability.

(22) FIG. 18 Shows a similar FLPS but enabling more accurate generation of a synchronized clock.

(23) FIG. 19A Shows the configuration of circuits implementing Direct Frequency Locked Phase Synthesis

(24) FIG. 19B Shows the timing for this configuration for Direct Frequency Locked Phase Synthesis.

(25) FIG. 19C Shows the configuration for Direct Synthesis of Receiver Clock including a second FDP for measurements of the phase tracking error between the synthesized clock and referencing frame.

DESCRIPTION OF EMBODIMENTS

(26) 1. Phase Synthesizer

(27) The above mentioned first PS implementation is selected for the preferred embodiment, and it is shown in the FIG. 4, FIG. 5, FIG. 6 and FIG. 7.

(28) The PS comprises wave timing definition, which includes two major components downloaded to the PS from the PCU:

(29) basic less frequently changed phase adjustments, which can include both periodical adjustments and fractional adjustments, define more stable components of wave-form phase;

(30) high frequency phase modulations, which can include both the periodical adjustments and the fractional adjustments, allow every leading edge phase and/or every falling edge phase to be modulated with a different modulation factor.

(31) Said phase modulations are downloaded to the PS simultaneously in batches containing multiple different modulation factors, where every said batch refers to a series of consecutive wave edges. The PS has internal selection circuits, which select and use consecutive modulation factors for modulating phases of consecutive edges.

(32) In order to allow higher wave generation frequencies, 2 parallel processing circuits are implemented which use consecutive phase1/phase2 circuits for synthesizing phases of consecutive odd/even edges.

(33) As it is shown in the FIG. 6, said basic phase adjustments are loaded to the Periodical Number Buffer (PNB) and to the Fractional Number Buffer (FNB); where they remain unchanged until PS internal Modulations Counter (MC) reaches MC=0 condition.

(34) On the other hand, said modulation factors M1, M2-M6, M7 are shifted left, by one factor for every new edge, in the Phase Modulation Buffers (PMB1/PMB2) for providing consecutive modulation factor needed for a next edge in the left end of the PMB1/PMB2.

(35) Such updated modulation factor is then added to the basic phase adjustments and resulting modulated phase adjustments are downloaded into the Periodical Number Registers (PNR1/PNR2) and into the Fractional Number Registers (FNR1/FNR2).

(36) In order to synthesize an actual position of a new edge of the synthesized waveform; said downloaded modulated phase adjustments need to be added to a current edge position, and the results of said addition are downloaded into the Periods Counters (PC1 or PC2) and into the Fractional Selection Register (FSR)

(37) The Sequential Clocks Generator (SCG) and Output Selection Circuits (OSC) are shown in the FIG. 4 and have been already explained in the Subsection “6. General Definition of Phase Synthesizer” of the previous section.

(38) The Clock Selection Register ½ (CSR1/CSR2) specifies a sub-clock which will be selected in a forthcoming Phase2/Phase1 cycle of the reference clock fsync.

(39) In order to remain settled during a whole next cycle of the fsync, the CSR1/CSR2 registers are loaded by the early sub-clocks of the present Phase2/Phase1 cycle of the fsync.

(40) The CSR1/CSR2 are loaded:

(41) with a current content of the Fractional Selection Register (FSR) (shown in FIG. 6), if the LD_C1 or LD_C2 (Load Counter 1 or Load Counter2) signal indicates that an end period of the present phase adjustment is indicated by the C2E or C1E (Counter 2 End or Counter 1 End) accordingly (see FIG. 2 and FIG. 3);

(42) with the binary value 2.sup.S−1=R+1 which exceeds ranges of the 1.sup.st Clock Selector (1CS) and the 2.sup.nd Clock Selector (2CS) and results in none of selectors outputs being activated and none of sub-clocks being selected during a following phase cycle.

(43) The Timing Control (TC) circuits are shown in FIG. 5, the resulting Timing Diagram of Phase Synthesizer (TDPS) is shown in FIG. 7, and TC operations are explained below.

(44) The LD_C1 signal enables loading of the Period Counter 1 (PC1) with a number of periods which the previous stages of the Synchronous Sequential phase Processor (SSPP) have calculated for the current phase adjustment.

(45) Said download deactivates/activates the C1E signal if a downloaded value is (bigger than 1)/(equal to 1) accordingly. When said downloaded value is bigger than 1, the ClEN=1 enables decreasing the PC1 content by 1 at every leading edge of the Clk1.1 until the PC1=1 condition is achieved and is detected by the PC1-OVF Detector which signals it with the C1E=1 signal. It shall be noticed that: when a fractional part of a phase adjustment calculated in said FSR reaches or exceeds a whole period of the fsync, the overflow bit FSR(OVF)=1

(46) is activated and switches the PC1=1-OVF DETECTOR from said 1 detection mode to a 0 detection mode which prolongs current phase adjustment by 1 fsync period.

(47) The phase 2 control circuit is driven by the C1E and by the LD_C1, and controls phase 2 operations with signals LD_C2, LD_RE2, LD_BU2; as it is further explained below: The first C1E activation period generates the LD_C2 signal, and is followed by setting the LDR2_FF which terminates the LD_C2. The LD_C2 signal; enables loading of PC2 with a periods number for the next phase adjustment, enables loading of the FSR with a fractional adjustment for the next phase adjustment, and enables a downloading of the FSR to the CSR1 or to the CSR2. The LDR2_FF=1 generates the leading edge of the LD_RE2 signal. The LD_RE2 signal clocks in; a new modified fractional adjustment to the Fractional Number Register 2 (FNR2), and a new modified periodical adjustment to the Periodical Number Register 2 (PNR2). When the period number loaded by the LD_C2 is counted down to its end by the PC2, the C2E signal activates the LD_C1 similarly as the C1E has activated the LD_C2. The LD_C1=1 resets both the C1E and the LDR2_FF in the next cycle; The LDR2_FF=0 generates the leading edge of the LD_BU2 signal. The LD_BU2 signal clocks in; a previous PMB2 content shifted left by S+1 bits, or a new PM[M6,M4,M2,M0] content from the PCU when the Modulations Counter (MC) is decoded as MC=0.

(48) The phase 1 control circuit is similarly driven by the C2E and by the LD_C2; and similarly generates the LD_C1, LD_RE1, LD_BU1 signals for controlling phase1 operations.

(49) The only differences in the phase 1 versus phase 2 operations, are specified below: The LD_BU1 signal clocks in a decreased by 1 value to the MC which is the modulo 4 counter. The DECODER MC=0 generates the MC=0 signal which selects provided by the PCU; the Periodical Number (PN)/the Fractional Number (FN)/the Phase Modifications (PM) to be loaded into the Periodical Number Buffer (PNB/the Fractional Number Buffer/the Phase Modifications Buffer 1 (PMB1) by the leading edge of the LD_BU1. The DECODER MC=1 generates the MC=1 _INT interrupt signal to the PCU, which informs the PCU that all the above mentioned phase adjustment parameters have been already stored in the PS buffers and can be replaced by new phase adjustment parameters.

(50) 2. Heterodyne Timing Configuration

(51) FIG. 3 shows the heterodyne timing configuration (HTC) according to the preferred embodiment. The HTC integrates both Digital PLLs (DPLLs) and Analog PLLs (APLLs) into a single CMOS ASIC, with the exception of the external VCXO which provides a stable clock (Fil_LocClk) having very low phase jitter.

(52) Said APLL mode of the HTC is described below.

(53) The Reference Selector (RFS) is programmed by the PCU to select one of the external reference clocks (Ext_RefClk). Such selected external reference clock is applied to the reference input of the Analog Phase Detector (APD) which drives the Loop Filter of the VCXO which provides the stable low jitter output f_filter.

(54) The Fil_OutClk; drives the Output PLL (OUT_PLL), and is connected to the fsync/L input of the Return Clock Synthesizer (RET_PS) which is implemented with the PS embodiment described in the previous section.

(55) The RET_PS synthesizes the RetClk, which is connected to the APD return input.

(56) It shall be noticed that very wide ranges of the RET_PS frequency adjustments, enable the PCU to tune the RET_PS to any frequency which the selected external reference may have.

(57) Said OUT_PLL generates the output reference clock (OutRef) which drives the Output Clocks Generator (OCG) which provides all the major HTC output clocks OutClk(T:1).

(58) Since the OCG consists of frequency dividers having very tightly controlled and well matched propagation delays, all the OutClk(T:1) are phase aligned with the Fil_OutClk and between themselves.

(59) The DPLL mode of the HTC is described below.

(60) The Fil_OutClk signal is programmed to be selected by the RFS for the APD reference signal, and the RET_PS provides the APD return signal which is synthesized from the same Fil_OutClk signal. One of the external reference waveforms (Ext_RefWfm) is selected by a selector controlled by the PCU for being processed by the NFED providing the filtered reference waveform (Fil_RefWfm), which is connected to the Time Stamp Decoder (TSD) and to the FPD1.

(61) Local oscillator fixed output (LocOsc) is connected to the FPD2.

(62) Both frame phase detectors FPD1/FPD2 shall use the high frequency sampling clock (SampClk) for accurate digital measurements of the PhaErr1 and the PhaErr2.

(63) Said sampling clock is generated by the frequency multiplier OutRefxR from the OutRef generated by the OUT_PLL.

(64) Since the OutClk(T:1) output clocks are phase aligned with the OUT_PLL output clock OutRef, and the sampling clock SampClk is phase aligned with the OutRef as well; the SampClk is phase aligned with the HTC output clocks OutClk(T:1).

(65) The FPD1 measures a phase error between the sampling clock SampClk and the Ext_RefWfm, as Δφ1=φ_samp−φ_wfm.

(66) The FPD2 measures a phase error between the sampling clock SampClk and the LocOsc, as Δφ2=φ_samp−φ_osc.

(67) The PCU reads the measured phase errors and uses the RET_PS to introduce digital phase displacements between the APD reference input and the APD return input which will drive the VCXO based PLL for providing required phase transfer functions between the Fil_OutClk and the Ext_RefWfm.

(68) Since the Fil_OutClk drives the OUT_PLL which has much higher BW than the VCXO PLL and the OUT_PLL determines phase of the OutClk, the OutClk implements the same phase transfer function as the Fil_OutClk.

(69) Based on the measurements of Δφ1 and Δφ2, the PCU calculates said Periodical Numbers (PN), Fractional Numbers (FN) and Phase Modifications (PM) which need to be provided to the Return Phase Synthesizer (RET_PS); in order to achieve a preprogrammed transfer function between the HTC output clocks and the selected DPLL reference clock Ext_RefWfm.

(70) HTC free-run and hold-over modes use the above described DPLL mode configuration, as it is described below.

(71) In the free-run mode; the PCU uses the phase error measurements for calculating phase differences which need to be inserted via the RET_PS for providing said OutClk locking to the local oscillator LocOsc.

(72) In the hold-over mode; the PCU inserts phase differences via the RET_PS which cause the OutClk to maintain its last frequency displacement versus the LocOsc.

(73) 3. Noise Filtering Edge Detectors

(74) The preferred embodiment implements the above defined general components of the NFED and is shown in FIG. 8, FIG. 9 and FIG. 10.

(75) The NFED comprises over-sampling and capturing of consecutive wave-form intervals in specifically dedicated consecutive wave registers, wherein odd intervals are written into the wave register 1WR and even intervals are written into the wave register 2WR. Therefore incoming stream of samples is split into the two parallel processing phases (sometimes named as parallel synchronous pipelines). The first processing phase begins in the wave register 1WR and the second begins in the register 2WR. Such splitting into 2 parallel phases obviously doubles cycle time available in the sequential stages following the register 1WR and in the stages following the 2WR as well.

(76) A sequential clock generation circuit (SCG) shows a method for splitting a steady stream of mutually overlapping sub-clocks spaced by a gate delay only into sub-sets of sub-clocks active during their dedicated phases only and non-active during all other phases. Such subsets are obviously used for providing timing for their dedicated phases.

(77) The wave register 1WR is further split into 2 parallel sub-phases and the 2WR is split into other 2 parallel sub-phases, for the purpose of quadrupling cycle time available in said sub-phases (see the FIG. 8 showing the wave registers 1WR, 2WR followed by the wave buffers 11WB, 12WB, 21WB, 22WB).

(78) In order to provide all wave samples needed for the filtering edge detection along a whole wave buffer, the NFED includes rewriting: the end part 2WR(R:(R-M+1) of the wave register 2WR, into the front parts 11WB(M:1), 12WB(M:1) of the wave buffers 11WB,12WB; the end part 1WR(R:(R-M+1) of the wave register 1WR, into the front parts 21WB(M:1), 22WB(M:1) of the wave buffers 21WB,22WB.

(79) The preferred embodiment is based on the assumptions listed below: the wave registers 1WR and the 2WR are 15 bit registers (i.e. R=14); the rising edge mask REM(M:0) and the falling edge mask FEM(M:0) are 8 bit registers (i.e. M=7) and the PCU loads the same masks equal to 00001111 to both mask registers; the rising edge threshold RET is loaded with 0110 (6 decimal), and the falling edge threshold FET is loaded with 0010 (2 decimal);

(80) The digital filter arithmometers 21DFA1/22DFA1/11DFA1/12DFA1 perform all the comparison functions, between the edge mask registers REM/FEM and the waveform buffers 21WB/22WB/11WB/12WB involving the edge threshold registers RET/FET, with the 3 basic operations which are further explained below.

(81) The first operation is performed on all the waveform bits and involves the edge mask bits as it is specified below:

(82) For every waveform buffer consecutive bit WB.sub.k the surrounding bits WB.sub.k−4, WB.sub.k−3, WB.sub.k−2, WB.sub.k−1, WB.sub.k, WB.sub.k+1, WB.sub.k+2, WB.sub.k+3 are logically compared with the mask bits B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.M and the resulting 8 bit binary expression BE.sub.k(7:0) is created as equal to;

(83) BE.sub.k(0)=(WB.sub.k−4=B.sub.0), BE.sub.k(1)=(WB.sub.k−3=B.sub.1), BE.sub.k(2)=(WB.sub.k−2=B.sub.2),

(84) BE.sub.k(3)=(WB.sub.k−i=B.sub.3), BE.sub.k(4)=(WB.sub.k=B.sub.4), BE.sub.k(5)=(WB.sub.k+1=B.sub.5),

(85) BE.sub.k(6)=(WB.sub.k+2=B.sub.6), BE.sub.k(7)=(WB.sub.k+3=B.sub.7).

(86) The second operation adds arithmetically all the bits of the binary expression BE.sub.k(7:0) and the resulting edge proximity figure EPF.sub.k is calculated as equal to EPF.sub.k=BE.sub.k(0)+BE.sub.k(1)+BE.sub.k(2)+BE.sub.k(3)+BE.sub.k(4)+BE.sub.k(5)+BE.sub.k(6)+BE.sub.k(7) which shall amount to a 0-8 decimal number. During the first and the second operations: all bits of any particular wave buffer have their specific edge proximity figures calculated at the same time during a cycle assigned for one of the arithmometers 21DFA1/22DFA1/11DFA1/12DFA1 attached to that buffer.

(87) Since there are 15 bits in every wave buffer every such arithmometer consists of 15 parallel micro-arithmometers, wherein each such micro-arithmometer performs operation on an 8 bit edge mask and on 8 bit wave region.

(88) Since this arithmometers perform the most intense processing, said quadrupling of cycle time by gradual splitting from the original 1 phase into the present 4 parallel phases was needed.

(89) The third operation performs functions explained below: In order to carry the same level from the last bit of the previous phase DFR1 into the following bits of the present phase digital filter register2 (DFR2), the last bit DFR1(R) of the previous DFR1 is always rewritten into the carry bit DFR1(C) of the present DFR1 and is used by the digital filter arithmometer2 (DFRA2) to fill front bits of the DFR2 with the same level as the last bit of the previous phase DFR1. The verification is made if the EPF.sub.k indicates a rising edge condition by exceeding the content of the rising edge threshold RET(T:0). Consequent detection of the EPF.sub.k>RET=6 condition, sets to level=1 the corresponding DFR1.sub.k bit of the DFR1 and all the remaining bits of the present DFR1 until a falling edge is detected as it is explained below. The verification is made if the EPF.sub.k indicates a falling edge condition by being smaller than the content of the falling edge threshold FET(T:0). Consequent detection of the EPF.sub.k<RET=2 condition, sets to level=0 the corresponding DFR1.sub.k bit of the DFR1 and all the remaining bits of the present DFR1 unless a rising edge is detected as it explained above.

(90) The digital filter arithmometers 21DFA2/22DFA2/11DFA2/12DFA2 perform; the inter-phase continuation of filling front bits of the present phase register in accordance with the level set in the last bit of the previous phase, followed by said edge displacement which compensates for duty cycle distortions due to inter-symbol interference (ISI), etc.

(91) The edge displacement comprises the 3 basic operations described below. Any DFR1 rising edge, indicated by a level 0 to 1 transition, is shifted left by a number of bits specified by a content of the rising edge displacement register (RED(D:0)) loaded by the PCU in accordance with its filtering algorithms. Any DFR1 falling edge, indicated by a level 1 to 0 transition, is shifted left by a number of bits specified by a content of the falling edge displacement register (FED(D:0)) loaded by the PCU in accordance with its filtering algorithms. In order to propagate said displacement operations from the present phase to the previous phase; the propagated sign of the edge bit (DFR2(Sp)) and the propagated bits (DFR2(Dp:0)), are calculated by the DFR2 and are written down into the DFR2 extension DFR2(Sp,Dp:0).

(92) In order to propagate said displacement operations from the next phase DFR2 into end bits of the present phase digital filter register3 (DFR3); the propagated sign of the edge bit and the propagated displaced bits DFR2(Sp,Dp:0) from the next phase, are used by the digital filter arithmometer3 (DFRA3) to fill end bits of the digital filter register3 (DFR3) with the correctly displaced bits propagated form the next phase to the present phase.

(93) 4. Wave-Form Screening and Capturing

(94) The wave-form screening and capturing (WFSC) of screened out intervals is performed by the circuits which are shown in FIG. 11 and the timing diagrams of the WFSC are shown FIG. 12.

(95) The WFSC allows the PCU to perform screening and capturing of the incoming signal, for timing intervals which correspond roughly to a period of a single data bit, based on a content of the wave buffers 11WB, 12WB, 21WB and 22WB.

(96) The WFSC allows the PCU to screen signal quality of incoming wave form, by applying programmable screening functions using programmable data masks, as it is listed below: content of said wave buffers can be verified for compliance or non compliance with a mask provided by the PCU, based on verification functions and verification tolerances which are programmed by the PCU; if any wave buffer verification detects preset by PCU screening out criteria to be met, the corresponding content of a wave buffer is captured and made available for PCU for further analysis; in addition to the wave buffer capturing, a number of said screened out results will be counted and communicated to the PCU as well.

(97) In addition to the above mentioned screening; the WFSC allows also the PCU to select arbitrarily a content of any of the wave buffers during any particular time slot; for being captured and made available for analysis by the PCU.

(98) The above mentioned signal screening is implemented by the WFSC, as it is explained below. The Mask Detection Arithmometrs (11MDA and 12MDA) for the WFSC are positioned similarly as the DFAs of the NFED.

(99) The second stage uses the mask detection arithmometers 11MDA/12MDA for identifying wave-forms which are beyond usually acceptable range defined by the PCU.

(100) The programmable control unit (PCU) determines logical and/or arithmetical processing which the 11MDA/12MDA shall perform, by pre-loading the detection control register (DCR) with a control code applied as the DCR(P:0) to the 11MDA/12MDA.

(101) Additionally the PCU determines the mask DMR(R:0) which the captured data 11WB(R: 0)/12WB(R:0) shall be processed against, by pre-loading the detection mask register (DMR). The 11SEL signal equal to I/O selects; the 11WB(R:0)/12WB(R:0) to be downloaded to the phase one detected data buffer (1DDB) by the clock 1Clk2 (see FIG. 11 and FIG. 12), if the11DET/12DET indicate detection of a pre-selected mask by the mask detection arithmometer 11DMA/12DMA.

(102) At the beginning of the next time frame, which has 128 phase1 cycles, the last captured 1DDB content is further downloaded to the phase1 data register (1DDR) by the clock signal 1Clk3/128. Number of said mask detections is counted in the mask counter buffer (1MCB), as it is explained below: at the beginning of every time frame which has 128 phase1 cycles, the 1MCB is reset/preset to 0/1 if there isn't/is a mask detection for the first cycle of the frame which is signaled by the 1PHA/128ena=1; the 1MCB is increased by 1/kept the same, if there is/isn't any mask detection during a particular phase1 cycle; at the beginning of the next time frame, the 1MCB is downloaded to the phase1 mask counter register (1MCR) and the output of the 1MCB>0 decoder (MCB>0 DEC) is downloaded to the 1MCR(P) bit, by the 1Clk3/128.

(103) Said 1DDR and 1MCR are read by the PCU, when the beginning of the next frame is communicated to the PCU by the phase1 128.sup.th clock enable signal (1PHA/128ena) and the above mentioned 1MCR(P)=1 indicates that at least 1 detection of a pre-selected mask occurred during the previous frame.

(104) Said PCU controlled capturing of a wave buffer content is implemented, as it is explained further below.

(105) The sample number register (SNR) is loaded by the PCU: with a phase number defined as phase1/phase2 if the SNR(0) is set 0/1, and with a particular phase cycle number in a time frame defined by SNR(7:1) bits.

(106) Since there are 2 phases with 128 cycles per time frame, SNR(7:0) bits define 1 of 256 sampling cycles for having its wave buffer captured and made available for a further analysis by the PCU. Said SNR is downloaded into the phase1 sample number buffer (1SNB) at the beginning of a time frame by the first phase1 clock of the frame 1Clk2/128.

(107) At the beginning of a time frame: the phase1 sample number counter (1SNC) is set to 0, since the 1PHA/128ena selects 0 to be loaded into the 1SNC by 1Clk2.

(108) During every other cycle of the time frame: 1 is added to the SNC content, since the 1PHA/128ena is inactive during all the next cycles of the frame.

(109) The 1SNC(7:1) and the 1SNB(7:1) are being compared by the logical comparator (Log.Comp.), which produces the Eq=1 signal when their identity is detected.

(110) Said Eq=1 enables the 1SNB(1)=0/1 to select the 11WB(R:0)/12WB(R:0) in the 3:1 selector (3:1 SEL), for capturing in the phase1 sampled data buffer (1SDB).

(111) At the beginning of the next time frame, the output of the 3:1 SEL is additionally captured in the phase1 sampled data register (1SDR) by the signal 1Clk3/128.

(112) Said 1SDR is read by the PCU, which is notified about availability of the requested sample by the signal 1PHA/128ena.

(113) 5. Receiver Synchronization Techniques

(114) Functional block diagram of inherently stable synchronization system is provided in FIG. 13 wherein recovery of OFDM receiver sampling clock Cs and local symbol frame Fls is shown. More detailed implementation and partitioning of such system is shown in FIG. 15.

(115) Samples from an OFDM composite signal interval, long enough to comprise entire OFDM symbol, are processed by the Synchronous Sequential Processor (defined in Subsection 8 of SUMMARY OF THE INVENTION) which uses Cs as its reference clock (see FIG. 13 and FIG. 14).

(116) Sub-clocks of such reference clock, driving such SSP used for OFDM processing, may not need to facilitate phase resolution matching single gate delay. Therefore a conventional delay line, consisting of serially connected flip-flops driven by a frequency multiplier of the reference clock, can be sufficient to generate such lower resolution sub-clocks instead of using the delay line consisting of serially connected gates with all elaborate timing involved.

(117) However independent of any delay line implementation, SSP architecture guaranties that all SSP micro-operations are performed in exactly predefined time windows within known time displacements to such reference clock. Therefore SSP processing delay measured from entering last sample of an interval processed to producing the final result of such interval processing is totally predictable.

(118) As specified therein, SSP includes real-time processing stages of incoming wave-form and a programmable computing unit (PCU) for supporting any adaptive signal processing dependent of previous micro-operations results or wave-form content.

(119) SSP uses interrupts to acquire results of such PCU adaptive processing, while PCU produces such results in advance before they are needed (see also Subsection 8 of SUMMARY OF THE INVENTION). Therefore SSP can use such results in predefined time windows synchronizing known sequence of said SSP micro-operations, while PCU accommodates all changes of processing time and/or algorithms.

(120) Since such SSP is used to detect composite frame boundary, resulting boundary detection delay Tbd is known very accurately.

(121) Despite such accurate Tbd, composite signal distortions due to channel interference and inherent problems of conventional methods for composite frame boundary detection, shall be expected to cause noticeable errors in boundary detection times which convey into receiver time offset errors.

(122) However said predictable Tbd of the boundary detection signal Sbd (see FIG. 13) facilitates generation of the referencing frame Fr, re-timed by the sampling clock Cs.

(123) Such Fr is applied to the digital frequency detector (DFD) which produces frequency offset estimate Fos by subtracting said expected nominal number of sampling clocks form the number of sampling clocks counted during said referencing frame interval.

(124) As such DFD arrangement facilitates measuring frequency offset within referencing frame intervals corresponding to multiple periods of OFDM composite frame, such prolongation of frequency sensing intervals multiples accuracy of frequency offset measurements (see also time-diagrams and Note 4 in FIG. 13).

(125) Such much more accurate frequency offset Fos applied to the frequency locked loop FLL, enables generation of said sampling clock with frequency by one order more accurate and thus prevents any inter-bin leaking endangering IDFT/IFFT processing of OFDM composite frame.

(126) Such DFD/FLL configuration offers other significant advantages as well over phase locked loops PLL used conventionally in OFDM receivers. Such configuration assures much faster frequency acquisition when connecting to new composite signal source, and avoids PLL instability when exposed to an unknown spectrum of phase noise caused by unpredictable channel interference and inaccuracy of conventional phase measurements methods.

(127) Inherent stability is achieved by combining such stable sampling clock generation by FLL with the phase synthesizer PS (defined in Subsections 5 and 6 of SUMMARY OF THE INVENTION) working in the open ended configuration (shown in FIG. 13 and FIG. 15).

(128) Such open ended PS configuration applies modifications of referencing frame phase with programmable phase steps defined by sub-clocks of sampling clock, wherein such sub-clocks are generated internally in PS from flip-flop based delay line driven by FreqDetClk produced by the frequency multiplier Samp-Clk×R of sampling clock Cs.

(129) Such PS method (defined in the Subsections 5 and 6 mentioned above) uses the same SSP architecture as that used for the boundary detection discussed above. Similarly sub-clocks driving such SSP do not need to facilitate phase resolution matching single gate delay. Coincidentally sub-clocks used by PS for defining programmable phase steps applied to the local symbol frame do not need to provide phase resolution matching single gate delay either. Therefore the same sub-clocks, generated by conventional flip-flop based delay line, can be used for both; for driving said SSP utilized by SP, and for defining said programmable phase steps.

(130) Such conventional delay line is used as consisting of serially connected flip-flops driven by the frequency multiplier Samp-Clk×R of the sampling clock wherein the sampling clock represents frequency multiplication of the local symbol frame (utilized as the reference clock by the SF_PS) by said nominal number Nn. Consequently total frequency multiplication factor amounts to R×Nn.

(131) PCU produces such steps number definition before it is requested by PS and places such steps number on its output PCU-OUT in response to PS interrupt MC_INT.

(132) PCU shown in FIG. 15 receives; the referencing frame Fr, the sampling clock Cs, the boundary delay time Tbd and said frequency offset Fos.

(133) When synchronization acquisition is initialized, Fr presets an PCU internal Fr phase register to Nn-Tbd, wherein Nn is said nominal number expected for reference frame interval covering single OFDM symbol.

(134) As such presetting of PCU internal Fr register provides said programmable presetting of numerical first edge specific for the FPD (see Subsection 7 of SUMMARY OF THE INVENTION), it utilizes such PCU function for upgrading this DPD to provide such FPD functionality.

(135) At the same time the referencing frame prompts the PCU_OUT register to provide definition of such Nn-Tbd phase step, and prompts the symbol frame phase synthesizer SF_PS to generate PCU interrupt MC=1_INT and to implement such Nn-Tbd phase step.

(136) Consequently the first edge of the Local Symbol Frame Fls is generated with the Nn-Tbd phase displacement to the initializing edge of Fr.

(137) Dependent of specifics of a particular PS design;

(138) such generation of Fls first edge displaced by Nn-Tbd phase step to the referencing frame edge, can include resetting the phase of frame generated previously by PS before such phase step is applied.

(139) As PCU receives consecutive Fos values defining displacements of next detected Fr boundaries to consecutive expected boundaries, it keeps updating track record of previous Fos and said Fr phase register with such Fos values in order to maintain continues record of Fr phase changes and present status.

(140) In order to avoid uncontrolled phase transients resulting from an accumulation of DFD digitization errors, only DFD design eliminating such digitization errors accumulation can be used (such DFD is defined in U.S. Pat. No. 6,864,672 by Bogdan).

(141) Similarly PCU keeps also track record of previous phase steps defined to SF_PS and keeps updating its internal Fls phase register defining present phase of the local symbol frame.

(142) Based on such data about Fr phase and Fls phase, PCU calculates a number of said phase steps which the referencing frame phase needs to be modified by, in order to implement a preprogrammed phase/frequency transient function between the local symbol frame and the referencing frame.

(143) Such configuration enables accurate phase frequency control reducing phase noise and jitter.

(144) In addition to the SF_PS, configuration shown in FIG. 15 uses another phase synthesizer FLL_PS placed in the return path of the analog phase locked loop APLL used to modify sampling clock frequency in order to minimize said frequency offset between the sampling clock and said composite signal clock.

(145) Additionally to the data mentioned above, PCU keeps track of phase steps introduced into the sampling clock Cs via the FLL_PS. Therefore PCU has all the data defining frequency and phase relations between the sampling clock Cs and the crystal oscillator clock LX_Clk, and between the LX_Clk and said composite frame clock outlined by the referencing frame clock.

(146) Similar configuration shown in FIG. 16 utilizes LX_Clk, instead of the sampling clock, for producing said Freq.DetClk. Therefore PCU scales said nominal number Nn, proportionally to frequency offset between the LX_Clk and the composite clock outlined by the Fr, before utilizing such Nn for measuring Fos with the DFD referenced by the LX_Clk.

(147) Synchronization System with improved stability shown in FIG. 14 and FIG. 17, includes:

(148) using the additional DPD for measuring time offset (phase error) Trf-ls between the referencing frame Fr and the symbol frame Fls, instead of relying entirely on PCU subroutines explained above;

(149) such Trf-ls is supplied to PCU which uses it to maintain close control of such time offset (phase error) by defining appropriate phase steps to the symbol frame synthesizer SF_PS.

(150) Such synchronization system can facilitate even closer control of such phase offset, while it implicates lesser stability improvements and simpler phase frequency control less efficient in reducing phase/frequency transients.

(151) High Accuracy FLPS shown in FIG. 18 represents high performance synchronization system which will be needed in future high speed wireless/wireline OFDM and mobile receivers, including next generations of ADSL, WiFi or WiMAX.

(152) Such system facilitates multiplying low frequency (down to 30 kHz) of XTAL oscillator (LX_Clk) by very high factor (up to 50 000), in order to utilize very inexpensive low frequency crystal cuts for producing highly stable local oscillator clock.

(153) Such frequency multiplier utilizes DFD1 for measuring frequency error XTALos between the XTAL oscillator clock (LX_Clk) and the sampling clock Cs represented by the FreqDetClk, wherein the frequency multiplication factor R shall be lower than 10 in order to avoid stability problems in SOC PLL implementations.

(154) PCU reads the frequency error XTALos and produces sequence of PCU-OUT signals supplied to the frequency locked loop phase synthesizer (FLL_PS) located in the reference path of VCXO based analog PLL having very low bandwidth (for example 0.1-1 kHz).

(155) Such PCU_OUT signals cause said FLL_PS to insert phase errors which drive said analog PLL into producing sampling clock Cs maintaining pre-programmed frequency relation to the LX_Clk.

(156) Since such PCU-OUT signals represent sequence of small phase steps applied with frequency by several orders higher than that of analog PLL bandwidth, resulting Cs jitter shall be very low.

(157) Consequently, such system multiplies low frequency of highly accurate inexpensive local XTAL oscillator (LX_Clk), in order to produce sampling clock frequency with accuracy much better than 1 ppm.

(158) Such system utilizes SCCS concept of multiplying low frequency of highly accurate inexpensive local XTAL oscillator, in order to produce sampling clock frequency with accuracy much better than 1 ppm (see Subsections 1, 2 and 3 of SUMMARY OF THE INVENTION).

(159) This system combines all the advanced features, explained above for the FLPS shown in FIG. 15, combined with such highly efficient frequency multiplication method.

(160) 6. Direct Synthesis of Receiver Clock

(161) The direct FLPS (DFPLS) configuration, implementing the DSRC, and DFPLS timing are shown in FIG. 19A and FIG. 19B and DFLPS operations are described below.

(162) A phase error between the referencing signal frame and corresponding to it oscillator frame is measured by the frame phase detector (FPD).

(163) Such FPD is explained in greater detail in subsection “7. Frame Phase Detector” of “SUMMARY OF THE INVENTION”.

(164) The FPD utilizes an oscillator clock counter (OscClk_Counter) for counting oscillator clocks (OscClk) occurring during a particular period of the referencing signal frame.

(165) PCU performs operations listed below. 1. Reading such OscClk_Counter, in response to the read counter request (RdCounter_Req) sent by FPD. 2. Calculating the measured phase error (MeasPhaError) by subtracting a nominal number of oscillator clocks (N) expected during the referencing frame period, from the actually counted number of oscillator clocks represented by the OscClk_Counter; i.e.:
MeasPhaErr=OscClk_Counter−N 3. Estimation of a predicted phase error (PredPhaErr), introduced to a phase of the synthesized frame by slowly changing factors such as: a drift of oscillator frequency caused by temperature or aging or a combination of the frequency drift and slow fluctuations of oscillator clock phase.

(166) The PredPhaErr can be estimated as equal to an averaged sum of the measured phase errors added over a set of consecutive M periods of the referencing frame preceding a next synthesized frame; ie.:

(167) $\mathrm{PredPhaErr}=\frac{1}{M}\underset{i=1}{\overset{i=M}{.Math.}}\mathrm{MeasPhaErr}\left(i\right)$

(168) wherein: MeasPhaErr(i)=OscClk_Counter(i)−N

(169) Since the FPD allows adding consecutive contents of the oscillator clock counter without accumulation of their digitization errors, the summation shown above can be calculated with a total error limited to 2 counter digitization errors no matter how large the M number is.

(170) The PredPhaErr is calculated for and applied to amend phase of the next synthesized frame only and it is calculated again for every following synthesized frame using a set of M measured phase shifted accordingly. Averaged summation of preceding measured phase errors stored in a first in first out (FIFO) memory may be applied to produce such PredPhaErr.

(171) The number M shall be selected as large enough to enable sufficiently accurate estimation of the frequency drift contributing a more steady component to the PredPhaErr. However, the M shall be also selected as small enough to enable sufficiently agile estimation of frequency & phase fluctuations of the oscillator clock contributing less steady components to the PredPhaErr.

(172) Such balanced choice of M shall be made based on an analysis of frequency/phase characteristics of the referencing frame and the oscillator clock.

(173) Such choice of M may be supported by applying known methods of statistical analysis of the measured phase errors such as Allen or Hadamard Deviations.

(174) Such PredPhaErr used for amending the last synthesized frame/next synthesized frame will be named further on as Last_PredPhaErr/Next_PredPhaErr accordingly.

(175) Consequently, predicted phase amendments applied to the last/next synthesized clock frames, can be specified as:
Last_PredPhaAmend=Last_PredPhaErr,
Next_PredPhaAmend=Next_PredPhaErr 4. Calculation of a next variable phase amendment (Next_VarPhaAmend) applied to the next synthesized clock frame, in order to eliminate a phase tracking error introduced to the previous synthesized clock frame (Last_PhaTraErr) by a part of the previous measured phase error (Last_MeasPhaErr) which has not been compensated by the previous predicted phase error (Last_PredPhaErr); i.e.:
Next_VarPhaAmend=Last_PhaTraErr;
wherein
Last_PhaTraErr=Last_MeasPhaErr−Last_PredPhaErr

(176) It shall be noted that since the above dependencies are applied consistently to all consecutive synthesized clock frames, any accumulation of phase tracking errors is prevented as it is shown below. It can be seen below that an eventual accumulated phase tracking error would be equal to:
Last_AccPhaTraErr=Penult_AccPhaTraErr+Last_MeasPhaErr−Last_PredPhaAmend−Last_VarPhaAmend.
However
Last_VarPhaAmend=Penult_AccPhaTraErr.
Therefore:
Last_AccPhaTraErr=Last_MeasPhaErr−Last_PredPhaAmend=Last_PhaTraErr.

(177) The above equation confirms that the last accumulated phase tracking error is defined entirely by the last measured phase error reduced by the last predicted phase amendment without accumulating any residual error from previous synthesized clock frames. 5. PCU calculates a next periodical phase amendment (Next_PerPhaAmend) by adding the next variable phase amendment to the next predicted phase amendment, i.e.:
Next-PerPhaAmend=Next_PredPhaAmend+Next_VarPhaAmend 6. PCU calculates control signals implementing the subtraction of the next periodical phase amendment from the phase of the next frame of synthesized clock produced by the PS, by distributing such subtraction gradually over the next period of the synthesized clock frame.

(178) Wherein the tracking error calculated by and controlled by the PCU enables maintaining of phase alignment of the synthesized clock to the external referencing signal, since such tracking error shows an accurate amount of a phase difference between the referencing signal and the synthesized clock expressed in local oscillator sub-clocks.

(179) The predicted phase amendment has been exemplified above as derived by using the moving average filter designed for detecting components of the measured phase errors related mainly to the frequency misalignment or difference.

(180) However, the DSRC invention utilizes particular said predicted phase amendments for reducing phase tracking errors of corresponding particular periods of the synthesized frame only, as the phase tracking errors of the corresponding periods are always eliminated by said variable phase amendments applied to periods of the synthesized frame following the corresponding periods.

(181) Therefore within the DSRC invention a wide variety of periodic phase amendments may be chosen as most suitable for reducing phase tracking errors of the synthesized frame in specific applications, without any departure from the DSRC principle of operation securing continuous control and minimization of the phase tracking errors.

(182) Such periodic phase amendments remaining within the scope of the DSRC invention, may be derived by using a combination of different filters suited for detecting phase errors components corresponding to different frequency/phase distortions characteristic for specific applications.

(183) In particular, such combination of different filters may include the moving average filter presented above and a weighted moving average filter.

(184) This weighted moving average filter may be designed for detecting components of the measured phase errors corresponding to a spread of the boundary detection delays (Tbd) occurring when the referencing frame is recovered from received data carrying signal (such as OFDM composite signal).

(185) The DSRC invention presented herein contributes methods, systems and circuits for a variety of implementations of synchronization solutions which include but are not limited to those mentioned above.

(186) Such implementations of the DSRC designed as suitable for different applications, will be obvious for persons having ordinary skill in the art. More specific description of DSRC configurations shown in FIG. 19A, FIG. 19B and FIG. 19C and some of their applications, are provided below. The phase synthesizer (PS) produces the synthesized clock based on PCU control signals (PCU_OUT) communicating such periodical phase amendments (PerPhaAmend) implementing phase synthesis functions specified above. Such phase synthesizer and its internal operations and circuits are explained in greater detail in the subsection “6 Phase Synthesizer” of “SUMMARY OF THE INVENTION”, and in the subsection “1. Phase Synthesizer” of “DESCRIPTION OF EMBODIMENTS”. DSRC initialization presetting or eliminating start-up phase offset of the synthesized clock versus the referencing signal, can be implemented with PCU operations listed below: an initial validation of the referencing signal frame received by PCU; resetting internal PCU register containing said phase tracking error, sending PCU-OUT content presetting to correct initial values all PS internal phase & frequency modification registers including PNB, FNB and PMB. Other initialization methods, securing such offsets elimination, may include: presetting said PCU register containing accumulated tracking error to a desirable initial offset value; and sending specific initial reset request signal (InitResetReq) to the PS which shall respond by resetting its all internal phase & frequency modification registers including PNB, FNB and PMB. Such DSRC can be used in OFDM receivers, as it is explained below: the oscillator clock mentioned above can be provided by the Local XTAL Clock shown in FIG. 16 (see also subsection “5. Receiver Synchronization Techniques” of “DESCRIPTION OF EMBODIMENTS”; said referencing signal frame can be provided by the Referencing Frame shown in FIG. 13 and FIG. 14 as the OFDM frame recovered from the Composite Frame; the Local Symbol Frame (shown in the FIG. 13 and FIG. 14) can be generated as containing Nsynth synthesized clocks, if an initial offset equal to the boundary detection delay Tbd is preset using one of the initialization methods exemplified above. One of said other direct synchronization solutions utilizing feed-forward hardware configuration shown in FIG. 19A (for securing even further size and power reductions critical for mass consumer markets), is described below: A non-cumulative (i.e. free of uncontrolled phase transients) periodical measurement of phase error between said referencing signal phase and said oscillator clock phase, is conducted by said phase/frequency analysis (PFA) system implemented with the Frame Phase Detector (FPD) and said PCU subroutine calculating such measured phase error (by subtracting said nominal expected number of oscillator clocks from an actually counted number of such clocks); PCU utilizes such phase error for calculating a control signal (PCU_OUT) which can distribute a phase amendment compensating such phase error gradually over a time period between consecutive phase error measurements; PCU applies such control signals (gradually distributing this phase amendment) to the phase synthesizer (PS), in order to produce said synthesized clock tracking phase of the reference signal with phase ramps approximating phase steps corresponding to such periodical phase amendments; wherein such replacement of phase steps with ramps, reduces high frequency jitter in the synthesized clock. Still other even simpler direct synchronization solution utilizing such feed-forward configuration, can be accomplished as it is explained below: a non-cumulative (i.e. free of uncontrolled phase transients) periodical measurement of phase error between said referencing signal phase and said oscillator clock phase, is conducted by a phase/frequency analysis (PFA) system implemented with the Frame Phase Detector (FPD) and said PCU subroutine calculating such measured phase error (by subtracting said nominal expected number of oscillator clocks from an actually counted number of such clocks); PCU utilizes such phase error for producing a control signal driving the phase synthesizer (PS) into adding a phase amendment (compensating such phase error) to the synthesized clock phase in order to produce a synthesized clock phase tracking such reference signal phase; such very simple inherently stable configuration enabled by the PS can secure very flexible conversion of the local oscillator frequency into the frequency of synthesized clock free of uncontrolled phase transients, and tracking reference signal phase with the phase of synthesized clock free of waveform glitches; resulting phase steps (introduced to the synthesized clock for compensating phase errors measured with FPD), can be still acceptable in less demanding mass markets where cost and power reductions are the most critical. The configuration shown in FIG. 19C shows the DSRC supplemented with the additional FPD (named FPD2) connected to the referencing signal frame and to the synthesized clock (SynthClk), in order to measure phase errors between the synthesized clock frame and the referencing frame. Such measurements may be used by the PCU for periodical standby verifications if an intermittent malfunction of the hardware or unpredictable frequency/phase perturbations are not disrupting the process of maintaining correct said phase tracking error free of uncontrolled phase transients. If such disruption happens the PCU may conduct a recovery process reconstructing an accurate phase tracking process or just reset the DSRC system and restart entire phase tracking process.

CONCLUSION

(187) In view of the above description of the invention and associated drawings, other modifications and variations will now become apparent to those skilled in the art based on the teachings contained herein. Such other modifications and variations fall within the scope and spirit of the present invention.