PRE-DRIVEN BOOTSTRAPPING DRIVERS

Abstract

A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Claims

1. A bootstrapping gate driver for a high side FET having a drain terminal connected to a supply voltage, a source terminal connected to an output, and a gate terminal, the bootstrapping gate driver comprising: an input for receiving a control signal; and a bootstrap capacitor electrically connected between the voltage source and ground when the control signal corresponds to a charging phase, thereby charging the capacitor to a charged voltage, the capacitor being electrically connected to the gate terminal of the high side FET such that, when the control signal corresponds to a driving stage and the bootstrap capacitor is electrically disconnected from ground, the charged voltage on the bootstrap capacitor is applied to the gate of the high side FET to provide an output voltage at the output; a pre-driven charging circuit comprising a pre-driven FET having a drain terminal connected to the supply voltage, a source terminal connected to the gate terminal of the high side FET, and a gate, wherein the gate of the pre-driven FET receives a logic inversion of the control signal in advance of the input for pre-charging the bootstrap capacitor during a pre-driven period before the control signal at the input corresponds to the charging phase.

2. The bootstrapping gate driver of claim 1, further comprising a resistor electrically connected between the voltage source and the gate of the high side FET to decrease static current consumption.

3. The bootstrapping gate driver of claim 1, further comprising a low side FET for turning off the high side FET, the low side FET having a drain terminal connected to the source of the high side FET and the output, a gate terminal connected to the input, and a source terminal connected to ground.

4. The bootstrapping gate driver of claim 1, wherein the bootstrapping gate driver is cascaded and comprises at least one additional stage of charging circuitry including a charging FET and an additional bootstrap capacitor.

5. The bootstrapping gate driver of claim 4, wherein the charging FET is smaller than the high side power FET, and wherein the bootstrap capacitor is smaller than the additional bootstrap capacitor of the additional stage of charging circuitry.

6. The bootstrapping gate driver of claim 5, further comprising further additional stages, each having a respective charging FET pre-driven by the pre-driven FET.

7. The bootstrapping gate driver of claim 1, further comprising at least one additional bootstrap capacitor electrically connected in parallel with the bootstrap capacitor between the voltage source and ground when the control signal corresponds to a charging phase, thereby charging the bootstrap capacitor and the at least one additional bootstrap capacitor in parallel, the bootstrap capacitor and the at least one additional bootstrap capacitor being electrically connected in series between the gate and the source of the high side FET when the control signal corresponds to a driving stage.

8. The bootstrapping gate driver of claim 1, wherein the FETs of the bootstrapping gate driver are gallium nitride (GaN) FETs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify correspondingly throughout and wherein:

[0027] FIG. 1 is a schematic of a conventional bootstrapping gate driver circuit.

[0028] FIG. 2 is a schematic of a conventional cascaded bootstrapping gate driver circuit.

[0029] FIG. 3 is a schematic of a pre-driven bootstrapping gate driver circuit in accordance with a first embodiment of the present invention.

[0030] FIG. 4 is a timing diagram of the pre-driven gate driver circuit of FIG. 3.

[0031] FIG. 5 is a schematic of a cascaded pre-driven bootstrapping gate driver circuit in accordance with a second embodiment of the present invention.

[0032] FIG. 6 is a schematic of the pre-driven bootstrapping gate driver circuit applied to the multi-voltage bootstrapping gate driver circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.

[0034] FIG. 3 shows a pre-driven bootstrapping gate driver circuit in accordance with a first embodiment of the present invention.

[0035] To reduce the total capacitance required in the bootstrapping gate driver circuit of FIG. 1, the gate-to-source voltage of the high side (pull-up) FET 394, V.sub.GS_394, is pre-driven initially to a pre-driven voltage, V.sub.GPD, such that less charge from the bootstrap capacitor 380 is required to charge up the gate-to-source voltage (V.sub.GS_394) of the high side FET to the final desired voltage.

[0036] For example, if the gate-to-source capacitance of high side FET 394 is C.sub.GS_394, bootstrap capacitor 380 is charged to V.sub.dd initially, and the initial gate-to-source voltage of V.sub.GS_394 is V.sub.GPD, then the final gate-to-source voltage of V.sub.GS_394 given as V.sub.GS_394 (F) will be:

[00001]${\text{V}}_{\text{GS\_394}}\left(\text{F}\right)=\left({\text{V}}_{\text{dd}}\cdot {\text{C}}_{\text{BS380}}+{\text{V}}_{355}\cdot {\text{C}}_{\text{GS\_394}}\right)\text{/}\left({\text{C}}_{380}+{\text{C}}_{\text{GS\_394}}\right)$

[0037] If the desired V.sub.GS_394 (F) is 0.9.Math.V.sub.dd, and V.sub.GBD is about 0.3.Math.V.sub.dd, then the required C.sub.BS394 can be calculated to be 6.Math.C.sub.GS_394, which is 33.3% reduction from the required C.sub.BS394 (~9.Math.C.sub.GS_394) in FIG. 1.

[0038] To pre-drive the gate-to-source voltage of FET 394 (V.sub.GS_394), pre-driven FET 385 is added and coupled to the gate of high side FET 394. Pre-driven FET 385 is driven by the input b′, which is the logic inversion of the input, but happens slightly earlier as shown.

[0039] As shown in the timing diagram of FIG. 4, when input b′ turns high at the beginning of the pre-driven period, pre-driven FET 385 in FIG. 3 will start charging the voltage at node 355. When the input goes to approximately 0V at the end of the pre-driven period, the voltage at node 355 will be charged to the pre-driven voltage, V.sub.GPD, which is higher than 0V. Then the gate-to-source capacitance of FET 394 (C.sub.GS_394) will continue to be charged by the bootstrap capacitor 380. At the same time, pre-driven FET 385 will be turned on and the output will be driven to V.sub.dd. Since the output is driven to V.sub.dd, the voltage at node 370 (and hence, the voltage at node 355) will be driven above V.sub.dd.

[0040] Depending on the length of the pre-driven period, the maximum voltage at node 355 is limited to approximately (V.sub.dd - V.sub.T), where V.sub.T is the threshold voltage of pre-driven FET 385 in FIG. 3. The pre-driven current, I.sub.385, will be gradually reduced to zero when the voltage at node 355 increases to approximately (V.sub.dd - V.sub.T).

[0041] When the voltage at node 355 in FIG. 3 is approximately (V.sub.dd - V.sub.T), the pre-driven FET 385 is turned off. Thus, when the voltage at node 355 goes even higher due to the voltage on bootstrap capacitor 380, the charge on the bootstrap capacitor 380 will not be discharged to V.sub.dd by the pre-driven FET 385.

[0042] If the voltage at node 355 in FIG. 3 at the end of the pre-driven period is slightly greater than V.sub.T, pre-driven FET 385 will be just started to turn on. For a higher voltage at node 355 before the end of the pre-driven period, the pre-driven FET 385 will start to turn on earlier, but pre-driven FET 385 may not have a large gate-to-source voltage. As a result, pre-driven FET 385 may not be fully turned on with a larger output current. Hence, the output may suffer with a slow initial rise time.

[0043] If the voltage at node 355 in FIG. 3 is approximately equal to V.sub.T at the end of the pre-driven period, I.sub.385 will still be non-zero. Together with the charge released from bootstrap capacitor 380, the voltage at node 355 will be charged up faster, leading to a shorter turn-on time for pre-driven FET 385 and hence, an overall faster rise time at the output.

[0044] When input b′ and the input go back to low and high, respectively, the voltage at node 355 and the output will be driven to logic low. Then, the bootstrap capacitor 380 will be recharged to V.sub.dd, getting ready for the next period of the output going from low to high.

[0045] FETs 320, 335, 375, 392 and 394 in FIG. 3 are preferably enhancement mode GaN FET semiconductor devices, which are monolithically integrated onto a single semiconductor die with the other components of system 300. GaN FETs switch more quickly than conventional FETs and allow bootstrapping gate driver 390 to turn high side FET 394 on and off more quickly than a similar system implementing other FETs, such as MOSFETs.

[0046] Referring now to FIG. 5, the pre-driven technique can be applied to the cascaded bootstrapping driver circuitry of FIG. 2. In this second embodiment of the invention, where like reference numbers in the 500′s of FIG. 4 represent corresponding elements in the 300′s of FIG. 3 and 200′s of FIG. 2, the pre-driven FET 585, is coupled to the gate of the final driving FET, high side FET 594.

[0047] Although only one cascade stage 550 of cascaded driver 590 is shown in FIG. 5, additional pre-driven FET stages can also be added to the preceding cascaded stage(s).

[0048] The pre-driven period is defined approximately by the high-to-low delay of the inverter 535. Inverter can be implemented using a bootstrapping stage similar to FIGS. 1 and 2.

[0049] Referring to FIG. 6, the pre-driven bootstrapping gate driver circuitry of the present invention can also be applied to the multi-voltage bootstrapping driver topology described in co-pending Application No. 18/062,698, the disclosure of which is incorporated by reference, where the final high side (pull-up) FET 694, and FET 665 between bootstrap capacitors 680 and 645, are both pre-driven by pre-driven FET 685, such that the sizes of the bootstrap capacitors can be further reduced.

[0050] The pre-driven bootstrapping drivers of the present invention have the following features and advantages:

[0051] The area of the bootstrap capacitors is usually the dominant area for bootstrapping drivers implemented in GaN technology. The pre-driven bootstrapping driver circuitry of the present invention allows the size of the bootstrap capacitors to be reduced.

[0052] The pre-driven bootstrapping driver circuitry of the present invention can be used in conjunction with other bootstrapping driver circuits, including cascaded bootstrapping driver circuits and multi-voltage bootstrapping driver circuits, as described in connection with FIGS. 5 and 6, respectively.

[0053] When the pre-driven voltage is adjusted to about the threshold voltage of the FET (approximately equal to 0.3.Math.V.sub.dd to 0.4 .Math.V.sub.dd) by adjusting the pre-driven period, the size of the bootstrap capacitors can be reduced by 33.3% to 44.4%.

[0054] Since the multi-voltage bootstrapping driver circuit of FIG. 6 can reduce the bootstrap capacitor size by approximately 50%, the total capacitor size reduction is 66.7% to 72.2% when the pre-driven circuitry of the present invention and multi-voltage bootstrapping driver circuits are combined in a single bootstrapping driver.

[0055] Since the bootstrap capacitor for the final high side (pull-up) FET of a cascaded bootstrapping driver is reduced in size, the FETs for switching the bootstrap capacitors in the preceding cascaded stages can be reduced. As a result, the bootstrap capacitor in each cascaded stage can also have a smaller size. This leads to a further overall reduction of the driver size.

[0056] Smaller bootstrap capacitor sizes also lead to faster settling on all the cascaded bootstrapping stages. Hence, the proposed technique also improves the overall rise time of the driver.

[0057] The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.