ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL and LIQUID CRYSTAL DISPLAY DEVICE

Abstract

The present application discloses an array substrate, a liquid crystal display panel and a liquid crystal display device; a metal layer is designed to be added between the pixel electrode and the common electrode. The metal layer can form a first storage capacitor with the pixel electrode and formed a second storage capacitor with the common electrode, such as the dual storage capacitors to enlarge the storage capacitor to improve the flicker caused by TFT leakage, ensure the display effect, and the two storage capacitor are overlapped set, the aperture ratio of the pixel is not reduced.

Claims

1. An array substrate, comprising: a substrate; a TFT, a planarization layer, a common electrode, a passivation layer and a pixel electrode sequentially formed on the substrate characterized in that the array substrate further comprising a touch panel insulation layer and a metal layer sequentially formed between the common electrode and the passivation layer; wherein the metal layer is electrically connected to the pixel electrode and the drain electrode of the TFT separately; by overlapping disposed, the insulation portion of the touch panel insulation layer and the passivation layer sandwiched by the common electrode and the pixel electrode to form the first storage capacitor; and by overlapping disposed, the insulation portion of the touch panel insulation layer sandwiched by the metal layer and the common electrode to form the second storage capacitor.

2. The array substrate according to claim 1, wherein the planarization layer and the touch panel insulation layer have a first contact hole to expose the drain electrode of the TFT and the metal layer is electrically connected to the drain electrode via the first contact hole; the passivation layer has a second contact hole to expose the metal layer and the pixel electrode is electrically connected to the metal layer via the second contact hole.

3. The array substrate according to claim 2, wherein a portion of the metal layer is corresponding to locate above the TFT, and another portion of the metal layer is in a stripe type and corresponding to formed above the data line of the array substrate.

4. The array substrate according to claim 2, wherein the TFT comprising a shading metal layer, a buffer layer, a polycrystalline semiconductor layer, an insulating layer, a gate electrode, a dielectric isolation layer, and a source-drain electrode layer formed by a source electrode and a drain electrode.

5. The array substrate according to claim 4, wherein the array substrate further comprising a first conductive layer formed in the same layer and disposed in intervals with the gate electrode of the TFT on the insulating layer; wherein the first conductive layer is located below the drain electrode, the dielectric isolation layer has a third contact hole to expose the first conductive layer, the first conductive layer is electrically connected to the drain electrode via the third contact hole; the array substrate further comprising a second conductive layer formed in the same layer and disposed in intervals with the shading metal layer on the substrate; the second conductive layer is located below the first conductive layer; the buffer layer has a fourth contact hole to expose the second conductive layer, the second conductive layer is electrically connected to the polycrystalline semiconductor layer via the fourth contact hole, by overlapping disposed, the insulation layer sandwiched by the polycrystalline semiconductor layer and the first conductive layer to form a MIS storage capacitor.

6. The array substrate according to claim 5, wherein the second conductive layer is across the effective display area of the array substrate, and is electrically connected to the common electrode in the peripheral area of the effective display area.

7. The array substrate according to claim 2, wherein the TFT comprising a gate electrode, a buffer layer, a polycrystalline semiconductor layer, a dielectric isolation layer, and a source-drain electrode layer formed by a source electrode and a drain electrode.

8. The array substrate according to claim 7, wherein the array substrate further comprising a first conductive layer formed in the same layer with the source-drain electrode layer of the TFT and disposed in intervals on the dielectric isolation layer, the first conductive layer is located under the drain electrode, the dielectric isolation layer has a third contact hole to expose the first conductive layer, the first conductive layer is electrically connected to the drain electrode via the third contact hole. the array substrate further comprising a second conductive layer formed on the same layer with the gate electrode of the TFT and disposed in intervals on the substrate, wherein the second conductive layer is located below the first conductive layer, the insulating layer has a fourth contact hole to expose the second conductive layer, the second conductive layer is electrically connected to the polycrystalline semiconductor layer via the fourth contact hole, by overlapping disposed, the dielectric isolation layer sandwiched by the polycrystalline semiconductor layer and the first conductive layer to form a MIS storage capacitor of the array substrate.

9. The array substrate according to claim 8, wherein the second conductive layer is across the effective display area of the array substrate, and is electrically connected to the common electrode in the peripheral area of the effective display area.

10. A liquid crystal display panel, comprising the array substrate according to claim 1.

11. A liquid crystal display device comprising a liquid crystal display panel and a light source module to provide the backlight to the liquid crystal display panel, wherein the liquid crystal display panel is according to claim 10.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or prior art, the following figures will be described in the embodiments are briefly introduced. It is obvious that the drawings are merely some embodiments of the present application, those of ordinary skill in this field can obtain other figures according to these figures without paying the premise.

[0018] FIG. 1 is a cross-sectional view of the structure of the liquid crystal display panel of one embodiment of the present application;

[0019] FIG. 2 is a schematic view of the structure of the pixel of one embodiment of the liquid crystal display panel illustrated in FIG. 1;

[0020] FIG. 3 illustrated the equivalent circuit of the pixel structure illustrated in FIG. 2;

[0021] FIG. 4 is a schematic view of the structure of the pixel zone of the array substrate of the first embodiment of the present application;

[0022] FIG. 5 is a cross-sectional view of the structure along the A-A′ line of the pixel zone illustrated in FIG. 4;

[0023] FIG. 6 is a schematic view of the structure of the pixel zone of the array substrate of the second embodiment of the present application;

[0024] FIG. 7 is a schematic view of the structure of the pixel zone of the array substrate of the third embodiment of the present application;

[0025] FIG. 8 is a cross-sectional view of the structure of MIS storage capacitor illustrated in FIG. 7;

[0026] FIG. 9 is a C-V curve of the MIS storage capacitor illustrated in FIG. 8;

[0027] FIG. 10 is a schematic view of the structure of the pixel zone of the array substrate of the fourth embodiment of the present application; and

[0028] FIG. 11 is a cross-sectional view of the structure of the liquid crystal display device of one embodiment of the present application.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] Embodiments of the present application are described in detail with the technical matters, structural features, achieved objects, and effects with reference to the accompanying drawings as follows. It is clear that the described embodiments are part of embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments to those of ordinary skill in the premise of no creative efforts obtained should be considered within the scope of protection of the present application.

[0030] Specifically, the terminologies in the embodiments of the present application are merely for describing the purpose of the certain embodiment, but not to limit the invention. Examples and the claims be implemented in the present application requires the use of the singular form of the book “an”, “the” and “the” are intend to include most forms unless the context clearly dictates otherwise. It should also be understood that the terminology used herein that “and/or” means and includes any or all possible combinations of one or more of the associated listed items.

[0031] FIG. 1 is a cross-sectional view of the structure of the liquid crystal display panel of one embodiment of the present application. As illustrated in FIG. 1, the liquid crystal display panel 10 of the present embodiment includes a color filter substrate, referred to as a CF substrate 11, and an array substrate (a thin film transistor substrate, referred to as a TFT substrate 12 formed opposite and spaced. And a liquid crystal (liquid crystal molecules) 13 filled between the two substrates, the liquid crystal 13 are in the liquid crystal cell formed by the overlapped array substrate 12 and the color filter substrate 13.

[0032] Combined referring to the FIG. 2 illustrated the schematic view of the structure of the pixel of the liquid crystal display panel 10. The array substrate 12 includes a plurality of data lines D formed along the column direction, a plurality of scan lines G formed along the row direction and a plurality of pixel regions P defined by the scanning line G and the data line D. Wherein each pixel region P is connected to a corresponding data line D and a corresponding scanning line G. Each scanning line G is connected to a gate driver 21 to provide a scan voltage to each pixel region P. Each data line D is connected to a source driver 22 to provide a gray scale voltage to each pixel region P. Further combining referring to FIG. 3 illustrated the equivalent circuit of the pixel structure. The array substrate 12 includes a thin-film transistor, TFT, a storage capacitor C.sub.st and a liquid crystal capacitor C.sub.lc. The liquid crystal capacitor C.sub.lc is formed by the pixel electrode located in the pixel region P, the common electrode located in the liquid crystal display panel 10, and the liquid crystal 13 between the two electrodes.

[0033] According to the display principle of the liquid crystal display panel 10, by input scan voltage to the scan lines G, the TFTs in the same row are simultaneously turned on, and the TFTs in the next row are simultaneously turned on after a certain time, and so on. Since the time to turn on each row of the TFTs is relatively short, the time to charge liquid crystal capacitor C.sub.lc and control the liquid crystal 13 deflected is shorter, it is difficult to achieve the response time of the liquid crystal 13. The storage capacitor C.sub.st can maintain the voltage of the pixel region P after the TFT is turned off, so as to provide response time to the liquid crystal 13.

[0034] The different to the conventional technology is the storage capacitor C.sub.st in the embodiment of the present invention includes two storage capacitors, i.e., a first storage capacitor C.sub.st1 and a second storage capacitor C.sub.st2 illustrated in FIG. 5.

[0035] Combined referring to FIGS. 4-5, the array substrate includes a substrate 120 and a plurality of layer structures sequentially formed on the substrate 120: a shading metal layer M.sub.0, a buffer layer 121, a polycrystalline semiconductor (polycrystalline silicon, P—Si) layer 122, an insulating layer, also known as a gate insulation layer, GI 123, a first metal layer M.sub.1, a dielectric isolation layer, also known as an interlayer dielectric isolation, ILD layer 124, a second metal layer M.sub.2, a planarization layer, PLN 125, a common electrode 126, a touch panel insulation layer, TPIL 127, a third metal layer M.sub.3, a passivation layer, PV layer 128 and a pixel electrode 129.

[0036] Wherein the second metal layer M.sub.2 includes a first zone Z.sub.1 and a second zone Z.sub.2 formed in the same layer and disposed in intervals on the dielectric isolation layer 124. The second metal layer M.sub.2, the first metal layer M.sub.1, the polycrystalline semiconductor layer 122, and the insulating layer 123 between the spaces hold by each other and the dielectric isolation layer 124 form the TFT in the array substrate 12. It should be understood that the array substrate 12 in the embodiments of present invention can also include other layer structures, for example, the passivation layer 128 can include a first passivation layer 1281 and a second passivation layer 1282, and the first passivation layer 1281 is formed covering the common electrode 126, and the arrangement to dispose between the other layers in the structure can refer to the conventional technology, and not to be mentioned here.

[0037] The first metal layer M.sub.1, the first zone Z.sub.1 and the second zone Z.sub.2 of the second metal layer M.sub.2 are corresponding to a gate electrode, a source electrode and a drain electrode of the TFT. Since the shading metal layer M.sub.0 is located below the first metal layer M.sub.1, and the gate electrode of the TFT is located above the polysilicon semiconductor layer 122, the pixel region P of the present embodiment can be taken as a top gate pixel design.

[0038] In the present embodiment, the planarization layer 125 and the touch panel insulation layer 127 have a first contact hole O.sub.1 to expose the drain electrode of the TFT. The third metal layer M.sub.3 is electrically connected to the drain electrode (the second zone Z.sub.2 of the second metal layer M.sub.2) of the TFT via the first contact hole O.sub.1.

[0039] The passivation layer 128 has a second contact hole O.sub.2 to expose the third metal layer M.sub.3. The pixel electrode 129 is electrically connected to the third metal layer M.sub.3 via the second contact hole O.sub.2. By overlapping disposed, the insulation portion of the touch panel insulation layer 127 and the passivation layer 128 sandwiched by the common electrode 126 and the pixel electrode 129 to form the first storage capacitor C.sub.st1. By overlapping disposed, the insulation portion of the touch panel insulation layer 127 sandwiched by the third metal layer M.sub.3 and the common electrode 126 to form the second storage capacitor C.sub.st2.

[0040] The first storage capacitor C.sub.st1 is corresponds to the storage capacitor in the conventional technology. The second storage capacitor C.sub.st2 is the additional storage capacitor in the embodiment of the present application. That is, a metal layer M.sub.3 in the present embodiment of the present application is additional added between the pixel electrode and the common electrode, such that the array substrate has a dual storage capacitors, thereby increasing the storage capacitor of the liquid crystal display panel 10. To improve the flicker caused by TFT leakage, ensure the display effect, and the two storage capacitor are overlapped set, and the aperture ratio of the pixel is not reduced compared to the conventional technology.

[0041] Further, referring to FIG. 4 and FIG. 5, a portion of the added third metal layer M.sub.3 is corresponding to locate above the TFT, another portion of the third metal layer M.sub.3 is in a stripe type and corresponding formed above the data line D 12 of the array substrate 12, and does not reduce the aperture ratio of the pixel. Further, the other portion of the third metal layer M.sub.3 can further replace the black matrix, BM to achieve of shading.

[0042] Further, the touch panel insulation layer 127 is formed between the third metal layer M.sub.3 and the second metal layer M.sub.2. It can prevent the second metal layer M.sub.2 from being etched during etching and forming the third metal layer M.sub.3, and ensure the contact resistance of the electrically connection of the third metal layer M.sub.3 and the second metal layer M.sub.2 meet the design requirements. Wherein the material of the third metal layer M.sub.3 can be the same with each of the material of the the second metal layer M.sub.2 or the first metal layer M.sub.1, and it can be not the same.

[0043] An array substrate of the second embodiment is also provided in the present invention, to distinguish the difference of the description of the above-described embodiment, which the same reference numerals identical the same structural elements. Referring to FIG. 6, the different between the embodiment in FIG. 5 is the TFT includes a gate electrode (that is the first metal layer M.sub.1), a insulation layer 123, a polycrystalline semiconductor layer 122, a dielectric isolation layer 124 and a source-drain electrode layer formed by a source electrode and a drain electrode sequentially formed on the substrate 120. A shading metal layer M.sub.0 and a buffer layer 121 are nor formed on the array substrate 12. The gate electrode of the TFT is disposed below the polycrystalline semiconductor layer 122, that is the present invention is also applicable to a bottom gate pixel design of the array substrate 12.

[0044] FIG. 7 is a schematic view of the structure of the pixel zone of the array substrate of the third embodiment of the present application. In order to distinguish the difference of description of the above-described embodiment, which the same reference numerals identical the same structural elements. As illustrated in FIG. 7, the different between the embodiment in FIGS. 4-5 is:

[0045] The array substrate 12 further includes a first conductive layer M.sub.1 (the fourth zone Z.sub.4 shown in FIG. 7) formed in the same layer and disposed in intervals with the gate electrode of the TFT on the insulating layer 123. The first conductive layer M.sub.1 is located below the drain electrode. The dielectric isolation layer has a third contact hole O.sub.3 to expose the first conductive layer M.sub.1. The first conductive layer M.sub.1 is electrically connected to the drain electrode via the third contact hole O.sub.3. The array substrate 12 further includes a second conductive layer M.sub.0 (the sixth zone Z.sub.6 shown in FIG. 7) formed in the same layer and disposed in intervals with the shading metal layer M.sub.0 on the substrate 120. The second conductive layer M.sub.0 is located below the first conductive layer M.sub.1. The buffer layer 121 has a fourth contact hole O.sub.4 to expose the second conductive layer M.sub.0. The second conductive layer M.sub.0 is electrically connected to the polycrystalline semiconductor layer 122 via the fourth contact hole O.sub.4. By overlapping disposed, the insulation layer 123 sandwiched by the polycrystalline semiconductor layer 122 and the first conductive layer M.sub.1 to form the MIS (metal insulator semiconductor) storage capacitor C.sub.st3.

[0046] In other words, the first metal layer M.sub.1 of the present embodiment includes a third zone Z.sub.3 and a fourth zone Z.sub.4 disposed in intervals, the third zone Z.sub.3 of the first metal layer M.sub.1 is the gate electrode of the TFT, the fourth zone Z.sub.4 of the first metal layer M.sub.1 is the first conductive layer M.sub.1. The dielectric isolation layer 124 has a third contact hole O.sub.3 to expose the fourth zone Z.sub.4 of the first metal layer M.sub.1. The fourth zone Z.sub.4 of the first metal layer M.sub.1 is electrically connected to the second zone Z.sub.2 of the second metal layer M.sub.2 via the third contact hole O.sub.3 and receive the gray scale voltage from the second zone Z.sub.2 of the second metal layer M.sub.2. The shading metal layer M.sub.0 of the present embodiment includes a fifth zone Z.sub.5 and a sixth zone Z.sub.6.

[0047] The fifth zone Z.sub.5 is located below the third zone Z.sub.3, and the sixth zone Z.sub.6 is located below the fourth zone Z.sub.4. The buffer layer 121 has a fourth contact hole O.sub.4. The polycrystalline semiconductor layer 122 is electrically connected to the sixth zone Z.sub.6 of the shading metal layer M.sub.0 via the fourth contact hole O.sub.4. The sixth zone Z.sub.6 of the shading metal layer M.sub.0 is across the effective display area of the array substrate 12 (Active area, AA), and is connected to the common electrode 126 in the peripheral area of the effective display area to receive the common voltage from the common electrode.

[0048] In the present embodiment, by overlapping disposed, the insulation portion sandwiched by the polycrystalline semiconductor layer 122 and the fourth zone Z.sub.4 of the first metal layer M.sub.1 to form the MIS storage capacitor C.sub.st3 of the array substrate 12 and further enlarge the storage capacitor of the array substrate 12.

[0049] Combined referring to FIG. 8, when the side of the first conductive layer M.sub.1 side receiving negative gray voltage, the P—Si of the polycrystalline semiconductor layer 122 will be aggregated to form a hole 421. When the gray-scale voltage received by the first conductive layer M.sub.1 is from negative to positive, the region of the hole 421 may form a depletion layer 422, i.e., the upper layer of the P—Si may form the depletion layer 422, the depletion layer 422 can be reduce the capacitance of the MIS storage capacitor C.sub.st3. That is, the MIS storage capacitor C.sub.st3 of the present embodiment is corresponding to a variable capacitor. Further referring to the C-V (capacitance-voltage gray) curve illustrated in FIG. 9, when the gray-scale voltage is negative, the capacitance of the MIS storage capacitor C.sub.st3 is C.sub.1, when the gray-scale voltage is positive, the capacitance of the MIS storage capacitor C.sub.st3 is

C.sub.2=C.sub.1*C.sub.0/(C.sub.1+C.sub.0), wherein C.sub.0 is the capacitance between the depletion layer 422 and the first conductive layer M.sub.1. it can be understood that C.sub.1>C.sub.2, such as the capacitance of the MIS storage capacitor C.sub.st3 when receiving a negative gray scale voltage is larger than that of receiving a negative gray scale voltage. Due to a larger leakage of the TFT when the gray voltage is negative, the capacitance of the MIS storage capacitor C.sub.st3 is increased in the present embodiment to reduce the leakage of the TFT, thereby improving the influence of the leakage of the TFT. Such as to reduce the capacitance difference between the positive or negative gray voltage received by the MIS storage capacitor C.sub.st3, and further improve the occurrence of the flicker, ensure the performance of the display.

[0050] The present invention also provides an array substrate of the fourth embodiment, to distinguish the difference of the description of the above-described embodiment, which the same reference numerals identical the same structural elements. Referring to FIG. 10, the different between the embodiment in FIG. 6 is:

[0051] The array substrate 12 further includes a first conductive layer M.sub.2 (the portion of the second zone Z.sub.2 of the second metal layer M.sub.2 formed in the same layer with the source-drain electrode layer of the TFT and disposed in intervals on the dielectric isolation layer 124. The first conductive layer M.sub.2 is located under the drain electrode. The dielectric isolation layer 124 has a third contact hole O.sub.3 to expose the first conductive layer M.sub.2. The first conductive layer M.sub.2 is electrically connected to the drain electrode via the third contact hole O.sub.3. The array substrate 12 further includes a second conductive layer M.sub.1 (the portion of the fourth zone Z.sub.4 of the first metal layer M.sub.1) formed on the same layer with the gate electrode of the TFT and disposed in intervals on the substrate 120. The second conductive layer M.sub.1 is located below the first conductive layer M.sub.2. The insulating layer 123 has a fourth contact hole O.sub.4 to expose the second conductive layer M.sub.1. The second conductive layer M.sub.1 is electrically connected to the polycrystalline semiconductor layer 122 via the fourth contact hole O.sub.4. By overlapping disposed, the dielectric isolation layer 124 sandwiched by the polycrystalline semiconductor layer 122 and the first conductive layer M.sub.2 to form the MIS storage capacitor C.sub.st3 of the array substrate 12.

[0052] In other words, the second zone Z.sub.2 of the second metal layer M.sub.2 of the present embodiment further includes a portion in the dielectric isolation layer 124. The first metal layer M.sub.1 includes a third zone Z.sub.3 and a fourth zone Z.sub.4 formed in intervals. The third zone Z.sub.3 of the first metal layer M.sub.1 is the gate electrode of the TFT. The insulating layer 123 has a fourth contact hole O.sub.4 to expose the fourth zone Z.sub.4 of the first metal layer M.sub.1. The fourth zone Z.sub.4 of the first metal layer M.sub.1 is electrically connected to the polycrystalline semiconductor layer 122 via the fourth contact hole O.sub.4. By overlapping disposed, the dielectric isolation layer 124 sandwiched by the polycrystalline semiconductor layer 122 and the second zone Z.sub.2 of the second metal layer M.sub.2 to form the MIS storage capacitor C.sub.st3 of the array substrate 12. Wherein the gate electrode of the TFT is disposed below the polycrystalline semiconductor layer 122, i.e., the present invention is also applicable to a bottom gate pixel design of the array substrate 12.

[0053] The embodiment of the present invention also provides a liquid crystal display device 110 illustrated in FIG. 11. The liquid crystal display device 110 includes a liquid crystal display panel 10 described above and a light source module 111 to provide the light to the liquid crystal display panel 10. The liquid crystal display panel 10 can use fringe field switching, FFS technology. Since the liquid crystal display device 110 having the design of the array substrate 12 described above, and therefore also has the same advantages.

[0054] Above are embodiments of the present application, which does not limit the scope of the present application. Any modifications, equivalent replacements or improvements within the spirit and principles of the embodiment described above should be covered by the protected scope of the invention.